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authorMartin Braun <martin.braun@ettus.com>2022-03-14 14:07:16 +0100
committerAaron Rossetto <aaron.rossetto@ni.com>2022-03-28 12:54:07 -0700
commit7753371e8b3ce916335ff5dc81fe8f5333a7d3d3 (patch)
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docs: Update E320 docs
- Clarify purpose of 'enclosure' flag - Add section on clock and time sync, which the E31x section already has
Diffstat (limited to 'host/docs/usrp_e3xx.dox')
-rw-r--r--host/docs/usrp_e3xx.dox16
1 files changed, 15 insertions, 1 deletions
diff --git a/host/docs/usrp_e3xx.dox b/host/docs/usrp_e3xx.dox
index 5703c479b..1fe37d195 100644
--- a/host/docs/usrp_e3xx.dox
+++ b/host/docs/usrp_e3xx.dox
@@ -1039,7 +1039,7 @@ GPS-disciplined oscillator (GPSDO) on the board, the value "gpsdo" was named
such for better compatibility with code written for other devices.
The device provides a 3.3V supply voltage to an external antenna connected to the *GPS* port
-of your device. Note that this supply voltage is turned off in order to safe power upon destruction of the software object.
+of your device. Note that this supply voltage is turned off in order to save power upon destruction of the software object.
\subsection e31x_hw_gpio Internal GPIO
@@ -1300,6 +1300,15 @@ input, 10 MHz external clock reference.
The connectors are labeled RF A and RF B and are powered by the two channels of
AD9361 RFIC.
+\subsection e320_hw_sync Clock and Time Synchronization
+
+Unlike the E31x, but like most other USRPs, the USRP E320 has separate inputs for
+clock and time reference. There is no separate internal 10 MHz oscillator, when
+selecting an 'internal' reference, the GPSDO is used to create reference signals.
+
+The values 'internal' and 'gpsdo' are thus interchangeable and mean the same
+thing.
+
\subsection e320_gpio Front Panel GPIO
### Front Panel GPIO Connections
@@ -1334,6 +1343,11 @@ For example, to set your device to auto-boot, with TPM, and with fans, the flag
$ eeprom-set-flags 0x3
+The enclosure flag is typically set during the manufacturing process, and can be
+used to identify if the board has an enclosure is used. The firmware and thermal
+subsystems of this device also use this flag to load different default thermal
+settings (see the [SCU firmware code](https://github.com/EttusResearch/usrp-firmware/blob/a190641b349b1bfdbdd9f471f82613971e50e375/board/neon/board.c#L191-L205)).
+
\section e3xx_regmap E3XX FPGA Register Map
The following tables describe how FPGA registers are mapped into the PS.