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author | Sugandha Gupta <sugandha.gupta@ettus.com> | 2019-05-10 16:08:59 -0700 |
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committer | Brent Stapleton <brent.stapleton@ettus.com> | 2019-05-17 11:02:02 -0700 |
commit | 6a09f0b2758be6db90f0a5dff2b01deca31d4520 (patch) | |
tree | 46b41b53a3caefe43785cbcbedf36c50d461a723 /host/docs/usrp_e3xx.dox | |
parent | 902a003d68c4534f04172109328aef5a0d7ca64f (diff) | |
download | uhd-6a09f0b2758be6db90f0a5dff2b01deca31d4520.tar.gz uhd-6a09f0b2758be6db90f0a5dff2b01deca31d4520.tar.bz2 uhd-6a09f0b2758be6db90f0a5dff2b01deca31d4520.zip |
docs: e320: Add documentation for gpio and eeprom-flags
Diffstat (limited to 'host/docs/usrp_e3xx.dox')
-rw-r--r-- | host/docs/usrp_e3xx.dox | 34 |
1 files changed, 34 insertions, 0 deletions
diff --git a/host/docs/usrp_e3xx.dox b/host/docs/usrp_e3xx.dox index 9382388a3..ca471624a 100644 --- a/host/docs/usrp_e3xx.dox +++ b/host/docs/usrp_e3xx.dox @@ -1178,6 +1178,40 @@ input, 10 MHz external clock reference. The connectors are labeled RF A and RF B and are powered by the two channels of AD9361 RFIC. +\subsection e320_gpio Front Panel GPIO + +### Front Panel GPIO Connections + +| GPIO | Mini HDMI (Type C) | HDMI (Type A) | +|---------|----------------------|-----------------| +| Data[0] | Data 0+ - Pin 8 | Pin 7 | +| Data[1] | Data 0- - Pin 9 | Pin 9 | +| Data[2] | Clock 0+ - Pin 11 | Pin 10 | +| Data[3] | Clock 0- - Pin 12 | Pin 12 | +| Data[4] | CEC - Pin 14 | Pin 13 | +| Data[5] | SCL - Pin 15 | Pin 15 | +| Data[6] | SDA - Pin 16 | Pin 16 | +| Data[7] | Utility - Pin 17 | Pin 14 | + +\subsection e320_eeprom_flags EEPROM flags + +EEPROM flags can be set with + + $ eeprom-set-flags 0xFLAGS + +where FLAGS is the hex number that you can construct with the following table of bits: + +| Bit | Description | +|-----|-----------------------| +| 0 | Auto-boot (1=on) | +| 1 | Fan (1=present) | +| 2 | TPM (0=present) | +| 3 | Enclosure (1=present) | + +For example, to set your device to auto-boot, with TPM, and with fans, the flag value is 0x5, so + + $ eeprom-set-flags 0x5 + \section e3xx_regmap E3XX FPGA Register Map The following tables describe how FPGA registers are mapped into the PS. |