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| author | Josh Blum <josh@joshknows.com> | 2011-06-06 04:58:42 +0100 |
|---|---|---|
| committer | Josh Blum <josh@joshknows.com> | 2011-06-06 04:58:42 +0100 |
| commit | f239b8517b238923aacc161664857a7d7b830ab0 (patch) | |
| tree | cd2ea667b121e018b4b752569c101ffdb4c546c6 /host/docs/usrp_e1xx.rst | |
| parent | 01d85c733bd3220e6a44e5a9c132172462f85ef7 (diff) | |
| download | uhd-f239b8517b238923aacc161664857a7d7b830ab0.tar.gz uhd-f239b8517b238923aacc161664857a7d7b830ab0.tar.bz2 uhd-f239b8517b238923aacc161664857a7d7b830ab0.zip | |
usrp-e100: removed clockgen config stuff and docs
Diffstat (limited to 'host/docs/usrp_e1xx.rst')
| -rw-r--r-- | host/docs/usrp_e1xx.rst | 15 |
1 files changed, 0 insertions, 15 deletions
diff --git a/host/docs/usrp_e1xx.rst b/host/docs/usrp_e1xx.rst index fcaa57716..4ac9d133a 100644 --- a/host/docs/usrp_e1xx.rst +++ b/host/docs/usrp_e1xx.rst @@ -53,21 +53,6 @@ Example: uhd_usrp_probe --args="master_clock_rate=52e6" -^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ -Clock rate recovery - unbricking -^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ -It is possible to set a clock rate such that the UHD can no longer communicate with the FPGA. -When this occurs, it is necessary to use the usrp-e-utility to recover the clock generator. -The recovery utility works by loading a special pass-through FPGA image so the computer -can talk directly to the clock generator over a SPI interface. - -Run the following commands to restore the clock generator to a usable state: -:: - - cd <install-path>/share/uhd/usrp_e_utilities - ./usrp-e-utility --fpga=../images/usrp_e100_pt_fpga.bin --reclk - - ------------------------------------------------------------------------ Clock Synchronization ------------------------------------------------------------------------ |