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author | Ben Hilburn <ben.hilburn@ettus.com> | 2014-04-11 14:51:04 -0700 |
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committer | Ben Hilburn <ben.hilburn@ettus.com> | 2014-04-11 14:51:04 -0700 |
commit | dedf16ea795443f41edefbeb1eb77e2b91cb4691 (patch) | |
tree | 6627f42cbe0d595120621cf51fe505cb74cac525 /host/docs/usrp_b200.dox | |
parent | 87b068edddf5862f532dbc06e7a20106e524b581 (diff) | |
parent | 5268e0794b82fa4da095f2de9bf233e01e92ab1c (diff) | |
download | uhd-dedf16ea795443f41edefbeb1eb77e2b91cb4691.tar.gz uhd-dedf16ea795443f41edefbeb1eb77e2b91cb4691.tar.bz2 uhd-dedf16ea795443f41edefbeb1eb77e2b91cb4691.zip |
Merging Doxygen manual into 'master'.
Diffstat (limited to 'host/docs/usrp_b200.dox')
-rw-r--r-- | host/docs/usrp_b200.dox | 69 |
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diff --git a/host/docs/usrp_b200.dox b/host/docs/usrp_b200.dox new file mode 100644 index 000000000..77b20ed01 --- /dev/null +++ b/host/docs/usrp_b200.dox @@ -0,0 +1,69 @@ +/*! \page page_usrp_b200 USRP-B2x0 Series Device Manual + +\tableofcontents + +\section b200_features Comparative features list - B200 + +- Hardware Capabilities: + - Integrated RF frontend (70 MHz - 6 GHz) + - External PPS reference input + - External 10 MHz reference input + - Configurable clock rate + - Internal GPSDO option + - B210 Only: + - MICTOR Debug Connector + - JTAG Connector +- FPGA Capabilities: + - Timed commands in FPGA + - Timed sampling in FPGA + +\section b200_imgs Specify a Non-standard Image + +UHD software will automatically select the USRP B2X0 images from the +installed images package. The image selection can be overridden with the +`fpga` and `fw` device address parameters. + +Example device address string representations to specify non-standard +images: + + fpga=usrp_b200_fpga.bin + + -- OR -- + + fw=usrp_b200_fw.hex + +\section b200_mcr Changing the Master Clock Rate + +The master clock rate feeds the RF frontends and the DSP chains. Users +may select non-default clock rates to acheive integer decimations or +interpolations in the DSP chains. The default master clock rate defaults +to 32 MHz, but can be set to any rate between 5 MHz and 61.44 MHz. + +The user can set the master clock rate through the usrp API call +uhd::usrp::multi_usrp::set_master_clock_rate(), or the clock rate can be set through the +device arguments, which many applications take: : + + uhd_usrp_probe --args="master_clock_rate=52e6" + +\section b200_fe RF Frontend Notes + +The B200 features an integrated RF frontend. + +\subsection b200_fe_tuning Frontend tuning + +The RF frontend has individually tunable receive and transmit chains. On +the B200, there is one transmit and one receive RF frontend. On the +B210, both transmit and receive can be used in a MIMO configuration. For +the MIMO case, both receive frontends share the RX LO, and both transmit +frontends share the TX LO. Each LO is tunable between 50 MHz and 6 GHz. + +\subsection b200_fe_gain Frontend gain + +All frontends have individual analog gain controls. The receive +frontends have 73 dB of available gain; and the transmit frontends have +89.5 dB of available gain. Gain settings are application specific, but +it is recommended that users consider using at least half of the +available gain to get reasonable dynamic range. + +*/ +// vim:ft=doxygen: |