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| author | Vidush <vidush.vishwanath@ettus.com> | 2018-06-14 14:02:03 -0700 |
|---|---|---|
| committer | Martin Braun <martin.braun@ettus.com> | 2018-06-15 13:20:56 -0500 |
| commit | f9101d7cc7552755d597982eeccecabe88b8a022 (patch) | |
| tree | 20eccd60e63ba598153f1b900b5e4b786c4f77bb /host/docs/rd_testing.dox | |
| parent | 66e050bf85b252b41e654602f7af7266a3bd60ae (diff) | |
| download | uhd-f9101d7cc7552755d597982eeccecabe88b8a022.tar.gz uhd-f9101d7cc7552755d597982eeccecabe88b8a022.tar.bz2 uhd-f9101d7cc7552755d597982eeccecabe88b8a022.zip | |
Docs: x300 Functional Verification Procedure
Diffstat (limited to 'host/docs/rd_testing.dox')
| -rw-r--r-- | host/docs/rd_testing.dox | 15 |
1 files changed, 15 insertions, 0 deletions
diff --git a/host/docs/rd_testing.dox b/host/docs/rd_testing.dox index 855790b0b..2708944bf 100644 --- a/host/docs/rd_testing.dox +++ b/host/docs/rd_testing.dox @@ -503,6 +503,21 @@ In all cases, make sure UHD is compiled in 'Release' mode (highest optimization), and that all NIC and kernel are set to optimal (CPU governor, ring buffer settings, ...). +### X310/X300 +The X310/X300 tests depend on the FPGA image to be tested. + +#### HG +-Connect a 1GigE cable into port 0 and a 10GigE cable into port 1. +-The following command must pass: + + $ usrp_fpga_funcverif x3x0hg -a 192.168.40.2 -2 192.168.10.2 -p /path/to/examples + +#### XG +-Connect 10GigE cables to both ethernet ports. +-The following command must pass: + + $ usrp_fpga_funcverif x3x0xg -a 192.168.40.2 -2 192.168.30.2 -p /path/to/examples + ### N310/N300 The N310/N300 tests depend slightly on the type of FPGA image to be tested. |