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| author | Wade Fife <wade.fife@ettus.com> | 2020-08-24 21:32:20 -0500 |
|---|---|---|
| committer | Wade Fife <wade.fife@ettus.com> | 2020-08-31 08:16:43 -0500 |
| commit | 97cb396297828f57bba455a275966c58f1abce6e (patch) | |
| tree | 4c36cd95e401253c12ec6b49bc80b2aaa967dad8 /host/docs/rd_testing.dox | |
| parent | ccf5d1e0a06bf8d46d7bf6dc33a17e3228a1bff4 (diff) | |
| download | uhd-97cb396297828f57bba455a275966c58f1abce6e.tar.gz uhd-97cb396297828f57bba455a275966c58f1abce6e.tar.bz2 uhd-97cb396297828f57bba455a275966c58f1abce6e.zip | |
fpga: sim: chdr_stream_endpoint_tb improvements
- Adds test coverage for stream command and status packets
- Cleans up report output during simulation
- Stops clocks at the end of simulation, so chdr_stream_endpoint_tb can
be run directly instead of just chdr_stream_endpoint_all_tb
Diffstat (limited to 'host/docs/rd_testing.dox')
0 files changed, 0 insertions, 0 deletions