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authorAshish Chaudhari <ashish@ettus.com>2015-03-17 13:52:29 -0700
committerAshish Chaudhari <ashish@ettus.com>2015-03-17 13:52:29 -0700
commit6a34824ad10eaa2d2b642b959f278f6c4e326d6d (patch)
tree1aa582ee8e5cef716b59ec4deb3a8e5f4f532929 /host/docs/images.dox
parent5682321efa26bb97f5d0c37d8e9921fc11a9b923 (diff)
parent306b5243e12af0db493856ad8397abac9835db0c (diff)
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Merge branch 'master' into ashish/vivado
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diff --git a/host/docs/images.dox b/host/docs/images.dox
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@@ -85,7 +85,7 @@ depending on the device.
The build requires that you have a UNIX-like environment with `Make`.
Make sure that `xtclsh` from the Xilinx ISE bin directory is in your `$PATH`.
-- Xilinx ISE 14.4: USRP X3x0 Series, USRP B2x0
+- Xilinx ISE 14.7: USRP X3x0 Series, USRP B2x0
See `<uhd-repo-path>/fpga/usrp3/top/`.