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authorMartin Braun <martin.braun@ettus.com>2014-10-07 16:37:11 +0200
committerMartin Braun <martin.braun@ettus.com>2014-10-07 16:37:11 +0200
commit43428ca3fa21ec7ebac032becf036c6f7d8dd598 (patch)
tree662fd590b95ef8dfaa5e7546c7fc34e52f72641d /host/docs/images.dox
parentf79669dc21f7c7c9be972bd68f98a7f8e0e66f65 (diff)
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e300: Updated documentation
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1 files changed, 1 insertions, 1 deletions
diff --git a/host/docs/images.dox b/host/docs/images.dox
index 2b7894300..321452b87 100644
--- a/host/docs/images.dox
+++ b/host/docs/images.dox
@@ -80,7 +80,7 @@ depending on the device.
The build requires that you have a UNIX-like environment with `Make`.
Make sure that `xtclsh` from the Xilinx ISE bin directory is in your `$PATH`.
-- Xilinx ISE 14.7: USRP X3x0 Series, USRP B2x0
+- Xilinx ISE 14.4: USRP X3x0 Series, USRP B2x0
See `<uhd-repo-path>/fpga/usrp3/top/`.