rfnoc: add eRFNoC block builder to generate boiler plate Verilog

This is an initial generator for eRFNoC block.
The script generates the top level block, the shell module, a testbench, and a
Makefile as well as a Makefile.srcs.
To build a block from a yml file one has to invoke

python -c <config> -d <destination folder>

destination folder should be an in tree module folder located in
uhd-fpga/usrp3/lib/erfnoc/blocks
The build tool supports all interface types for control as well as data.

For each interface type there are three templates to generate the variable
block in the top level block and the shell

 * declare the wires
 * connect the wires
 * instantiate the modules

The first two are used in the shell module as well as in the top level block.
The last is for the shell only.

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