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authorWade Fife <wade.fife@ettus.com>2021-06-08 19:42:34 -0500
committerAaron Rossetto <aaron.rossetto@ni.com>2021-06-10 11:56:58 -0500
commitf706b89e6974e28ce76aadeeb06169becc86acba (patch)
tree565f5500bd5265753d0e34a634f0320103a98826 /fpga
parent791bafd09a30a041a0c6f65dbf395cc4e567911f (diff)
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fpga: sim: Add slave_idle() to PkgAxiStreamBfm.sv
Diffstat (limited to 'fpga')
-rw-r--r--fpga/usrp3/sim/rfnoc/PkgAxiStreamBfm.sv4
1 files changed, 4 insertions, 0 deletions
diff --git a/fpga/usrp3/sim/rfnoc/PkgAxiStreamBfm.sv b/fpga/usrp3/sim/rfnoc/PkgAxiStreamBfm.sv
index fd23e501c..14fcbc531 100644
--- a/fpga/usrp3/sim/rfnoc/PkgAxiStreamBfm.sv
+++ b/fpga/usrp3/sim/rfnoc/PkgAxiStreamBfm.sv
@@ -469,6 +469,10 @@ package PkgAxiStreamBfm;
return slave_stall_prob;
endfunction
+ // Determine if the slave interface is doing a transfer this clock
+ function logic slave_idle();
+ return !slave.tvalid;
+ endfunction
// Create separate processes for driving the master and slave interfaces
task run();