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author | michael-west <michael.west@ettus.com> | 2022-02-13 18:12:30 -0800 |
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committer | Wade Fife <wade.fife@ettus.com> | 2022-03-09 17:49:38 -0600 |
commit | b6c7e99830f10c21262247cafa3e077fe3f54119 (patch) | |
tree | 2c965b28e0e47baae5776ae8823e7c9c1962ad17 /fpga | |
parent | d9834b84f4e141a4ed0befcdbc814ab5148807e1 (diff) | |
download | uhd-b6c7e99830f10c21262247cafa3e077fe3f54119.tar.gz uhd-b6c7e99830f10c21262247cafa3e077fe3f54119.tar.bz2 uhd-b6c7e99830f10c21262247cafa3e077fe3f54119.zip |
fpga: rfnoc: Fix PPS edge detection
Make timekeeper module sample rising edge instead of falling edge of PPS
signal.
Signed-off-by: michael-west <michael.west@ettus.com>
Diffstat (limited to 'fpga')
-rw-r--r-- | fpga/usrp3/lib/rfnoc/utils/timekeeper.v | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/fpga/usrp3/lib/rfnoc/utils/timekeeper.v b/fpga/usrp3/lib/rfnoc/utils/timekeeper.v index 2b43c7ee6..436118861 100644 --- a/fpga/usrp3/lib/rfnoc/utils/timekeeper.v +++ b/fpga/usrp3/lib/rfnoc/utils/timekeeper.v @@ -244,7 +244,7 @@ module timekeeper #( pps_edge <= 0; end else begin pps_del <= pps; - pps_edge<= pps_del & ~pps; + pps_edge<= pps & ~pps_del; end end |