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authorJonathon Pendlum <jonathon.pendlum@ettus.com>2022-02-10 02:48:17 -0500
committerWade Fife <wade.fife@ettus.com>2022-02-10 18:11:41 -0700
commit8444f84add04f025b7e24855e0ba79446e615e01 (patch)
treebe0082e9d059ba7e816048a06a0cb5737018065a /fpga
parentcdcd39aeb508298e28e8a2a89db5ab9fefd70435 (diff)
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fpga: rfnoc: Add BLANK_OUTPUT to FIR filter block's parameters
Diffstat (limited to 'fpga')
-rw-r--r--fpga/usrp3/lib/rfnoc/axi_fir_filter.v2
-rw-r--r--fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_fir_filter/rfnoc_block_fir_filter.v15
-rw-r--r--fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_fir_filter/rfnoc_fir_filter_core.v14
3 files changed, 20 insertions, 11 deletions
diff --git a/fpga/usrp3/lib/rfnoc/axi_fir_filter.v b/fpga/usrp3/lib/rfnoc/axi_fir_filter.v
index 7efa60a97..5c63b1d94 100644
--- a/fpga/usrp3/lib/rfnoc/axi_fir_filter.v
+++ b/fpga/usrp3/lib/rfnoc/axi_fir_filter.v
@@ -23,7 +23,7 @@
// COEFFS_VEC - Vector of NUM_COEFFS values each of width COEFF_WIDTH to
// initialize coeffs. Defaults to an impulse.
// RELOADABLE_COEFFS - Enable (1) or disable (0) reloading coefficients at runtime (via reload bus)
-// BLANK_OUTPUT - Disable (1) or enable (0) output when filling internal pipeline
+// BLANK_OUTPUT - Disable (1) or enable (0) output when initially filling internal pipeline
// SYMMETRIC_COEFFS - Reduce multiplier usage by approx half if coefficients are symmetric
// SKIP_ZERO_COEFFS - Reduce multiplier usage by assuming zero valued coefficients in
// DEFAULT_COEFFS are always zero. Useful for halfband filters.
diff --git a/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_fir_filter/rfnoc_block_fir_filter.v b/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_fir_filter/rfnoc_block_fir_filter.v
index 346de8567..f05c05df1 100644
--- a/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_fir_filter/rfnoc_block_fir_filter.v
+++ b/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_fir_filter/rfnoc_block_fir_filter.v
@@ -13,11 +13,11 @@
// that are always set to zero, and using internal DSP slice registers to
// hold coefficients.
//
-// For the most efficient DSP slice inference use these settings, set
+// For the most efficient DSP slice inference use these settings, set
// COEFF_WIDTH to be less than 18.
//
// Parameters:
-//
+//
// COEFF_WIDTH : Coefficient width
//
// NUM_COEFFS : Number of coefficients / filter taps
@@ -29,6 +29,9 @@
// RELOADABLE_COEFFS : Enable (1) or disable (0) reloading
// coefficients at runtime
//
+// BLANK_OUTPUT : Disable (1) or enable (0) output when initially
+// filling internal pipeline
+//
// SYMMETRIC_COEFFS : Reduce multiplier usage by approximately half
// if coefficients are symmetric
//
@@ -41,7 +44,7 @@
// streaming will cause temporary output
// corruption!
//
-// Note: If using USE_EMBEDDED_REGS_COEFFS, coefficients must be written at
+// Note: If using USE_EMBEDDED_REGS_COEFFS, coefficients must be written at
// least once since COEFFS_VEC is ignored!
//
@@ -56,11 +59,12 @@ module rfnoc_block_fir_filter #(
parameter COEFF_WIDTH = 16,
parameter NUM_COEFFS = 41,
parameter [NUM_COEFFS*COEFF_WIDTH-1:0] COEFFS_VEC = // Make impulse by default
- {
+ {
{1'b0, {(COEFF_WIDTH-1){1'b1}} }, // Max positive value
{(COEFF_WIDTH*(NUM_COEFFS-1)){1'b0}} // Zero for remaining coefficients
},
parameter RELOADABLE_COEFFS = 1,
+ parameter BLANK_OUTPUT = 1,
parameter SYMMETRIC_COEFFS = 0,
parameter SKIP_ZERO_COEFFS = 0,
parameter USE_EMBEDDED_REGS_COEFFS = 1
@@ -161,7 +165,7 @@ module rfnoc_block_fir_filter #(
) noc_shell_fir_filter_i (
.rfnoc_chdr_clk (rfnoc_chdr_clk),
.rfnoc_ctrl_clk (rfnoc_ctrl_clk),
- .ce_clk (ce_clk),
+ .ce_clk (ce_clk),
.rfnoc_chdr_rst (),
.rfnoc_ctrl_rst (),
.ce_rst (ce_rst),
@@ -280,6 +284,7 @@ module rfnoc_block_fir_filter #(
.NUM_COEFFS (NUM_COEFFS),
.COEFFS_VEC (COEFFS_VEC),
.RELOADABLE_COEFFS (RELOADABLE_COEFFS),
+ .BLANK_OUTPUT (BLANK_OUTPUT),
.SYMMETRIC_COEFFS (SYMMETRIC_COEFFS),
.SKIP_ZERO_COEFFS (SKIP_ZERO_COEFFS),
.USE_EMBEDDED_REGS_COEFFS (USE_EMBEDDED_REGS_COEFFS)
diff --git a/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_fir_filter/rfnoc_fir_filter_core.v b/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_fir_filter/rfnoc_fir_filter_core.v
index 774f43761..60303e6fa 100644
--- a/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_fir_filter/rfnoc_fir_filter_core.v
+++ b/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_fir_filter/rfnoc_fir_filter_core.v
@@ -17,7 +17,7 @@
//
// BASE_ADDR : Control port base address to which this block
// responds.
-//
+//
// COEFF_WIDTH : Coefficient width
//
// NUM_COEFFS : Number of coefficients / filter taps
@@ -29,6 +29,9 @@
// RELOADABLE_COEFFS : Enable (1) or disable (0) reloading
// coefficients at runtime
//
+// BLANK_OUTPUT : Disable (1) or enable (0) output when initially
+// filling internal pipeline
+//
// SYMMETRIC_COEFFS : Reduce multiplier usage by approximately half
// if coefficients are symmetric
//
@@ -41,7 +44,7 @@
// streaming will cause temporary output
// corruption!
//
-// Note: If using USE_EMBEDDED_REGS_COEFFS, coefficients must be written at
+// Note: If using USE_EMBEDDED_REGS_COEFFS, coefficients must be written at
// least once since COEFFS_VEC is ignored!
@@ -53,11 +56,12 @@ module rfnoc_fir_filter_core #(
parameter COEFF_WIDTH = 16,
parameter NUM_COEFFS = 41,
parameter [NUM_COEFFS*COEFF_WIDTH-1:0] COEFFS_VEC = // Make impulse by default
- {
+ {
{1'b0, {(COEFF_WIDTH-1){1'b1}} }, // Max positive value
{(COEFF_WIDTH*(NUM_COEFFS-1)){1'b0}} // Zero for remaining coefficients
},
parameter RELOADABLE_COEFFS = 1,
+ parameter BLANK_OUTPUT = 1,
parameter SYMMETRIC_COEFFS = 0,
parameter SKIP_ZERO_COEFFS = 0,
parameter USE_EMBEDDED_REGS_COEFFS = 1
@@ -171,7 +175,7 @@ module rfnoc_fir_filter_core #(
.NUM_COEFFS (NUM_COEFFS),
.COEFFS_VEC (COEFFS_VEC),
.RELOADABLE_COEFFS (RELOADABLE_COEFFS),
- .BLANK_OUTPUT (1),
+ .BLANK_OUTPUT (BLANK_OUTPUT),
// Optional optimizations
.SYMMETRIC_COEFFS (SYMMETRIC_COEFFS),
.SKIP_ZERO_COEFFS (SKIP_ZERO_COEFFS),
@@ -202,7 +206,7 @@ module rfnoc_fir_filter_core #(
.NUM_COEFFS (NUM_COEFFS),
.COEFFS_VEC (COEFFS_VEC),
.RELOADABLE_COEFFS (RELOADABLE_COEFFS),
- .BLANK_OUTPUT (1),
+ .BLANK_OUTPUT (BLANK_OUTPUT),
// Optional optimizations
.SYMMETRIC_COEFFS (SYMMETRIC_COEFFS),
.SKIP_ZERO_COEFFS (SKIP_ZERO_COEFFS),