fpga: Add Replay Block to RFNoC Core Image

Add the Replay RFNoC block to the RFNoC core image for x300, x310, n300,
n310, n320/n321, and e320. The Replay block is contained within its own
static connection, so previous default behavior is still supported.

Signed-off-by: mattprost <matt.prost@ni.com>

20 files changed, 2586 insertions, 591 deletions

diff --git a/fpga/usrp3/top/e320/Makefile.e320.inc b/fpga/usrp3/top/e320/Makefile.e320.inc
index b8544f3cd..c78c40d4a 100644
--- a/fpga/usrp3/top/e320/Makefile.e320.inc
+++ b/fpga/usrp3/top/e320/Makefile.e320.inc
@@ -34,12 +34,13 @@ include $(LIB_DIR)/dsp/Makefile.srcs
 include $(LIB_DIR)/io_cap_gen/Makefile.srcs
 include $(LIB_DIR)/rfnoc/Makefile.srcs
 # For sake of convenience, we include the Makefile.srcs for DRAM FIFO, DDC, and
-# DUC, and of course the radio. Any other block needs to use the
+# DUC, Replay, and of course the radio. Any other block needs to use the
 # RFNOC_OOT_MAKEFILE_SRCS variable (see below).
 include $(LIB_DIR)/rfnoc/blocks/rfnoc_block_axi_ram_fifo/Makefile.srcs
 include $(LIB_DIR)/rfnoc/blocks/rfnoc_block_radio/Makefile.srcs
 include $(LIB_DIR)/rfnoc/blocks/rfnoc_block_ddc/Makefile.srcs
 include $(LIB_DIR)/rfnoc/blocks/rfnoc_block_duc/Makefile.srcs
+include $(LIB_DIR)/rfnoc/blocks/rfnoc_block_replay/Makefile.srcs
 # If out-of-tree modules want to be compiled into this image, then they need to
 # pass in the RFNOC_OOT_MAKEFILE_SRCS as a list of Makefile.srcs files.
 # Those files need to amend the RFNOC_OOT_SRCS variable with a list of actual
@@ -117,6 +118,7 @@ $(RFNOC_FRAMEWORK_SRCS) \
 $(RFNOC_BLOCK_AXI_RAM_FIFO_SRCS) \
 $(RFNOC_BLOCK_DUC_SRCS) $(RFNOC_BLOCK_DDC_SRCS) \
 $(RFNOC_BLOCK_RADIO_SRCS) \
+$(RFNOC_BLOCK_REPLAY_SRCS) \
 $(abspath $(MB_XDC))
 
 EDGE_TBL_DEF="RFNOC_EDGE_TBL_FILE=$(call RESOLVE_PATH,$(EDGE_FILE))"
diff --git a/fpga/usrp3/top/e320/e320_rfnoc_image_core.v b/fpga/usrp3/top/e320/e320_rfnoc_image_core.v
index 0811c9cc7..7a896f51c 100644
--- a/fpga/usrp3/top/e320/e320_rfnoc_image_core.v
+++ b/fpga/usrp3/top/e320/e320_rfnoc_image_core.v
@@ -1,5 +1,5 @@
 //
-// Copyright 2019 Ettus Research, A National Instruments Brand
+// Copyright 2020 Ettus Research, A National Instruments Brand
 //
 // SPDX-License-Identifier: LGPL-3.0-or-later
 //
@@ -7,9 +7,9 @@
 // Module: rfnoc_image_core (for e320)
 // This file was autogenerated by UHD's image builder tool (rfnoc_image_builder)
 // Re-running that tool will overwrite this file!
-// File generated on: 2019-11-08T15:58:14.818480
-// Source: ./e320/e320_rfnoc_image_core.yml
-// Source SHA256: a2a7b213b5764ef6cb83fed9d744a415bf8a7f18a955fbe1f867590f5d8c5142
+// File generated on: 2020-09-02T12:03:19.552358
+// Source: ./e320_rfnoc_image_core.yml
+// Source SHA256: c9b4c8ff60f4b6829b45cbb0beae5dbbb6ef64db4e20a54be556a99dd88a48cf
 
 module rfnoc_image_core #(
   parameter [15:0] PROTOVER = {8'd1, 8'd0}
@@ -45,50 +45,50 @@ module rfnoc_image_core #(
   output wire [  2-1:0] radio_tx_running,
 //  dram
   input  wire [  1-1:0] axi_rst,
-  output wire [  2-1:0] m_axi_awid,
-  output wire [ 64-1:0] m_axi_awaddr,
-  output wire [ 16-1:0] m_axi_awlen,
-  output wire [  6-1:0] m_axi_awsize,
-  output wire [  4-1:0] m_axi_awburst,
-  output wire [  2-1:0] m_axi_awlock,
-  output wire [  8-1:0] m_axi_awcache,
-  output wire [  6-1:0] m_axi_awprot,
-  output wire [  8-1:0] m_axi_awqos,
-  output wire [  8-1:0] m_axi_awregion,
-  output wire [  2-1:0] m_axi_awuser,
-  output wire [  2-1:0] m_axi_awvalid,
-  input  wire [  2-1:0] m_axi_awready,
-  output wire [128-1:0] m_axi_wdata,
-  output wire [ 16-1:0] m_axi_wstrb,
-  output wire [  2-1:0] m_axi_wlast,
-  output wire [  2-1:0] m_axi_wuser,
-  output wire [  2-1:0] m_axi_wvalid,
-  input  wire [  2-1:0] m_axi_wready,
-  input  wire [  2-1:0] m_axi_bid,
-  input  wire [  4-1:0] m_axi_bresp,
-  input  wire [  2-1:0] m_axi_buser,
-  input  wire [  2-1:0] m_axi_bvalid,
-  output wire [  2-1:0] m_axi_bready,
-  output wire [  2-1:0] m_axi_arid,
-  output wire [ 64-1:0] m_axi_araddr,
-  output wire [ 16-1:0] m_axi_arlen,
-  output wire [  6-1:0] m_axi_arsize,
-  output wire [  4-1:0] m_axi_arburst,
-  output wire [  2-1:0] m_axi_arlock,
-  output wire [  8-1:0] m_axi_arcache,
-  output wire [  6-1:0] m_axi_arprot,
-  output wire [  8-1:0] m_axi_arqos,
-  output wire [  8-1:0] m_axi_arregion,
-  output wire [  2-1:0] m_axi_aruser,
-  output wire [  2-1:0] m_axi_arvalid,
-  input  wire [  2-1:0] m_axi_arready,
-  input  wire [  2-1:0] m_axi_rid,
-  input  wire [128-1:0] m_axi_rdata,
-  input  wire [  4-1:0] m_axi_rresp,
-  input  wire [  2-1:0] m_axi_rlast,
-  input  wire [  2-1:0] m_axi_ruser,
-  input  wire [  2-1:0] m_axi_rvalid,
-  output wire [  2-1:0] m_axi_rready,
+  output wire [  4-1:0] m_axi_awid,
+  output wire [128-1:0] m_axi_awaddr,
+  output wire [ 32-1:0] m_axi_awlen,
+  output wire [ 12-1:0] m_axi_awsize,
+  output wire [  8-1:0] m_axi_awburst,
+  output wire [  4-1:0] m_axi_awlock,
+  output wire [ 16-1:0] m_axi_awcache,
+  output wire [ 12-1:0] m_axi_awprot,
+  output wire [ 16-1:0] m_axi_awqos,
+  output wire [ 16-1:0] m_axi_awregion,
+  output wire [  4-1:0] m_axi_awuser,
+  output wire [  4-1:0] m_axi_awvalid,
+  input  wire [  4-1:0] m_axi_awready,
+  output wire [256-1:0] m_axi_wdata,
+  output wire [ 32-1:0] m_axi_wstrb,
+  output wire [  4-1:0] m_axi_wlast,
+  output wire [  4-1:0] m_axi_wuser,
+  output wire [  4-1:0] m_axi_wvalid,
+  input  wire [  4-1:0] m_axi_wready,
+  input  wire [  4-1:0] m_axi_bid,
+  input  wire [  8-1:0] m_axi_bresp,
+  input  wire [  4-1:0] m_axi_buser,
+  input  wire [  4-1:0] m_axi_bvalid,
+  output wire [  4-1:0] m_axi_bready,
+  output wire [  4-1:0] m_axi_arid,
+  output wire [128-1:0] m_axi_araddr,
+  output wire [ 32-1:0] m_axi_arlen,
+  output wire [ 12-1:0] m_axi_arsize,
+  output wire [  8-1:0] m_axi_arburst,
+  output wire [  4-1:0] m_axi_arlock,
+  output wire [ 16-1:0] m_axi_arcache,
+  output wire [ 12-1:0] m_axi_arprot,
+  output wire [ 16-1:0] m_axi_arqos,
+  output wire [ 16-1:0] m_axi_arregion,
+  output wire [  4-1:0] m_axi_aruser,
+  output wire [  4-1:0] m_axi_arvalid,
+  input  wire [  4-1:0] m_axi_arready,
+  input  wire [  4-1:0] m_axi_rid,
+  input  wire [256-1:0] m_axi_rdata,
+  input  wire [  8-1:0] m_axi_rresp,
+  input  wire [  4-1:0] m_axi_rlast,
+  input  wire [  4-1:0] m_axi_ruser,
+  input  wire [  4-1:0] m_axi_rvalid,
+  output wire [  4-1:0] m_axi_rready,
   // Transport 0 (eth 10G)
   input  wire [64-1:0]  s_eth_tdata,
   input  wire         s_eth_tlast,
@@ -329,7 +329,7 @@ module rfnoc_image_core #(
     .NUM_DATA_O         (1),
     .INST_NUM           (2),
     .CTRL_XBAR_PORT     (3),
-    .INGRESS_BUFF_SIZE  (13),
+    .INGRESS_BUFF_SIZE  (12),
     .MTU                (MTU),
     .REPORT_STRM_ERRS   (1)
   ) ep2_i (
@@ -390,7 +390,7 @@ module rfnoc_image_core #(
     .NUM_DATA_O         (1),
     .INST_NUM           (3),
     .CTRL_XBAR_PORT     (4),
-    .INGRESS_BUFF_SIZE  (13),
+    .INGRESS_BUFF_SIZE  (12),
     .MTU                (MTU),
     .REPORT_STRM_ERRS   (1)
   ) ep3_i (
@@ -451,10 +451,10 @@ module rfnoc_image_core #(
   wire              m_radio0_ctrl_tlast ,   s_radio0_ctrl_tlast ;
   wire              m_radio0_ctrl_tvalid,   s_radio0_ctrl_tvalid;
   wire              m_radio0_ctrl_tready,   s_radio0_ctrl_tready;
-  wire [31:0]       m_fifo0_ctrl_tdata ,   s_fifo0_ctrl_tdata ;
-  wire              m_fifo0_ctrl_tlast ,   s_fifo0_ctrl_tlast ;
-  wire              m_fifo0_ctrl_tvalid,   s_fifo0_ctrl_tvalid;
-  wire              m_fifo0_ctrl_tready,   s_fifo0_ctrl_tready;
+  wire [31:0]       m_replay0_ctrl_tdata ,   s_replay0_ctrl_tdata ;
+  wire              m_replay0_ctrl_tlast ,   s_replay0_ctrl_tlast ;
+  wire              m_replay0_ctrl_tvalid,   s_replay0_ctrl_tvalid;
+  wire              m_replay0_ctrl_tready,   s_replay0_ctrl_tready;
 
   axis_ctrl_crossbar_nxn #(
     .WIDTH            (32),
@@ -467,14 +467,14 @@ module rfnoc_image_core #(
   ) ctrl_xb_i (
     .clk              (rfnoc_ctrl_clk),
     .reset            (rfnoc_ctrl_rst),
-    .s_axis_tdata     ({m_fifo0_ctrl_tdata , m_radio0_ctrl_tdata , m_ddc0_ctrl_tdata , m_duc0_ctrl_tdata , m_ep0_ctrl_tdata , m_core_ctrl_tdata }),
-    .s_axis_tvalid    ({m_fifo0_ctrl_tvalid, m_radio0_ctrl_tvalid, m_ddc0_ctrl_tvalid, m_duc0_ctrl_tvalid, m_ep0_ctrl_tvalid, m_core_ctrl_tvalid}),
-    .s_axis_tlast     ({m_fifo0_ctrl_tlast , m_radio0_ctrl_tlast , m_ddc0_ctrl_tlast , m_duc0_ctrl_tlast , m_ep0_ctrl_tlast , m_core_ctrl_tlast }),
-    .s_axis_tready    ({m_fifo0_ctrl_tready, m_radio0_ctrl_tready, m_ddc0_ctrl_tready, m_duc0_ctrl_tready, m_ep0_ctrl_tready, m_core_ctrl_tready}),
-    .m_axis_tdata     ({s_fifo0_ctrl_tdata , s_radio0_ctrl_tdata , s_ddc0_ctrl_tdata , s_duc0_ctrl_tdata , s_ep0_ctrl_tdata , s_core_ctrl_tdata }),
-    .m_axis_tvalid    ({s_fifo0_ctrl_tvalid, s_radio0_ctrl_tvalid, s_ddc0_ctrl_tvalid, s_duc0_ctrl_tvalid, s_ep0_ctrl_tvalid, s_core_ctrl_tvalid}),
-    .m_axis_tlast     ({s_fifo0_ctrl_tlast , s_radio0_ctrl_tlast , s_ddc0_ctrl_tlast , s_duc0_ctrl_tlast , s_ep0_ctrl_tlast , s_core_ctrl_tlast }),
-    .m_axis_tready    ({s_fifo0_ctrl_tready, s_radio0_ctrl_tready, s_ddc0_ctrl_tready, s_duc0_ctrl_tready, s_ep0_ctrl_tready, s_core_ctrl_tready}),
+    .s_axis_tdata     ({m_replay0_ctrl_tdata , m_radio0_ctrl_tdata , m_ddc0_ctrl_tdata , m_duc0_ctrl_tdata , m_ep0_ctrl_tdata , m_core_ctrl_tdata }),
+    .s_axis_tvalid    ({m_replay0_ctrl_tvalid, m_radio0_ctrl_tvalid, m_ddc0_ctrl_tvalid, m_duc0_ctrl_tvalid, m_ep0_ctrl_tvalid, m_core_ctrl_tvalid}),
+    .s_axis_tlast     ({m_replay0_ctrl_tlast , m_radio0_ctrl_tlast , m_ddc0_ctrl_tlast , m_duc0_ctrl_tlast , m_ep0_ctrl_tlast , m_core_ctrl_tlast }),
+    .s_axis_tready    ({m_replay0_ctrl_tready, m_radio0_ctrl_tready, m_ddc0_ctrl_tready, m_duc0_ctrl_tready, m_ep0_ctrl_tready, m_core_ctrl_tready}),
+    .m_axis_tdata     ({s_replay0_ctrl_tdata , s_radio0_ctrl_tdata , s_ddc0_ctrl_tdata , s_duc0_ctrl_tdata , s_ep0_ctrl_tdata , s_core_ctrl_tdata }),
+    .m_axis_tvalid    ({s_replay0_ctrl_tvalid, s_radio0_ctrl_tvalid, s_ddc0_ctrl_tvalid, s_duc0_ctrl_tvalid, s_ep0_ctrl_tvalid, s_core_ctrl_tvalid}),
+    .m_axis_tlast     ({s_replay0_ctrl_tlast , s_radio0_ctrl_tlast , s_ddc0_ctrl_tlast , s_duc0_ctrl_tlast , s_ep0_ctrl_tlast , s_core_ctrl_tlast }),
+    .m_axis_tready    ({s_replay0_ctrl_tready, s_radio0_ctrl_tready, s_ddc0_ctrl_tready, s_duc0_ctrl_tready, s_ep0_ctrl_tready, s_core_ctrl_tready}),
     .deadlock_detected()
   );
 
@@ -702,144 +702,141 @@ module rfnoc_image_core #(
 
 
   // ----------------------------------------------------
-  // fifo0
+  // replay0
   // ----------------------------------------------------
-  wire              fifo0_mem_clk;
-  wire [CHDR_W-1:0] s_fifo0_in_1_tdata , s_fifo0_in_0_tdata ;
-  wire              s_fifo0_in_1_tlast , s_fifo0_in_0_tlast ;
-  wire              s_fifo0_in_1_tvalid, s_fifo0_in_0_tvalid;
-  wire              s_fifo0_in_1_tready, s_fifo0_in_0_tready;
-  wire [CHDR_W-1:0] m_fifo0_out_1_tdata , m_fifo0_out_0_tdata ;
-  wire              m_fifo0_out_1_tlast , m_fifo0_out_0_tlast ;
-  wire              m_fifo0_out_1_tvalid, m_fifo0_out_0_tvalid;
-  wire              m_fifo0_out_1_tready, m_fifo0_out_0_tready;
+  wire              replay0_mem_clk;
+  wire [CHDR_W-1:0] s_replay0_in_1_tdata , s_replay0_in_0_tdata ;
+  wire              s_replay0_in_1_tlast , s_replay0_in_0_tlast ;
+  wire              s_replay0_in_1_tvalid, s_replay0_in_0_tvalid;
+  wire              s_replay0_in_1_tready, s_replay0_in_0_tready;
+  wire [CHDR_W-1:0] m_replay0_out_1_tdata , m_replay0_out_0_tdata ;
+  wire              m_replay0_out_1_tlast , m_replay0_out_0_tlast ;
+  wire              m_replay0_out_1_tvalid, m_replay0_out_0_tvalid;
+  wire              m_replay0_out_1_tready, m_replay0_out_0_tready;
 
   //  axi_ram
-  wire [  1-1:0] fifo0_axi_rst;
-  wire [  2-1:0] fifo0_m_axi_awid;
-  wire [ 64-1:0] fifo0_m_axi_awaddr;
-  wire [ 16-1:0] fifo0_m_axi_awlen;
-  wire [  6-1:0] fifo0_m_axi_awsize;
-  wire [  4-1:0] fifo0_m_axi_awburst;
-  wire [  2-1:0] fifo0_m_axi_awlock;
-  wire [  8-1:0] fifo0_m_axi_awcache;
-  wire [  6-1:0] fifo0_m_axi_awprot;
-  wire [  8-1:0] fifo0_m_axi_awqos;
-  wire [  8-1:0] fifo0_m_axi_awregion;
-  wire [  2-1:0] fifo0_m_axi_awuser;
-  wire [  2-1:0] fifo0_m_axi_awvalid;
-  wire [  2-1:0] fifo0_m_axi_awready;
-  wire [128-1:0] fifo0_m_axi_wdata;
-  wire [ 16-1:0] fifo0_m_axi_wstrb;
-  wire [  2-1:0] fifo0_m_axi_wlast;
-  wire [  2-1:0] fifo0_m_axi_wuser;
-  wire [  2-1:0] fifo0_m_axi_wvalid;
-  wire [  2-1:0] fifo0_m_axi_wready;
-  wire [  2-1:0] fifo0_m_axi_bid;
-  wire [  4-1:0] fifo0_m_axi_bresp;
-  wire [  2-1:0] fifo0_m_axi_buser;
-  wire [  2-1:0] fifo0_m_axi_bvalid;
-  wire [  2-1:0] fifo0_m_axi_bready;
-  wire [  2-1:0] fifo0_m_axi_arid;
-  wire [ 64-1:0] fifo0_m_axi_araddr;
-  wire [ 16-1:0] fifo0_m_axi_arlen;
-  wire [  6-1:0] fifo0_m_axi_arsize;
-  wire [  4-1:0] fifo0_m_axi_arburst;
-  wire [  2-1:0] fifo0_m_axi_arlock;
-  wire [  8-1:0] fifo0_m_axi_arcache;
-  wire [  6-1:0] fifo0_m_axi_arprot;
-  wire [  8-1:0] fifo0_m_axi_arqos;
-  wire [  8-1:0] fifo0_m_axi_arregion;
-  wire [  2-1:0] fifo0_m_axi_aruser;
-  wire [  2-1:0] fifo0_m_axi_arvalid;
-  wire [  2-1:0] fifo0_m_axi_arready;
-  wire [  2-1:0] fifo0_m_axi_rid;
-  wire [128-1:0] fifo0_m_axi_rdata;
-  wire [  4-1:0] fifo0_m_axi_rresp;
-  wire [  2-1:0] fifo0_m_axi_rlast;
-  wire [  2-1:0] fifo0_m_axi_ruser;
-  wire [  2-1:0] fifo0_m_axi_rvalid;
-  wire [  2-1:0] fifo0_m_axi_rready;
-
-  rfnoc_block_axi_ram_fifo #(
+  wire [  1-1:0] replay0_axi_rst;
+  wire [  4-1:0] replay0_m_axi_awid;
+  wire [128-1:0] replay0_m_axi_awaddr;
+  wire [ 32-1:0] replay0_m_axi_awlen;
+  wire [ 12-1:0] replay0_m_axi_awsize;
+  wire [  8-1:0] replay0_m_axi_awburst;
+  wire [  4-1:0] replay0_m_axi_awlock;
+  wire [ 16-1:0] replay0_m_axi_awcache;
+  wire [ 12-1:0] replay0_m_axi_awprot;
+  wire [ 16-1:0] replay0_m_axi_awqos;
+  wire [ 16-1:0] replay0_m_axi_awregion;
+  wire [  4-1:0] replay0_m_axi_awuser;
+  wire [  4-1:0] replay0_m_axi_awvalid;
+  wire [  4-1:0] replay0_m_axi_awready;
+  wire [256-1:0] replay0_m_axi_wdata;
+  wire [ 32-1:0] replay0_m_axi_wstrb;
+  wire [  4-1:0] replay0_m_axi_wlast;
+  wire [  4-1:0] replay0_m_axi_wuser;
+  wire [  4-1:0] replay0_m_axi_wvalid;
+  wire [  4-1:0] replay0_m_axi_wready;
+  wire [  4-1:0] replay0_m_axi_bid;
+  wire [  8-1:0] replay0_m_axi_bresp;
+  wire [  4-1:0] replay0_m_axi_buser;
+  wire [  4-1:0] replay0_m_axi_bvalid;
+  wire [  4-1:0] replay0_m_axi_bready;
+  wire [  4-1:0] replay0_m_axi_arid;
+  wire [128-1:0] replay0_m_axi_araddr;
+  wire [ 32-1:0] replay0_m_axi_arlen;
+  wire [ 12-1:0] replay0_m_axi_arsize;
+  wire [  8-1:0] replay0_m_axi_arburst;
+  wire [  4-1:0] replay0_m_axi_arlock;
+  wire [ 16-1:0] replay0_m_axi_arcache;
+  wire [ 12-1:0] replay0_m_axi_arprot;
+  wire [ 16-1:0] replay0_m_axi_arqos;
+  wire [ 16-1:0] replay0_m_axi_arregion;
+  wire [  4-1:0] replay0_m_axi_aruser;
+  wire [  4-1:0] replay0_m_axi_arvalid;
+  wire [  4-1:0] replay0_m_axi_arready;
+  wire [  4-1:0] replay0_m_axi_rid;
+  wire [256-1:0] replay0_m_axi_rdata;
+  wire [  8-1:0] replay0_m_axi_rresp;
+  wire [  4-1:0] replay0_m_axi_rlast;
+  wire [  4-1:0] replay0_m_axi_ruser;
+  wire [  4-1:0] replay0_m_axi_rvalid;
+  wire [  4-1:0] replay0_m_axi_rready;
+
+  rfnoc_block_replay #(
     .THIS_PORTID(5),
     .CHDR_W(CHDR_W),
+    .NUM_PORTS(2),
     .MEM_ADDR_W(31),
     .MEM_DATA_W(64),
-    .MEM_CLK_RATE(300e6),
-    .FIFO_ADDR_BASE({31'h02000000, 31'h00000000}),
-    .FIFO_ADDR_MASK({31'h01FFFFFF, 31'h01FFFFFF}),
-    .NUM_PORTS(2),
     .MTU(MTU)
-  ) b_fifo0_3 (
+  ) b_replay0_3 (
     .rfnoc_chdr_clk     (rfnoc_chdr_clk),
     .rfnoc_ctrl_clk     (rfnoc_ctrl_clk),
-    .mem_clk(fifo0_mem_clk),
+    .mem_clk(replay0_mem_clk),
     .rfnoc_core_config  (rfnoc_core_config[512*4-1:512*3]),
     .rfnoc_core_status  (rfnoc_core_status[512*4-1:512*3]),
 
-    .axi_rst(fifo0_axi_rst),
-    .m_axi_awid(fifo0_m_axi_awid),
-    .m_axi_awaddr(fifo0_m_axi_awaddr),
-    .m_axi_awlen(fifo0_m_axi_awlen),
-    .m_axi_awsize(fifo0_m_axi_awsize),
-    .m_axi_awburst(fifo0_m_axi_awburst),
-    .m_axi_awlock(fifo0_m_axi_awlock),
-    .m_axi_awcache(fifo0_m_axi_awcache),
-    .m_axi_awprot(fifo0_m_axi_awprot),
-    .m_axi_awqos(fifo0_m_axi_awqos),
-    .m_axi_awregion(fifo0_m_axi_awregion),
-    .m_axi_awuser(fifo0_m_axi_awuser),
-    .m_axi_awvalid(fifo0_m_axi_awvalid),
-    .m_axi_awready(fifo0_m_axi_awready),
-    .m_axi_wdata(fifo0_m_axi_wdata),
-    .m_axi_wstrb(fifo0_m_axi_wstrb),
-    .m_axi_wlast(fifo0_m_axi_wlast),
-    .m_axi_wuser(fifo0_m_axi_wuser),
-    .m_axi_wvalid(fifo0_m_axi_wvalid),
-    .m_axi_wready(fifo0_m_axi_wready),
-    .m_axi_bid(fifo0_m_axi_bid),
-    .m_axi_bresp(fifo0_m_axi_bresp),
-    .m_axi_buser(fifo0_m_axi_buser),
-    .m_axi_bvalid(fifo0_m_axi_bvalid),
-    .m_axi_bready(fifo0_m_axi_bready),
-    .m_axi_arid(fifo0_m_axi_arid),
-    .m_axi_araddr(fifo0_m_axi_araddr),
-    .m_axi_arlen(fifo0_m_axi_arlen),
-    .m_axi_arsize(fifo0_m_axi_arsize),
-    .m_axi_arburst(fifo0_m_axi_arburst),
-    .m_axi_arlock(fifo0_m_axi_arlock),
-    .m_axi_arcache(fifo0_m_axi_arcache),
-    .m_axi_arprot(fifo0_m_axi_arprot),
-    .m_axi_arqos(fifo0_m_axi_arqos),
-    .m_axi_arregion(fifo0_m_axi_arregion),
-    .m_axi_aruser(fifo0_m_axi_aruser),
-    .m_axi_arvalid(fifo0_m_axi_arvalid),
-    .m_axi_arready(fifo0_m_axi_arready),
-    .m_axi_rid(fifo0_m_axi_rid),
-    .m_axi_rdata(fifo0_m_axi_rdata),
-    .m_axi_rresp(fifo0_m_axi_rresp),
-    .m_axi_rlast(fifo0_m_axi_rlast),
-    .m_axi_ruser(fifo0_m_axi_ruser),
-    .m_axi_rvalid(fifo0_m_axi_rvalid),
-    .m_axi_rready(fifo0_m_axi_rready),
-
-    .s_rfnoc_chdr_tdata ({s_fifo0_in_1_tdata , s_fifo0_in_0_tdata }),
-    .s_rfnoc_chdr_tlast ({s_fifo0_in_1_tlast , s_fifo0_in_0_tlast }),
-    .s_rfnoc_chdr_tvalid({s_fifo0_in_1_tvalid, s_fifo0_in_0_tvalid}),
-    .s_rfnoc_chdr_tready({s_fifo0_in_1_tready, s_fifo0_in_0_tready}),
-    .m_rfnoc_chdr_tdata ({m_fifo0_out_1_tdata , m_fifo0_out_0_tdata }),
-    .m_rfnoc_chdr_tlast ({m_fifo0_out_1_tlast , m_fifo0_out_0_tlast }),
-    .m_rfnoc_chdr_tvalid({m_fifo0_out_1_tvalid, m_fifo0_out_0_tvalid}),
-    .m_rfnoc_chdr_tready({m_fifo0_out_1_tready, m_fifo0_out_0_tready}),
-    .s_rfnoc_ctrl_tdata (s_fifo0_ctrl_tdata ),
-    .s_rfnoc_ctrl_tlast (s_fifo0_ctrl_tlast ),
-    .s_rfnoc_ctrl_tvalid(s_fifo0_ctrl_tvalid),
-    .s_rfnoc_ctrl_tready(s_fifo0_ctrl_tready),
-    .m_rfnoc_ctrl_tdata (m_fifo0_ctrl_tdata ),
-    .m_rfnoc_ctrl_tlast (m_fifo0_ctrl_tlast ),
-    .m_rfnoc_ctrl_tvalid(m_fifo0_ctrl_tvalid),
-    .m_rfnoc_ctrl_tready(m_fifo0_ctrl_tready)
+    .axi_rst(replay0_axi_rst),
+    .m_axi_awid(replay0_m_axi_awid),
+    .m_axi_awaddr(replay0_m_axi_awaddr),
+    .m_axi_awlen(replay0_m_axi_awlen),
+    .m_axi_awsize(replay0_m_axi_awsize),
+    .m_axi_awburst(replay0_m_axi_awburst),
+    .m_axi_awlock(replay0_m_axi_awlock),
+    .m_axi_awcache(replay0_m_axi_awcache),
+    .m_axi_awprot(replay0_m_axi_awprot),
+    .m_axi_awqos(replay0_m_axi_awqos),
+    .m_axi_awregion(replay0_m_axi_awregion),
+    .m_axi_awuser(replay0_m_axi_awuser),
+    .m_axi_awvalid(replay0_m_axi_awvalid),
+    .m_axi_awready(replay0_m_axi_awready),
+    .m_axi_wdata(replay0_m_axi_wdata),
+    .m_axi_wstrb(replay0_m_axi_wstrb),
+    .m_axi_wlast(replay0_m_axi_wlast),
+    .m_axi_wuser(replay0_m_axi_wuser),
+    .m_axi_wvalid(replay0_m_axi_wvalid),
+    .m_axi_wready(replay0_m_axi_wready),
+    .m_axi_bid(replay0_m_axi_bid),
+    .m_axi_bresp(replay0_m_axi_bresp),
+    .m_axi_buser(replay0_m_axi_buser),
+    .m_axi_bvalid(replay0_m_axi_bvalid),
+    .m_axi_bready(replay0_m_axi_bready),
+    .m_axi_arid(replay0_m_axi_arid),
+    .m_axi_araddr(replay0_m_axi_araddr),
+    .m_axi_arlen(replay0_m_axi_arlen),
+    .m_axi_arsize(replay0_m_axi_arsize),
+    .m_axi_arburst(replay0_m_axi_arburst),
+    .m_axi_arlock(replay0_m_axi_arlock),
+    .m_axi_arcache(replay0_m_axi_arcache),
+    .m_axi_arprot(replay0_m_axi_arprot),
+    .m_axi_arqos(replay0_m_axi_arqos),
+    .m_axi_arregion(replay0_m_axi_arregion),
+    .m_axi_aruser(replay0_m_axi_aruser),
+    .m_axi_arvalid(replay0_m_axi_arvalid),
+    .m_axi_arready(replay0_m_axi_arready),
+    .m_axi_rid(replay0_m_axi_rid),
+    .m_axi_rdata(replay0_m_axi_rdata),
+    .m_axi_rresp(replay0_m_axi_rresp),
+    .m_axi_rlast(replay0_m_axi_rlast),
+    .m_axi_ruser(replay0_m_axi_ruser),
+    .m_axi_rvalid(replay0_m_axi_rvalid),
+    .m_axi_rready(replay0_m_axi_rready),
+
+    .s_rfnoc_chdr_tdata ({s_replay0_in_1_tdata , s_replay0_in_0_tdata }),
+    .s_rfnoc_chdr_tlast ({s_replay0_in_1_tlast , s_replay0_in_0_tlast }),
+    .s_rfnoc_chdr_tvalid({s_replay0_in_1_tvalid, s_replay0_in_0_tvalid}),
+    .s_rfnoc_chdr_tready({s_replay0_in_1_tready, s_replay0_in_0_tready}),
+    .m_rfnoc_chdr_tdata ({m_replay0_out_1_tdata , m_replay0_out_0_tdata }),
+    .m_rfnoc_chdr_tlast ({m_replay0_out_1_tlast , m_replay0_out_0_tlast }),
+    .m_rfnoc_chdr_tvalid({m_replay0_out_1_tvalid, m_replay0_out_0_tvalid}),
+    .m_rfnoc_chdr_tready({m_replay0_out_1_tready, m_replay0_out_0_tready}),
+    .s_rfnoc_ctrl_tdata (s_replay0_ctrl_tdata ),
+    .s_rfnoc_ctrl_tlast (s_replay0_ctrl_tlast ),
+    .s_rfnoc_ctrl_tvalid(s_replay0_ctrl_tvalid),
+    .s_rfnoc_ctrl_tready(s_replay0_ctrl_tready),
+    .m_rfnoc_ctrl_tdata (m_replay0_ctrl_tdata ),
+    .m_rfnoc_ctrl_tlast (m_replay0_ctrl_tlast ),
+    .m_rfnoc_ctrl_tvalid(m_replay0_ctrl_tvalid),
+    .m_rfnoc_ctrl_tready(m_replay0_ctrl_tready)
   );
 
 
@@ -886,25 +883,25 @@ module rfnoc_image_core #(
   assign s_ep1_in0_tvalid = m_ddc0_out_1_tvalid;
   assign m_ddc0_out_1_tready = s_ep1_in0_tready;
 
-  assign s_fifo0_in_0_tdata = m_ep2_out0_tdata ;
-  assign s_fifo0_in_0_tlast = m_ep2_out0_tlast ;
-  assign s_fifo0_in_0_tvalid = m_ep2_out0_tvalid;
-  assign m_ep2_out0_tready = s_fifo0_in_0_tready;
+  assign s_replay0_in_0_tdata = m_ep2_out0_tdata ;
+  assign s_replay0_in_0_tlast = m_ep2_out0_tlast ;
+  assign s_replay0_in_0_tvalid = m_ep2_out0_tvalid;
+  assign m_ep2_out0_tready = s_replay0_in_0_tready;
 
-  assign s_ep2_in0_tdata = m_fifo0_out_0_tdata ;
-  assign s_ep2_in0_tlast = m_fifo0_out_0_tlast ;
-  assign s_ep2_in0_tvalid = m_fifo0_out_0_tvalid;
-  assign m_fifo0_out_0_tready = s_ep2_in0_tready;
+  assign s_ep2_in0_tdata = m_replay0_out_0_tdata ;
+  assign s_ep2_in0_tlast = m_replay0_out_0_tlast ;
+  assign s_ep2_in0_tvalid = m_replay0_out_0_tvalid;
+  assign m_replay0_out_0_tready = s_ep2_in0_tready;
 
-  assign s_fifo0_in_1_tdata = m_ep3_out0_tdata ;
-  assign s_fifo0_in_1_tlast = m_ep3_out0_tlast ;
-  assign s_fifo0_in_1_tvalid = m_ep3_out0_tvalid;
-  assign m_ep3_out0_tready = s_fifo0_in_1_tready;
+  assign s_replay0_in_1_tdata = m_ep3_out0_tdata ;
+  assign s_replay0_in_1_tlast = m_ep3_out0_tlast ;
+  assign s_replay0_in_1_tvalid = m_ep3_out0_tvalid;
+  assign m_ep3_out0_tready = s_replay0_in_1_tready;
 
-  assign s_ep3_in0_tdata = m_fifo0_out_1_tdata ;
-  assign s_ep3_in0_tlast = m_fifo0_out_1_tlast ;
-  assign s_ep3_in0_tvalid = m_fifo0_out_1_tvalid;
-  assign m_fifo0_out_1_tready = s_ep3_in0_tready;
+  assign s_ep3_in0_tdata = m_replay0_out_1_tdata ;
+  assign s_ep3_in0_tlast = m_replay0_out_1_tlast ;
+  assign s_ep3_in0_tvalid = m_replay0_out_1_tvalid;
+  assign m_replay0_out_1_tready = s_ep3_in0_tready;
 
 
   // ----------------------------------------------------
@@ -917,7 +914,7 @@ module rfnoc_image_core #(
   assign radio0_radio_clk = radio_clk;
   assign duc0_ce_clk = rfnoc_chdr_clk;
   assign ddc0_ce_clk = rfnoc_chdr_clk;
-  assign fifo0_mem_clk = dram_clk;
+  assign replay0_mem_clk = dram_clk;
 
 
   // ----------------------------------------------------
@@ -935,6 +932,52 @@ module rfnoc_image_core #(
   assign radio0_m_ctrlport_resp_status = m_ctrlport_resp_status;
   assign radio0_m_ctrlport_resp_data = m_ctrlport_resp_data;
 
+  assign replay0_axi_rst = axi_rst;
+  assign m_axi_awid = replay0_m_axi_awid;
+  assign m_axi_awaddr = replay0_m_axi_awaddr;
+  assign m_axi_awlen = replay0_m_axi_awlen;
+  assign m_axi_awsize = replay0_m_axi_awsize;
+  assign m_axi_awburst = replay0_m_axi_awburst;
+  assign m_axi_awlock = replay0_m_axi_awlock;
+  assign m_axi_awcache = replay0_m_axi_awcache;
+  assign m_axi_awprot = replay0_m_axi_awprot;
+  assign m_axi_awqos = replay0_m_axi_awqos;
+  assign m_axi_awregion = replay0_m_axi_awregion;
+  assign m_axi_awuser = replay0_m_axi_awuser;
+  assign m_axi_awvalid = replay0_m_axi_awvalid;
+  assign replay0_m_axi_awready = m_axi_awready;
+  assign m_axi_wdata = replay0_m_axi_wdata;
+  assign m_axi_wstrb = replay0_m_axi_wstrb;
+  assign m_axi_wlast = replay0_m_axi_wlast;
+  assign m_axi_wuser = replay0_m_axi_wuser;
+  assign m_axi_wvalid = replay0_m_axi_wvalid;
+  assign replay0_m_axi_wready = m_axi_wready;
+  assign replay0_m_axi_bid = m_axi_bid;
+  assign replay0_m_axi_bresp = m_axi_bresp;
+  assign replay0_m_axi_buser = m_axi_buser;
+  assign replay0_m_axi_bvalid = m_axi_bvalid;
+  assign m_axi_bready = replay0_m_axi_bready;
+  assign m_axi_arid = replay0_m_axi_arid;
+  assign m_axi_araddr = replay0_m_axi_araddr;
+  assign m_axi_arlen = replay0_m_axi_arlen;
+  assign m_axi_arsize = replay0_m_axi_arsize;
+  assign m_axi_arburst = replay0_m_axi_arburst;
+  assign m_axi_arlock = replay0_m_axi_arlock;
+  assign m_axi_arcache = replay0_m_axi_arcache;
+  assign m_axi_arprot = replay0_m_axi_arprot;
+  assign m_axi_arqos = replay0_m_axi_arqos;
+  assign m_axi_arregion = replay0_m_axi_arregion;
+  assign m_axi_aruser = replay0_m_axi_aruser;
+  assign m_axi_arvalid = replay0_m_axi_arvalid;
+  assign replay0_m_axi_arready = m_axi_arready;
+  assign replay0_m_axi_rid = m_axi_rid;
+  assign replay0_m_axi_rdata = m_axi_rdata;
+  assign replay0_m_axi_rresp = m_axi_rresp;
+  assign replay0_m_axi_rlast = m_axi_rlast;
+  assign replay0_m_axi_ruser = m_axi_ruser;
+  assign replay0_m_axi_rvalid = m_axi_rvalid;
+  assign m_axi_rready = replay0_m_axi_rready;
+
   assign radio0_radio_rx_data = radio_rx_data;
   assign radio0_radio_rx_stb = radio_rx_stb;
   assign radio_rx_running = radio0_radio_rx_running;
@@ -942,52 +985,6 @@ module rfnoc_image_core #(
   assign radio0_radio_tx_stb = radio_tx_stb;
   assign radio_tx_running = radio0_radio_tx_running;
 
-  assign fifo0_axi_rst = axi_rst;
-  assign m_axi_awid = fifo0_m_axi_awid;
-  assign m_axi_awaddr = fifo0_m_axi_awaddr;
-  assign m_axi_awlen = fifo0_m_axi_awlen;
-  assign m_axi_awsize = fifo0_m_axi_awsize;
-  assign m_axi_awburst = fifo0_m_axi_awburst;
-  assign m_axi_awlock = fifo0_m_axi_awlock;
-  assign m_axi_awcache = fifo0_m_axi_awcache;
-  assign m_axi_awprot = fifo0_m_axi_awprot;
-  assign m_axi_awqos = fifo0_m_axi_awqos;
-  assign m_axi_awregion = fifo0_m_axi_awregion;
-  assign m_axi_awuser = fifo0_m_axi_awuser;
-  assign m_axi_awvalid = fifo0_m_axi_awvalid;
-  assign fifo0_m_axi_awready = m_axi_awready;
-  assign m_axi_wdata = fifo0_m_axi_wdata;
-  assign m_axi_wstrb = fifo0_m_axi_wstrb;
-  assign m_axi_wlast = fifo0_m_axi_wlast;
-  assign m_axi_wuser = fifo0_m_axi_wuser;
-  assign m_axi_wvalid = fifo0_m_axi_wvalid;
-  assign fifo0_m_axi_wready = m_axi_wready;
-  assign fifo0_m_axi_bid = m_axi_bid;
-  assign fifo0_m_axi_bresp = m_axi_bresp;
-  assign fifo0_m_axi_buser = m_axi_buser;
-  assign fifo0_m_axi_bvalid = m_axi_bvalid;
-  assign m_axi_bready = fifo0_m_axi_bready;
-  assign m_axi_arid = fifo0_m_axi_arid;
-  assign m_axi_araddr = fifo0_m_axi_araddr;
-  assign m_axi_arlen = fifo0_m_axi_arlen;
-  assign m_axi_arsize = fifo0_m_axi_arsize;
-  assign m_axi_arburst = fifo0_m_axi_arburst;
-  assign m_axi_arlock = fifo0_m_axi_arlock;
-  assign m_axi_arcache = fifo0_m_axi_arcache;
-  assign m_axi_arprot = fifo0_m_axi_arprot;
-  assign m_axi_arqos = fifo0_m_axi_arqos;
-  assign m_axi_arregion = fifo0_m_axi_arregion;
-  assign m_axi_aruser = fifo0_m_axi_aruser;
-  assign m_axi_arvalid = fifo0_m_axi_arvalid;
-  assign fifo0_m_axi_arready = m_axi_arready;
-  assign fifo0_m_axi_rid = m_axi_rid;
-  assign fifo0_m_axi_rdata = m_axi_rdata;
-  assign fifo0_m_axi_rresp = m_axi_rresp;
-  assign fifo0_m_axi_rlast = m_axi_rlast;
-  assign fifo0_m_axi_ruser = m_axi_ruser;
-  assign fifo0_m_axi_rvalid = m_axi_rvalid;
-  assign m_axi_rready = fifo0_m_axi_rready;
-
   // Broadcaster/Listener Connections:
   assign radio0_radio_time = radio_time;
 
diff --git a/fpga/usrp3/top/e320/e320_rfnoc_image_core.yml b/fpga/usrp3/top/e320/e320_rfnoc_image_core.yml
index 57234c19b..e80553fdc 100644
--- a/fpga/usrp3/top/e320/e320_rfnoc_image_core.yml
+++ b/fpga/usrp3/top/e320/e320_rfnoc_image_core.yml
@@ -25,11 +25,11 @@ stream_endpoints:
   ep2:                       # Stream endpoint name
     ctrl: False                     # Endpoint passes control traffic
     data: True                      # Endpoint passes data traffic
-    buff_size: 8192                 # Ingress buffer size for data
+    buff_size: 4096                 # Ingress buffer size for data
   ep3:                       # Stream endpoint name
     ctrl: False                     # Endpoint passes control traffic
     data: True                      # Endpoint passes data traffic
-    buff_size: 8192                 # Ingress buffer size for data
+    buff_size: 4096                 # Ingress buffer size for data
 
 # A list of all NoC blocks in design
 # ----------------------------------
@@ -44,16 +44,11 @@ noc_blocks:
       NUM_PORTS: 2
   radio0:
     block_desc: 'radio_2x64.yml'
-  fifo0:
-    block_desc: 'axi_ram_fifo_2x64.yml'
+  replay0:
+    block_desc: 'replay.yml'
     parameters:
-      # These parameters correspond to the memory interface on the E320
-      MEM_ADDR_W:   31
-      MEM_DATA_W:   64
-      MEM_CLK_RATE: "300e6"
-      # Create two non-overlapping 32 MB buffers by default
-      FIFO_ADDR_BASE: "{31'h02000000, 31'h00000000}"
-      FIFO_ADDR_MASK: "{31'h01FFFFFF, 31'h01FFFFFF}"
+      NUM_PORTS: 2
+      MEM_ADDR_W: 31
 
 # A list of all static connections in design
 # ------------------------------------------
@@ -75,17 +70,19 @@ connections:
   # radio0(1) to ep1 - RF1 RX
   - { srcblk: radio0, srcport: out_1, dstblk: ddc0,   dstport: in_1 }
   - { srcblk: ddc0,   srcport: out_1, dstblk: ep1,    dstport: in0  }
-  # ep2 to fifo0(0)
-  - { srcblk: ep2,    srcport: out0,  dstblk: fifo0,  dstport: in_0 }
-  - { srcblk: fifo0,  srcport: out_0, dstblk: ep2,    dstport: in0  }
-  # ep3 to fifo0(1)
-  - { srcblk: ep3,    srcport: out0,  dstblk: fifo0,  dstport: in_1 }
-  - { srcblk: fifo0,  srcport: out_1, dstblk: ep3,    dstport: in0  }
+  # ep2 to replay0(0)
+  - { srcblk: ep2,     srcport: out0,  dstblk: replay0, dstport: in_0 }
+  # replay0(0) to ep2
+  - { srcblk: replay0, srcport: out_0, dstblk: ep2,     dstport: in0  }
+  # ep3 to replay0(1)
+  - { srcblk: ep3,     srcport: out0,  dstblk: replay0, dstport: in_1 }
+  # replay0(1) to ep3
+  - { srcblk: replay0, srcport: out_1, dstblk: ep3,     dstport: in0  }
   # BSP Connections
   - { srcblk: radio0,   srcport: ctrl_port,   dstblk: _device_, dstport: ctrl_port   }
+  - { srcblk: replay0,  srcport: axi_ram,     dstblk: _device_, dstport: dram        }
   - { srcblk: _device_, srcport: x300_radio,  dstblk: radio0,   dstport: x300_radio  }
   - { srcblk: _device_, srcport: time_keeper, dstblk: radio0,   dstport: time_keeper }
-  - { srcblk: fifo0,    srcport: axi_ram,     dstblk: _device_, dstport: dram        }
 
 # A list of all clock domain connections in design
 # ------------------------------------------------
@@ -98,4 +95,4 @@ clk_domains:
   - { srcblk: _device_, srcport: radio,      dstblk: radio0, dstport: radio }
   - { srcblk: _device_, srcport: rfnoc_chdr, dstblk: duc0,   dstport: ce    }
   - { srcblk: _device_, srcport: rfnoc_chdr, dstblk: ddc0,   dstport: ce    }
-  - { srcblk: _device_, srcport: dram,       dstblk: fifo0,  dstport: mem   }
+  - { srcblk: _device_, srcport: dram,       dstblk: replay0, dstport: mem  }
diff --git a/fpga/usrp3/top/n3xx/Makefile.n3xx.inc b/fpga/usrp3/top/n3xx/Makefile.n3xx.inc
index 5851e7daa..23258b209 100644
--- a/fpga/usrp3/top/n3xx/Makefile.n3xx.inc
+++ b/fpga/usrp3/top/n3xx/Makefile.n3xx.inc
@@ -38,12 +38,13 @@ include $(BASE_DIR)/n3xx/dboards/rh/Makefile.srcs
 include $(BASE_DIR)/n3xx/dboards/mg/Makefile.srcs
 include $(BASE_DIR)/n3xx/dboards/common/Makefile.srcs
 # For sake of convenience, we include the Makefile.srcs for DRAM FIFO, DDC, and
-# DUC, and of course the radio. Any other block needs to use the
+# DUC, Replay, and of course the radio. Any other block needs to use the
 # RFNOC_OOT_MAKEFILE_SRCS variable (see below).
 include $(LIB_DIR)/rfnoc/blocks/rfnoc_block_axi_ram_fifo/Makefile.srcs
 include $(LIB_DIR)/rfnoc/blocks/rfnoc_block_radio/Makefile.srcs
 include $(LIB_DIR)/rfnoc/blocks/rfnoc_block_ddc/Makefile.srcs
 include $(LIB_DIR)/rfnoc/blocks/rfnoc_block_duc/Makefile.srcs
+include $(LIB_DIR)/rfnoc/blocks/rfnoc_block_replay/Makefile.srcs
 # If out-of-tree modules want to be compiled into this image, then they need to
 # pass in the RFNOC_OOT_MAKEFILE_SRCS as a list of Makefile.srcs files.
 # Those files need to amend the RFNOC_OOT_SRCS variable with a list of actual
@@ -137,7 +138,8 @@ $(WHITE_RABBIT_SRCS) \
 $(RFNOC_FRAMEWORK_SRCS) \
 $(RFNOC_BLOCK_AXI_RAM_FIFO_SRCS) \
 $(RFNOC_BLOCK_DUC_SRCS) $(RFNOC_BLOCK_DDC_SRCS) \
-$(RFNOC_BLOCK_RADIO_SRCS)
+$(RFNOC_BLOCK_RADIO_SRCS) \
+$(RFNOC_BLOCK_REPLAY_SRCS)
 
 EDGE_TBL_DEF="RFNOC_EDGE_TBL_FILE=$(call RESOLVE_PATH,$(EDGE_FILE))"
 
diff --git a/fpga/usrp3/top/n3xx/n300_rfnoc_image_core.v b/fpga/usrp3/top/n3xx/n300_rfnoc_image_core.v
index 064dcf16b..43b9ffc81 100644
--- a/fpga/usrp3/top/n3xx/n300_rfnoc_image_core.v
+++ b/fpga/usrp3/top/n3xx/n300_rfnoc_image_core.v
@@ -1,5 +1,5 @@
 //
-// Copyright 2019 Ettus Research, A National Instruments Brand
+// Copyright 2020 Ettus Research, A National Instruments Brand
 //
 // SPDX-License-Identifier: LGPL-3.0-or-later
 //
@@ -7,9 +7,9 @@
 // Module: rfnoc_image_core (for n300)
 // This file was autogenerated by UHD's image builder tool (rfnoc_image_builder)
 // Re-running that tool will overwrite this file!
-// File generated on: 2019-11-08T15:58:12.572410
-// Source: ./n3xx/n300_rfnoc_image_core.yml
-// Source SHA256: 0137aa82c54cb7f7e539f2b09d75ec9c2b5d0c97479431953ab78fc8c56b7201
+// File generated on: 2020-09-02T12:02:55.936585
+// Source: ./n300_rfnoc_image_core.yml
+// Source SHA256: e9dd3107c1f434abca5d183f64dfc5e53d52192f5d488cab07b239c3b44b2593
 
 module rfnoc_image_core #(
   parameter [15:0] PROTOVER = {8'd1, 8'd0}
@@ -144,10 +144,26 @@ module rfnoc_image_core #(
   wire              ep1_to_xb_tlast ;
   wire              ep1_to_xb_tvalid;
   wire              ep1_to_xb_tready;
+  wire [CHDR_W-1:0] xb_to_ep2_tdata ;
+  wire              xb_to_ep2_tlast ;
+  wire              xb_to_ep2_tvalid;
+  wire              xb_to_ep2_tready;
+  wire [CHDR_W-1:0] ep2_to_xb_tdata ;
+  wire              ep2_to_xb_tlast ;
+  wire              ep2_to_xb_tvalid;
+  wire              ep2_to_xb_tready;
+  wire [CHDR_W-1:0] xb_to_ep3_tdata ;
+  wire              xb_to_ep3_tlast ;
+  wire              xb_to_ep3_tvalid;
+  wire              xb_to_ep3_tready;
+  wire [CHDR_W-1:0] ep3_to_xb_tdata ;
+  wire              ep3_to_xb_tlast ;
+  wire              ep3_to_xb_tvalid;
+  wire              ep3_to_xb_tready;
 
   chdr_crossbar_nxn #(
     .CHDR_W         (CHDR_W),
-    .NPORTS         (5),
+    .NPORTS         (7),
     .DEFAULT_PORT   (0),
     .MTU            (MTU),
     .ROUTE_TBL_SIZE (6),
@@ -160,14 +176,14 @@ module rfnoc_image_core #(
     .clk            (rfnoc_chdr_clk),
     .reset          (rfnoc_chdr_rst),
     .device_id      (device_id),
-    .s_axis_tdata   ({ep1_to_xb_tdata, ep0_to_xb_tdata, s_dma_tdata, s_eth1_tdata, s_eth0_tdata}),
-    .s_axis_tlast   ({ep1_to_xb_tlast, ep0_to_xb_tlast, s_dma_tlast, s_eth1_tlast, s_eth0_tlast}),
-    .s_axis_tvalid  ({ep1_to_xb_tvalid, ep0_to_xb_tvalid, s_dma_tvalid, s_eth1_tvalid, s_eth0_tvalid}),
-    .s_axis_tready  ({ep1_to_xb_tready, ep0_to_xb_tready, s_dma_tready, s_eth1_tready, s_eth0_tready}),
-    .m_axis_tdata   ({xb_to_ep1_tdata, xb_to_ep0_tdata, m_dma_tdata, m_eth1_tdata, m_eth0_tdata}),
-    .m_axis_tlast   ({xb_to_ep1_tlast, xb_to_ep0_tlast, m_dma_tlast, m_eth1_tlast, m_eth0_tlast}),
-    .m_axis_tvalid  ({xb_to_ep1_tvalid, xb_to_ep0_tvalid, m_dma_tvalid, m_eth1_tvalid, m_eth0_tvalid}),
-    .m_axis_tready  ({xb_to_ep1_tready, xb_to_ep0_tready, m_dma_tready, m_eth1_tready, m_eth0_tready}),
+    .s_axis_tdata   ({ep3_to_xb_tdata, ep2_to_xb_tdata, ep1_to_xb_tdata, ep0_to_xb_tdata, s_dma_tdata, s_eth1_tdata, s_eth0_tdata}),
+    .s_axis_tlast   ({ep3_to_xb_tlast, ep2_to_xb_tlast, ep1_to_xb_tlast, ep0_to_xb_tlast, s_dma_tlast, s_eth1_tlast, s_eth0_tlast}),
+    .s_axis_tvalid  ({ep3_to_xb_tvalid, ep2_to_xb_tvalid, ep1_to_xb_tvalid, ep0_to_xb_tvalid, s_dma_tvalid, s_eth1_tvalid, s_eth0_tvalid}),
+    .s_axis_tready  ({ep3_to_xb_tready, ep2_to_xb_tready, ep1_to_xb_tready, ep0_to_xb_tready, s_dma_tready, s_eth1_tready, s_eth0_tready}),
+    .m_axis_tdata   ({xb_to_ep3_tdata, xb_to_ep2_tdata, xb_to_ep1_tdata, xb_to_ep0_tdata, m_dma_tdata, m_eth1_tdata, m_eth0_tdata}),
+    .m_axis_tlast   ({xb_to_ep3_tlast, xb_to_ep2_tlast, xb_to_ep1_tlast, xb_to_ep0_tlast, m_dma_tlast, m_eth1_tlast, m_eth0_tlast}),
+    .m_axis_tvalid  ({xb_to_ep3_tvalid, xb_to_ep2_tvalid, xb_to_ep1_tvalid, xb_to_ep0_tvalid, m_dma_tvalid, m_eth1_tvalid, m_eth0_tvalid}),
+    .m_axis_tready  ({xb_to_ep3_tready, xb_to_ep2_tready, xb_to_ep1_tready, xb_to_ep0_tready, m_dma_tready, m_eth1_tready, m_eth0_tready}),
     .ext_rtcfg_stb  (1'h0),
     .ext_rtcfg_addr (16'h0),
     .ext_rtcfg_data (32'h0),
@@ -300,6 +316,128 @@ module rfnoc_image_core #(
     .signal_data_err    (1'b0              )
   );
 
+  wire [CHDR_W-1:0] m_ep2_out0_tdata;
+  wire              m_ep2_out0_tlast;
+  wire              m_ep2_out0_tvalid;
+  wire              m_ep2_out0_tready;
+  wire [CHDR_W-1:0] s_ep2_in0_tdata;
+  wire              s_ep2_in0_tlast;
+  wire              s_ep2_in0_tvalid;
+  wire              s_ep2_in0_tready;
+  wire [31:0]       m_ep2_ctrl_tdata , s_ep2_ctrl_tdata ;
+  wire              m_ep2_ctrl_tlast , s_ep2_ctrl_tlast ;
+  wire              m_ep2_ctrl_tvalid, s_ep2_ctrl_tvalid;
+  wire              m_ep2_ctrl_tready, s_ep2_ctrl_tready;
+
+  chdr_stream_endpoint #(
+    .PROTOVER           (PROTOVER),
+    .CHDR_W             (CHDR_W),
+    .AXIS_CTRL_EN       (0),
+    .AXIS_DATA_EN       (1),
+    .NUM_DATA_I         (1),
+    .NUM_DATA_O         (1),
+    .INST_NUM           (2),
+    .CTRL_XBAR_PORT     (3),
+    .INGRESS_BUFF_SIZE  (12),
+    .MTU                (MTU),
+    .REPORT_STRM_ERRS   (1)
+  ) ep2_i (
+    .rfnoc_chdr_clk     (rfnoc_chdr_clk    ),
+    .rfnoc_chdr_rst     (rfnoc_chdr_rst    ),
+    .rfnoc_ctrl_clk     (rfnoc_ctrl_clk    ),
+    .rfnoc_ctrl_rst     (rfnoc_ctrl_rst    ),
+    .device_id          (device_id         ),
+    .s_axis_chdr_tdata  (xb_to_ep2_tdata  ),
+    .s_axis_chdr_tlast  (xb_to_ep2_tlast  ),
+    .s_axis_chdr_tvalid (xb_to_ep2_tvalid ),
+    .s_axis_chdr_tready (xb_to_ep2_tready ),
+    .m_axis_chdr_tdata  (ep2_to_xb_tdata  ),
+    .m_axis_chdr_tlast  (ep2_to_xb_tlast  ),
+    .m_axis_chdr_tvalid (ep2_to_xb_tvalid ),
+    .m_axis_chdr_tready (ep2_to_xb_tready ),
+    .s_axis_data_tdata  ({s_ep2_in0_tdata}),
+    .s_axis_data_tlast  ({s_ep2_in0_tlast}),
+    .s_axis_data_tvalid ({s_ep2_in0_tvalid}),
+    .s_axis_data_tready ({s_ep2_in0_tready}),
+    .m_axis_data_tdata  ({m_ep2_out0_tdata}),
+    .m_axis_data_tlast  ({m_ep2_out0_tlast}),
+    .m_axis_data_tvalid ({m_ep2_out0_tvalid}),
+    .m_axis_data_tready ({m_ep2_out0_tready}),
+    .s_axis_ctrl_tdata  (s_ep2_ctrl_tdata ),
+    .s_axis_ctrl_tlast  (s_ep2_ctrl_tlast ),
+    .s_axis_ctrl_tvalid (s_ep2_ctrl_tvalid),
+    .s_axis_ctrl_tready (s_ep2_ctrl_tready),
+    .m_axis_ctrl_tdata  (m_ep2_ctrl_tdata ),
+    .m_axis_ctrl_tlast  (m_ep2_ctrl_tlast ),
+    .m_axis_ctrl_tvalid (m_ep2_ctrl_tvalid),
+    .m_axis_ctrl_tready (m_ep2_ctrl_tready),
+    .strm_seq_err_stb   (                  ),
+    .strm_data_err_stb  (                  ),
+    .strm_route_err_stb (                  ),
+    .signal_data_err    (1'b0              )
+  );
+
+  wire [CHDR_W-1:0] m_ep3_out0_tdata;
+  wire              m_ep3_out0_tlast;
+  wire              m_ep3_out0_tvalid;
+  wire              m_ep3_out0_tready;
+  wire [CHDR_W-1:0] s_ep3_in0_tdata;
+  wire              s_ep3_in0_tlast;
+  wire              s_ep3_in0_tvalid;
+  wire              s_ep3_in0_tready;
+  wire [31:0]       m_ep3_ctrl_tdata , s_ep3_ctrl_tdata ;
+  wire              m_ep3_ctrl_tlast , s_ep3_ctrl_tlast ;
+  wire              m_ep3_ctrl_tvalid, s_ep3_ctrl_tvalid;
+  wire              m_ep3_ctrl_tready, s_ep3_ctrl_tready;
+
+  chdr_stream_endpoint #(
+    .PROTOVER           (PROTOVER),
+    .CHDR_W             (CHDR_W),
+    .AXIS_CTRL_EN       (0),
+    .AXIS_DATA_EN       (1),
+    .NUM_DATA_I         (1),
+    .NUM_DATA_O         (1),
+    .INST_NUM           (3),
+    .CTRL_XBAR_PORT     (4),
+    .INGRESS_BUFF_SIZE  (12),
+    .MTU                (MTU),
+    .REPORT_STRM_ERRS   (1)
+  ) ep3_i (
+    .rfnoc_chdr_clk     (rfnoc_chdr_clk    ),
+    .rfnoc_chdr_rst     (rfnoc_chdr_rst    ),
+    .rfnoc_ctrl_clk     (rfnoc_ctrl_clk    ),
+    .rfnoc_ctrl_rst     (rfnoc_ctrl_rst    ),
+    .device_id          (device_id         ),
+    .s_axis_chdr_tdata  (xb_to_ep3_tdata  ),
+    .s_axis_chdr_tlast  (xb_to_ep3_tlast  ),
+    .s_axis_chdr_tvalid (xb_to_ep3_tvalid ),
+    .s_axis_chdr_tready (xb_to_ep3_tready ),
+    .m_axis_chdr_tdata  (ep3_to_xb_tdata  ),
+    .m_axis_chdr_tlast  (ep3_to_xb_tlast  ),
+    .m_axis_chdr_tvalid (ep3_to_xb_tvalid ),
+    .m_axis_chdr_tready (ep3_to_xb_tready ),
+    .s_axis_data_tdata  ({s_ep3_in0_tdata}),
+    .s_axis_data_tlast  ({s_ep3_in0_tlast}),
+    .s_axis_data_tvalid ({s_ep3_in0_tvalid}),
+    .s_axis_data_tready ({s_ep3_in0_tready}),
+    .m_axis_data_tdata  ({m_ep3_out0_tdata}),
+    .m_axis_data_tlast  ({m_ep3_out0_tlast}),
+    .m_axis_data_tvalid ({m_ep3_out0_tvalid}),
+    .m_axis_data_tready ({m_ep3_out0_tready}),
+    .s_axis_ctrl_tdata  (s_ep3_ctrl_tdata ),
+    .s_axis_ctrl_tlast  (s_ep3_ctrl_tlast ),
+    .s_axis_ctrl_tvalid (s_ep3_ctrl_tvalid),
+    .s_axis_ctrl_tready (s_ep3_ctrl_tready),
+    .m_axis_ctrl_tdata  (m_ep3_ctrl_tdata ),
+    .m_axis_ctrl_tlast  (m_ep3_ctrl_tlast ),
+    .m_axis_ctrl_tvalid (m_ep3_ctrl_tvalid),
+    .m_axis_ctrl_tready (m_ep3_ctrl_tready),
+    .strm_seq_err_stb   (                  ),
+    .strm_data_err_stb  (                  ),
+    .strm_route_err_stb (                  ),
+    .signal_data_err    (1'b0              )
+  );
+
 
 
   // ----------------------------------------------------
@@ -322,10 +460,14 @@ module rfnoc_image_core #(
   wire              m_radio0_ctrl_tlast ,   s_radio0_ctrl_tlast ;
   wire              m_radio0_ctrl_tvalid,   s_radio0_ctrl_tvalid;
   wire              m_radio0_ctrl_tready,   s_radio0_ctrl_tready;
+  wire [31:0]       m_replay0_ctrl_tdata ,   s_replay0_ctrl_tdata ;
+  wire              m_replay0_ctrl_tlast ,   s_replay0_ctrl_tlast ;
+  wire              m_replay0_ctrl_tvalid,   s_replay0_ctrl_tvalid;
+  wire              m_replay0_ctrl_tready,   s_replay0_ctrl_tready;
 
   axis_ctrl_crossbar_nxn #(
     .WIDTH            (32),
-    .NPORTS           (5),
+    .NPORTS           (6),
     .TOPOLOGY         ("TORUS"),
     .INGRESS_BUFF_SIZE(5),
     .ROUTER_BUFF_SIZE (5),
@@ -334,32 +476,32 @@ module rfnoc_image_core #(
   ) ctrl_xb_i (
     .clk              (rfnoc_ctrl_clk),
     .reset            (rfnoc_ctrl_rst),
-    .s_axis_tdata     ({m_radio0_ctrl_tdata , m_ddc0_ctrl_tdata , m_duc0_ctrl_tdata , m_ep0_ctrl_tdata , m_core_ctrl_tdata }),
-    .s_axis_tvalid    ({m_radio0_ctrl_tvalid, m_ddc0_ctrl_tvalid, m_duc0_ctrl_tvalid, m_ep0_ctrl_tvalid, m_core_ctrl_tvalid}),
-    .s_axis_tlast     ({m_radio0_ctrl_tlast , m_ddc0_ctrl_tlast , m_duc0_ctrl_tlast , m_ep0_ctrl_tlast , m_core_ctrl_tlast }),
-    .s_axis_tready    ({m_radio0_ctrl_tready, m_ddc0_ctrl_tready, m_duc0_ctrl_tready, m_ep0_ctrl_tready, m_core_ctrl_tready}),
-    .m_axis_tdata     ({s_radio0_ctrl_tdata , s_ddc0_ctrl_tdata , s_duc0_ctrl_tdata , s_ep0_ctrl_tdata , s_core_ctrl_tdata }),
-    .m_axis_tvalid    ({s_radio0_ctrl_tvalid, s_ddc0_ctrl_tvalid, s_duc0_ctrl_tvalid, s_ep0_ctrl_tvalid, s_core_ctrl_tvalid}),
-    .m_axis_tlast     ({s_radio0_ctrl_tlast , s_ddc0_ctrl_tlast , s_duc0_ctrl_tlast , s_ep0_ctrl_tlast , s_core_ctrl_tlast }),
-    .m_axis_tready    ({s_radio0_ctrl_tready, s_ddc0_ctrl_tready, s_duc0_ctrl_tready, s_ep0_ctrl_tready, s_core_ctrl_tready}),
+    .s_axis_tdata     ({m_replay0_ctrl_tdata , m_radio0_ctrl_tdata , m_ddc0_ctrl_tdata , m_duc0_ctrl_tdata , m_ep0_ctrl_tdata , m_core_ctrl_tdata }),
+    .s_axis_tvalid    ({m_replay0_ctrl_tvalid, m_radio0_ctrl_tvalid, m_ddc0_ctrl_tvalid, m_duc0_ctrl_tvalid, m_ep0_ctrl_tvalid, m_core_ctrl_tvalid}),
+    .s_axis_tlast     ({m_replay0_ctrl_tlast , m_radio0_ctrl_tlast , m_ddc0_ctrl_tlast , m_duc0_ctrl_tlast , m_ep0_ctrl_tlast , m_core_ctrl_tlast }),
+    .s_axis_tready    ({m_replay0_ctrl_tready, m_radio0_ctrl_tready, m_ddc0_ctrl_tready, m_duc0_ctrl_tready, m_ep0_ctrl_tready, m_core_ctrl_tready}),
+    .m_axis_tdata     ({s_replay0_ctrl_tdata , s_radio0_ctrl_tdata , s_ddc0_ctrl_tdata , s_duc0_ctrl_tdata , s_ep0_ctrl_tdata , s_core_ctrl_tdata }),
+    .m_axis_tvalid    ({s_replay0_ctrl_tvalid, s_radio0_ctrl_tvalid, s_ddc0_ctrl_tvalid, s_duc0_ctrl_tvalid, s_ep0_ctrl_tvalid, s_core_ctrl_tvalid}),
+    .m_axis_tlast     ({s_replay0_ctrl_tlast , s_radio0_ctrl_tlast , s_ddc0_ctrl_tlast , s_duc0_ctrl_tlast , s_ep0_ctrl_tlast , s_core_ctrl_tlast }),
+    .m_axis_tready    ({s_replay0_ctrl_tready, s_radio0_ctrl_tready, s_ddc0_ctrl_tready, s_duc0_ctrl_tready, s_ep0_ctrl_tready, s_core_ctrl_tready}),
     .deadlock_detected()
   );
 
   // ----------------------------------------------------
   // RFNoC Core Kernel
   // ----------------------------------------------------
-  wire [(512*3)-1:0] rfnoc_core_config, rfnoc_core_status;
+  wire [(512*4)-1:0] rfnoc_core_config, rfnoc_core_status;
 
   rfnoc_core_kernel #(
     .PROTOVER            (PROTOVER),
     .DEVICE_TYPE         (16'h1300),
     .DEVICE_FAMILY       ("7SERIES"),
     .SAFE_START_CLKS     (0),
-    .NUM_BLOCKS          (3),
-    .NUM_STREAM_ENDPOINTS(2),
+    .NUM_BLOCKS          (4),
+    .NUM_STREAM_ENDPOINTS(4),
     .NUM_ENDPOINTS_CTRL  (1),
     .NUM_TRANSPORTS      (3),
-    .NUM_EDGES           (8),
+    .NUM_EDGES           (12),
     .CHDR_XBAR_PRESENT   (1),
     .EDGE_TBL_FILE       (EDGE_TBL_FILE)
   ) core_kernel_i (
@@ -569,6 +711,145 @@ module rfnoc_image_core #(
 
 
   // ----------------------------------------------------
+  // replay0
+  // ----------------------------------------------------
+  wire              replay0_mem_clk;
+  wire [CHDR_W-1:0] s_replay0_in_1_tdata , s_replay0_in_0_tdata ;
+  wire              s_replay0_in_1_tlast , s_replay0_in_0_tlast ;
+  wire              s_replay0_in_1_tvalid, s_replay0_in_0_tvalid;
+  wire              s_replay0_in_1_tready, s_replay0_in_0_tready;
+  wire [CHDR_W-1:0] m_replay0_out_1_tdata , m_replay0_out_0_tdata ;
+  wire              m_replay0_out_1_tlast , m_replay0_out_0_tlast ;
+  wire              m_replay0_out_1_tvalid, m_replay0_out_0_tvalid;
+  wire              m_replay0_out_1_tready, m_replay0_out_0_tready;
+
+  //  axi_ram
+  wire [  1-1:0] replay0_axi_rst;
+  wire [  4-1:0] replay0_m_axi_awid;
+  wire [128-1:0] replay0_m_axi_awaddr;
+  wire [ 32-1:0] replay0_m_axi_awlen;
+  wire [ 12-1:0] replay0_m_axi_awsize;
+  wire [  8-1:0] replay0_m_axi_awburst;
+  wire [  4-1:0] replay0_m_axi_awlock;
+  wire [ 16-1:0] replay0_m_axi_awcache;
+  wire [ 12-1:0] replay0_m_axi_awprot;
+  wire [ 16-1:0] replay0_m_axi_awqos;
+  wire [ 16-1:0] replay0_m_axi_awregion;
+  wire [  4-1:0] replay0_m_axi_awuser;
+  wire [  4-1:0] replay0_m_axi_awvalid;
+  wire [  4-1:0] replay0_m_axi_awready;
+  wire [256-1:0] replay0_m_axi_wdata;
+  wire [ 32-1:0] replay0_m_axi_wstrb;
+  wire [  4-1:0] replay0_m_axi_wlast;
+  wire [  4-1:0] replay0_m_axi_wuser;
+  wire [  4-1:0] replay0_m_axi_wvalid;
+  wire [  4-1:0] replay0_m_axi_wready;
+  wire [  4-1:0] replay0_m_axi_bid;
+  wire [  8-1:0] replay0_m_axi_bresp;
+  wire [  4-1:0] replay0_m_axi_buser;
+  wire [  4-1:0] replay0_m_axi_bvalid;
+  wire [  4-1:0] replay0_m_axi_bready;
+  wire [  4-1:0] replay0_m_axi_arid;
+  wire [128-1:0] replay0_m_axi_araddr;
+  wire [ 32-1:0] replay0_m_axi_arlen;
+  wire [ 12-1:0] replay0_m_axi_arsize;
+  wire [  8-1:0] replay0_m_axi_arburst;
+  wire [  4-1:0] replay0_m_axi_arlock;
+  wire [ 16-1:0] replay0_m_axi_arcache;
+  wire [ 12-1:0] replay0_m_axi_arprot;
+  wire [ 16-1:0] replay0_m_axi_arqos;
+  wire [ 16-1:0] replay0_m_axi_arregion;
+  wire [  4-1:0] replay0_m_axi_aruser;
+  wire [  4-1:0] replay0_m_axi_arvalid;
+  wire [  4-1:0] replay0_m_axi_arready;
+  wire [  4-1:0] replay0_m_axi_rid;
+  wire [256-1:0] replay0_m_axi_rdata;
+  wire [  8-1:0] replay0_m_axi_rresp;
+  wire [  4-1:0] replay0_m_axi_rlast;
+  wire [  4-1:0] replay0_m_axi_ruser;
+  wire [  4-1:0] replay0_m_axi_rvalid;
+  wire [  4-1:0] replay0_m_axi_rready;
+
+  rfnoc_block_replay #(
+    .THIS_PORTID(5),
+    .CHDR_W(CHDR_W),
+    .NUM_PORTS(2),
+    .MEM_ADDR_W(31),
+    .MEM_DATA_W(64),
+    .MTU(MTU)
+  ) b_replay0_3 (
+    .rfnoc_chdr_clk     (rfnoc_chdr_clk),
+    .rfnoc_ctrl_clk     (rfnoc_ctrl_clk),
+    .mem_clk(replay0_mem_clk),
+    .rfnoc_core_config  (rfnoc_core_config[512*4-1:512*3]),
+    .rfnoc_core_status  (rfnoc_core_status[512*4-1:512*3]),
+
+    .axi_rst(replay0_axi_rst),
+    .m_axi_awid(replay0_m_axi_awid),
+    .m_axi_awaddr(replay0_m_axi_awaddr),
+    .m_axi_awlen(replay0_m_axi_awlen),
+    .m_axi_awsize(replay0_m_axi_awsize),
+    .m_axi_awburst(replay0_m_axi_awburst),
+    .m_axi_awlock(replay0_m_axi_awlock),
+    .m_axi_awcache(replay0_m_axi_awcache),
+    .m_axi_awprot(replay0_m_axi_awprot),
+    .m_axi_awqos(replay0_m_axi_awqos),
+    .m_axi_awregion(replay0_m_axi_awregion),
+    .m_axi_awuser(replay0_m_axi_awuser),
+    .m_axi_awvalid(replay0_m_axi_awvalid),
+    .m_axi_awready(replay0_m_axi_awready),
+    .m_axi_wdata(replay0_m_axi_wdata),
+    .m_axi_wstrb(replay0_m_axi_wstrb),
+    .m_axi_wlast(replay0_m_axi_wlast),
+    .m_axi_wuser(replay0_m_axi_wuser),
+    .m_axi_wvalid(replay0_m_axi_wvalid),
+    .m_axi_wready(replay0_m_axi_wready),
+    .m_axi_bid(replay0_m_axi_bid),
+    .m_axi_bresp(replay0_m_axi_bresp),
+    .m_axi_buser(replay0_m_axi_buser),
+    .m_axi_bvalid(replay0_m_axi_bvalid),
+    .m_axi_bready(replay0_m_axi_bready),
+    .m_axi_arid(replay0_m_axi_arid),
+    .m_axi_araddr(replay0_m_axi_araddr),
+    .m_axi_arlen(replay0_m_axi_arlen),
+    .m_axi_arsize(replay0_m_axi_arsize),
+    .m_axi_arburst(replay0_m_axi_arburst),
+    .m_axi_arlock(replay0_m_axi_arlock),
+    .m_axi_arcache(replay0_m_axi_arcache),
+    .m_axi_arprot(replay0_m_axi_arprot),
+    .m_axi_arqos(replay0_m_axi_arqos),
+    .m_axi_arregion(replay0_m_axi_arregion),
+    .m_axi_aruser(replay0_m_axi_aruser),
+    .m_axi_arvalid(replay0_m_axi_arvalid),
+    .m_axi_arready(replay0_m_axi_arready),
+    .m_axi_rid(replay0_m_axi_rid),
+    .m_axi_rdata(replay0_m_axi_rdata),
+    .m_axi_rresp(replay0_m_axi_rresp),
+    .m_axi_rlast(replay0_m_axi_rlast),
+    .m_axi_ruser(replay0_m_axi_ruser),
+    .m_axi_rvalid(replay0_m_axi_rvalid),
+    .m_axi_rready(replay0_m_axi_rready),
+
+    .s_rfnoc_chdr_tdata ({s_replay0_in_1_tdata , s_replay0_in_0_tdata }),
+    .s_rfnoc_chdr_tlast ({s_replay0_in_1_tlast , s_replay0_in_0_tlast }),
+    .s_rfnoc_chdr_tvalid({s_replay0_in_1_tvalid, s_replay0_in_0_tvalid}),
+    .s_rfnoc_chdr_tready({s_replay0_in_1_tready, s_replay0_in_0_tready}),
+    .m_rfnoc_chdr_tdata ({m_replay0_out_1_tdata , m_replay0_out_0_tdata }),
+    .m_rfnoc_chdr_tlast ({m_replay0_out_1_tlast , m_replay0_out_0_tlast }),
+    .m_rfnoc_chdr_tvalid({m_replay0_out_1_tvalid, m_replay0_out_0_tvalid}),
+    .m_rfnoc_chdr_tready({m_replay0_out_1_tready, m_replay0_out_0_tready}),
+    .s_rfnoc_ctrl_tdata (s_replay0_ctrl_tdata ),
+    .s_rfnoc_ctrl_tlast (s_replay0_ctrl_tlast ),
+    .s_rfnoc_ctrl_tvalid(s_replay0_ctrl_tvalid),
+    .s_rfnoc_ctrl_tready(s_replay0_ctrl_tready),
+    .m_rfnoc_ctrl_tdata (m_replay0_ctrl_tdata ),
+    .m_rfnoc_ctrl_tlast (m_replay0_ctrl_tlast ),
+    .m_rfnoc_ctrl_tvalid(m_replay0_ctrl_tvalid),
+    .m_rfnoc_ctrl_tready(m_replay0_ctrl_tready)
+  );
+
+
+  // ----------------------------------------------------
   // Static Router
   // ----------------------------------------------------
   assign s_duc0_in_0_tdata = m_ep0_out0_tdata ;
@@ -611,6 +892,26 @@ module rfnoc_image_core #(
   assign s_ep1_in0_tvalid = m_ddc0_out_1_tvalid;
   assign m_ddc0_out_1_tready = s_ep1_in0_tready;
 
+  assign s_replay0_in_0_tdata = m_ep2_out0_tdata ;
+  assign s_replay0_in_0_tlast = m_ep2_out0_tlast ;
+  assign s_replay0_in_0_tvalid = m_ep2_out0_tvalid;
+  assign m_ep2_out0_tready = s_replay0_in_0_tready;
+
+  assign s_ep2_in0_tdata = m_replay0_out_0_tdata ;
+  assign s_ep2_in0_tlast = m_replay0_out_0_tlast ;
+  assign s_ep2_in0_tvalid = m_replay0_out_0_tvalid;
+  assign m_replay0_out_0_tready = s_ep2_in0_tready;
+
+  assign s_replay0_in_1_tdata = m_ep3_out0_tdata ;
+  assign s_replay0_in_1_tlast = m_ep3_out0_tlast ;
+  assign s_replay0_in_1_tvalid = m_ep3_out0_tvalid;
+  assign m_ep3_out0_tready = s_replay0_in_1_tready;
+
+  assign s_ep3_in0_tdata = m_replay0_out_1_tdata ;
+  assign s_ep3_in0_tlast = m_replay0_out_1_tlast ;
+  assign s_ep3_in0_tvalid = m_replay0_out_1_tvalid;
+  assign m_replay0_out_1_tready = s_ep3_in0_tready;
+
 
   // ----------------------------------------------------
   // Unused Ports
@@ -622,6 +923,7 @@ module rfnoc_image_core #(
   assign radio0_radio_clk = radio_clk;
   assign ddc0_ce_clk = rfnoc_chdr_clk;
   assign duc0_ce_clk = rfnoc_chdr_clk;
+  assign replay0_mem_clk = dram_clk;
 
 
   // ----------------------------------------------------
@@ -639,6 +941,52 @@ module rfnoc_image_core #(
   assign radio0_m_ctrlport_resp_status = m_ctrlport_radio0_resp_status;
   assign radio0_m_ctrlport_resp_data = m_ctrlport_radio0_resp_data;
 
+  assign replay0_axi_rst = axi_rst;
+  assign m_axi_awid = replay0_m_axi_awid;
+  assign m_axi_awaddr = replay0_m_axi_awaddr;
+  assign m_axi_awlen = replay0_m_axi_awlen;
+  assign m_axi_awsize = replay0_m_axi_awsize;
+  assign m_axi_awburst = replay0_m_axi_awburst;
+  assign m_axi_awlock = replay0_m_axi_awlock;
+  assign m_axi_awcache = replay0_m_axi_awcache;
+  assign m_axi_awprot = replay0_m_axi_awprot;
+  assign m_axi_awqos = replay0_m_axi_awqos;
+  assign m_axi_awregion = replay0_m_axi_awregion;
+  assign m_axi_awuser = replay0_m_axi_awuser;
+  assign m_axi_awvalid = replay0_m_axi_awvalid;
+  assign replay0_m_axi_awready = m_axi_awready;
+  assign m_axi_wdata = replay0_m_axi_wdata;
+  assign m_axi_wstrb = replay0_m_axi_wstrb;
+  assign m_axi_wlast = replay0_m_axi_wlast;
+  assign m_axi_wuser = replay0_m_axi_wuser;
+  assign m_axi_wvalid = replay0_m_axi_wvalid;
+  assign replay0_m_axi_wready = m_axi_wready;
+  assign replay0_m_axi_bid = m_axi_bid;
+  assign replay0_m_axi_bresp = m_axi_bresp;
+  assign replay0_m_axi_buser = m_axi_buser;
+  assign replay0_m_axi_bvalid = m_axi_bvalid;
+  assign m_axi_bready = replay0_m_axi_bready;
+  assign m_axi_arid = replay0_m_axi_arid;
+  assign m_axi_araddr = replay0_m_axi_araddr;
+  assign m_axi_arlen = replay0_m_axi_arlen;
+  assign m_axi_arsize = replay0_m_axi_arsize;
+  assign m_axi_arburst = replay0_m_axi_arburst;
+  assign m_axi_arlock = replay0_m_axi_arlock;
+  assign m_axi_arcache = replay0_m_axi_arcache;
+  assign m_axi_arprot = replay0_m_axi_arprot;
+  assign m_axi_arqos = replay0_m_axi_arqos;
+  assign m_axi_arregion = replay0_m_axi_arregion;
+  assign m_axi_aruser = replay0_m_axi_aruser;
+  assign m_axi_arvalid = replay0_m_axi_arvalid;
+  assign replay0_m_axi_arready = m_axi_arready;
+  assign replay0_m_axi_rid = m_axi_rid;
+  assign replay0_m_axi_rdata = m_axi_rdata;
+  assign replay0_m_axi_rresp = m_axi_rresp;
+  assign replay0_m_axi_rlast = m_axi_rlast;
+  assign replay0_m_axi_ruser = m_axi_ruser;
+  assign replay0_m_axi_rvalid = m_axi_rvalid;
+  assign m_axi_rready = replay0_m_axi_rready;
+
   assign radio0_radio_rx_data = radio_rx_data_radio0;
   assign radio0_radio_rx_stb = radio_rx_stb_radio0;
   assign radio_rx_running_radio0 = radio0_radio_rx_running;
diff --git a/fpga/usrp3/top/n3xx/n300_rfnoc_image_core.yml b/fpga/usrp3/top/n3xx/n300_rfnoc_image_core.yml
index 54df51725..3b28fcd14 100644
--- a/fpga/usrp3/top/n3xx/n300_rfnoc_image_core.yml
+++ b/fpga/usrp3/top/n3xx/n300_rfnoc_image_core.yml
@@ -20,6 +20,14 @@ stream_endpoints:
     ctrl: False                     # Endpoint passes control traffic
     data: True                      # Endpoint passes data traffic
     buff_size: 32768                # Ingress buffer size for data
+  ep2:                       # Stream endpoint name
+    ctrl: False                     # Endpoint passes control traffic
+    data: True                      # Endpoint passes data traffic
+    buff_size: 4096                 # Ingress buffer size for data
+  ep3:                       # Stream endpoint name
+    ctrl: False                     # Endpoint passes control traffic
+    data: True                      # Endpoint passes data traffic
+    buff_size: 4096                 # Ingress buffer size for data
 
 # A list of all NoC blocks in design
 # ----------------------------------
@@ -34,16 +42,11 @@ noc_blocks:
       NUM_PORTS: 2
   radio0:
     block_desc: 'radio_2x64.yml'
-  #fifo0:
-    #block_desc: 'axi_ram_fifo_4x64.yml'
-    #parameters:
-      ## These parameters match the memory interface on the N3XX
-      #NUM_PORTS: 4
-      #MEM_DATA_W: 64
-      #MEM_ADDR_W: 31
-      #FIFO_ADDR_BASE: "{30'h06000000, 30'h04000000, 30'h02000000, 30'h00000000}"
-      #FIFO_ADDR_MASK: "{30'h01FFFFFF, 30'h01FFFFFF, 30'h01FFFFFF, 30'h01FFFFFF}"
-      #MEM_CLK_RATE: "303819444" # 166.666666 MHz * 21.875 / 4 / 3 = 303.819444 MHz
+  replay0:
+    block_desc: 'replay.yml'
+    parameters:
+      NUM_PORTS: 2
+      MEM_ADDR_W: 31
 
 # A list of all static connections in design
 # ------------------------------------------
@@ -61,7 +64,12 @@ connections:
   - { srcblk: duc0,   srcport: out_1, dstblk: radio0, dstport: in_1 }
   - { srcblk: radio0, srcport: out_1, dstblk: ddc0,   dstport: in_1 }
   - { srcblk: ddc0,   srcport: out_1, dstblk: ep1,    dstport: in0  }
+  - { srcblk: ep2,     srcport: out0,  dstblk: replay0, dstport: in_0 }
+  - { srcblk: replay0, srcport: out_0, dstblk: ep2,     dstport: in0  }
+  - { srcblk: ep3,     srcport: out0,  dstblk: replay0, dstport: in_1 }
+  - { srcblk: replay0, srcport: out_1, dstblk: ep3,     dstport: in0  }
   - { srcblk: radio0, srcport: ctrl_port, dstblk: _device_, dstport: ctrlport_radio0 }
+  - { srcblk: replay0, srcport: axi_ram, dstblk: _device_, dstport: dram }
   - { srcblk: _device_, srcport: x300_radio0, dstblk: radio0, dstport: x300_radio }
   - { srcblk: _device_, srcport: time_keeper, dstblk: radio0, dstport: time_keeper }
 
@@ -76,3 +84,4 @@ clk_domains:
   - { srcblk: _device_, srcport: radio,      dstblk: radio0, dstport: radio }
   - { srcblk: _device_, srcport: rfnoc_chdr, dstblk: ddc0,   dstport: ce    }
   - { srcblk: _device_, srcport: rfnoc_chdr, dstblk: duc0,   dstport: ce    }
+  - { srcblk: _device_, srcport: dram,       dstblk: replay0, dstport: mem  }
diff --git a/fpga/usrp3/top/n3xx/n300_static_router.hex b/fpga/usrp3/top/n3xx/n300_static_router.hex
index 6e8701d3a..6217eaf68 100644
--- a/fpga/usrp3/top/n3xx/n300_static_router.hex
+++ b/fpga/usrp3/top/n3xx/n300_static_router.hex
@@ -1,9 +1,13 @@
-00000008
-004000c0
-00c00140
-01400100
-01000040
-008000c1
-00c10141
-01410101
-01010080
+0000000C
+00400140
+014001c0
+01c00180
+01800040
+00800141
+014101c1
+01c10181
+01810080
+00c00200
+020000c0
+01000201
+02010100
diff --git a/fpga/usrp3/top/n3xx/n310_rfnoc_image_core.v b/fpga/usrp3/top/n3xx/n310_rfnoc_image_core.v
index 027f176ce..3ded945ac 100644
--- a/fpga/usrp3/top/n3xx/n310_rfnoc_image_core.v
+++ b/fpga/usrp3/top/n3xx/n310_rfnoc_image_core.v
@@ -1,5 +1,5 @@
 //
-// Copyright 2019 Ettus Research, A National Instruments Brand
+// Copyright 2020 Ettus Research, A National Instruments Brand
 //
 // SPDX-License-Identifier: LGPL-3.0-or-later
 //
@@ -7,9 +7,9 @@
 // Module: rfnoc_image_core (for n310)
 // This file was autogenerated by UHD's image builder tool (rfnoc_image_builder)
 // Re-running that tool will overwrite this file!
-// File generated on: 2019-11-08T15:58:13.073656
-// Source: ./n3xx/n310_rfnoc_image_core.yml
-// Source SHA256: a4a2464a5fdebb8ac35e78c2ea53ad7be23f8106376098188c9a4caeba8bcf0e
+// File generated on: 2020-09-02T12:03:00.129190
+// Source: ./n310_rfnoc_image_core.yml
+// Source SHA256: 39427a6d2533bc5342e99d75d7eaff9368e89ab8ff639821d333143af5ace45b
 
 module rfnoc_image_core #(
   parameter [15:0] PROTOVER = {8'd1, 8'd0}
@@ -178,10 +178,42 @@ module rfnoc_image_core #(
   wire              ep3_to_xb_tlast ;
   wire              ep3_to_xb_tvalid;
   wire              ep3_to_xb_tready;
+  wire [CHDR_W-1:0] xb_to_ep4_tdata ;
+  wire              xb_to_ep4_tlast ;
+  wire              xb_to_ep4_tvalid;
+  wire              xb_to_ep4_tready;
+  wire [CHDR_W-1:0] ep4_to_xb_tdata ;
+  wire              ep4_to_xb_tlast ;
+  wire              ep4_to_xb_tvalid;
+  wire              ep4_to_xb_tready;
+  wire [CHDR_W-1:0] xb_to_ep5_tdata ;
+  wire              xb_to_ep5_tlast ;
+  wire              xb_to_ep5_tvalid;
+  wire              xb_to_ep5_tready;
+  wire [CHDR_W-1:0] ep5_to_xb_tdata ;
+  wire              ep5_to_xb_tlast ;
+  wire              ep5_to_xb_tvalid;
+  wire              ep5_to_xb_tready;
+  wire [CHDR_W-1:0] xb_to_ep6_tdata ;
+  wire              xb_to_ep6_tlast ;
+  wire              xb_to_ep6_tvalid;
+  wire              xb_to_ep6_tready;
+  wire [CHDR_W-1:0] ep6_to_xb_tdata ;
+  wire              ep6_to_xb_tlast ;
+  wire              ep6_to_xb_tvalid;
+  wire              ep6_to_xb_tready;
+  wire [CHDR_W-1:0] xb_to_ep7_tdata ;
+  wire              xb_to_ep7_tlast ;
+  wire              xb_to_ep7_tvalid;
+  wire              xb_to_ep7_tready;
+  wire [CHDR_W-1:0] ep7_to_xb_tdata ;
+  wire              ep7_to_xb_tlast ;
+  wire              ep7_to_xb_tvalid;
+  wire              ep7_to_xb_tready;
 
   chdr_crossbar_nxn #(
     .CHDR_W         (CHDR_W),
-    .NPORTS         (7),
+    .NPORTS         (11),
     .DEFAULT_PORT   (0),
     .MTU            (MTU),
     .ROUTE_TBL_SIZE (6),
@@ -194,14 +226,14 @@ module rfnoc_image_core #(
     .clk            (rfnoc_chdr_clk),
     .reset          (rfnoc_chdr_rst),
     .device_id      (device_id),
-    .s_axis_tdata   ({ep3_to_xb_tdata, ep2_to_xb_tdata, ep1_to_xb_tdata, ep0_to_xb_tdata, s_dma_tdata, s_eth1_tdata, s_eth0_tdata}),
-    .s_axis_tlast   ({ep3_to_xb_tlast, ep2_to_xb_tlast, ep1_to_xb_tlast, ep0_to_xb_tlast, s_dma_tlast, s_eth1_tlast, s_eth0_tlast}),
-    .s_axis_tvalid  ({ep3_to_xb_tvalid, ep2_to_xb_tvalid, ep1_to_xb_tvalid, ep0_to_xb_tvalid, s_dma_tvalid, s_eth1_tvalid, s_eth0_tvalid}),
-    .s_axis_tready  ({ep3_to_xb_tready, ep2_to_xb_tready, ep1_to_xb_tready, ep0_to_xb_tready, s_dma_tready, s_eth1_tready, s_eth0_tready}),
-    .m_axis_tdata   ({xb_to_ep3_tdata, xb_to_ep2_tdata, xb_to_ep1_tdata, xb_to_ep0_tdata, m_dma_tdata, m_eth1_tdata, m_eth0_tdata}),
-    .m_axis_tlast   ({xb_to_ep3_tlast, xb_to_ep2_tlast, xb_to_ep1_tlast, xb_to_ep0_tlast, m_dma_tlast, m_eth1_tlast, m_eth0_tlast}),
-    .m_axis_tvalid  ({xb_to_ep3_tvalid, xb_to_ep2_tvalid, xb_to_ep1_tvalid, xb_to_ep0_tvalid, m_dma_tvalid, m_eth1_tvalid, m_eth0_tvalid}),
-    .m_axis_tready  ({xb_to_ep3_tready, xb_to_ep2_tready, xb_to_ep1_tready, xb_to_ep0_tready, m_dma_tready, m_eth1_tready, m_eth0_tready}),
+    .s_axis_tdata   ({ep7_to_xb_tdata, ep6_to_xb_tdata, ep5_to_xb_tdata, ep4_to_xb_tdata, ep3_to_xb_tdata, ep2_to_xb_tdata, ep1_to_xb_tdata, ep0_to_xb_tdata, s_dma_tdata, s_eth1_tdata, s_eth0_tdata}),
+    .s_axis_tlast   ({ep7_to_xb_tlast, ep6_to_xb_tlast, ep5_to_xb_tlast, ep4_to_xb_tlast, ep3_to_xb_tlast, ep2_to_xb_tlast, ep1_to_xb_tlast, ep0_to_xb_tlast, s_dma_tlast, s_eth1_tlast, s_eth0_tlast}),
+    .s_axis_tvalid  ({ep7_to_xb_tvalid, ep6_to_xb_tvalid, ep5_to_xb_tvalid, ep4_to_xb_tvalid, ep3_to_xb_tvalid, ep2_to_xb_tvalid, ep1_to_xb_tvalid, ep0_to_xb_tvalid, s_dma_tvalid, s_eth1_tvalid, s_eth0_tvalid}),
+    .s_axis_tready  ({ep7_to_xb_tready, ep6_to_xb_tready, ep5_to_xb_tready, ep4_to_xb_tready, ep3_to_xb_tready, ep2_to_xb_tready, ep1_to_xb_tready, ep0_to_xb_tready, s_dma_tready, s_eth1_tready, s_eth0_tready}),
+    .m_axis_tdata   ({xb_to_ep7_tdata, xb_to_ep6_tdata, xb_to_ep5_tdata, xb_to_ep4_tdata, xb_to_ep3_tdata, xb_to_ep2_tdata, xb_to_ep1_tdata, xb_to_ep0_tdata, m_dma_tdata, m_eth1_tdata, m_eth0_tdata}),
+    .m_axis_tlast   ({xb_to_ep7_tlast, xb_to_ep6_tlast, xb_to_ep5_tlast, xb_to_ep4_tlast, xb_to_ep3_tlast, xb_to_ep2_tlast, xb_to_ep1_tlast, xb_to_ep0_tlast, m_dma_tlast, m_eth1_tlast, m_eth0_tlast}),
+    .m_axis_tvalid  ({xb_to_ep7_tvalid, xb_to_ep6_tvalid, xb_to_ep5_tvalid, xb_to_ep4_tvalid, xb_to_ep3_tvalid, xb_to_ep2_tvalid, xb_to_ep1_tvalid, xb_to_ep0_tvalid, m_dma_tvalid, m_eth1_tvalid, m_eth0_tvalid}),
+    .m_axis_tready  ({xb_to_ep7_tready, xb_to_ep6_tready, xb_to_ep5_tready, xb_to_ep4_tready, xb_to_ep3_tready, xb_to_ep2_tready, xb_to_ep1_tready, xb_to_ep0_tready, m_dma_tready, m_eth1_tready, m_eth0_tready}),
     .ext_rtcfg_stb  (1'h0),
     .ext_rtcfg_addr (16'h0),
     .ext_rtcfg_data (32'h0),
@@ -456,6 +488,250 @@ module rfnoc_image_core #(
     .signal_data_err    (1'b0              )
   );
 
+  wire [CHDR_W-1:0] m_ep4_out0_tdata;
+  wire              m_ep4_out0_tlast;
+  wire              m_ep4_out0_tvalid;
+  wire              m_ep4_out0_tready;
+  wire [CHDR_W-1:0] s_ep4_in0_tdata;
+  wire              s_ep4_in0_tlast;
+  wire              s_ep4_in0_tvalid;
+  wire              s_ep4_in0_tready;
+  wire [31:0]       m_ep4_ctrl_tdata , s_ep4_ctrl_tdata ;
+  wire              m_ep4_ctrl_tlast , s_ep4_ctrl_tlast ;
+  wire              m_ep4_ctrl_tvalid, s_ep4_ctrl_tvalid;
+  wire              m_ep4_ctrl_tready, s_ep4_ctrl_tready;
+
+  chdr_stream_endpoint #(
+    .PROTOVER           (PROTOVER),
+    .CHDR_W             (CHDR_W),
+    .AXIS_CTRL_EN       (0),
+    .AXIS_DATA_EN       (1),
+    .NUM_DATA_I         (1),
+    .NUM_DATA_O         (1),
+    .INST_NUM           (4),
+    .CTRL_XBAR_PORT     (5),
+    .INGRESS_BUFF_SIZE  (12),
+    .MTU                (MTU),
+    .REPORT_STRM_ERRS   (1)
+  ) ep4_i (
+    .rfnoc_chdr_clk     (rfnoc_chdr_clk    ),
+    .rfnoc_chdr_rst     (rfnoc_chdr_rst    ),
+    .rfnoc_ctrl_clk     (rfnoc_ctrl_clk    ),
+    .rfnoc_ctrl_rst     (rfnoc_ctrl_rst    ),
+    .device_id          (device_id         ),
+    .s_axis_chdr_tdata  (xb_to_ep4_tdata  ),
+    .s_axis_chdr_tlast  (xb_to_ep4_tlast  ),
+    .s_axis_chdr_tvalid (xb_to_ep4_tvalid ),
+    .s_axis_chdr_tready (xb_to_ep4_tready ),
+    .m_axis_chdr_tdata  (ep4_to_xb_tdata  ),
+    .m_axis_chdr_tlast  (ep4_to_xb_tlast  ),
+    .m_axis_chdr_tvalid (ep4_to_xb_tvalid ),
+    .m_axis_chdr_tready (ep4_to_xb_tready ),
+    .s_axis_data_tdata  ({s_ep4_in0_tdata}),
+    .s_axis_data_tlast  ({s_ep4_in0_tlast}),
+    .s_axis_data_tvalid ({s_ep4_in0_tvalid}),
+    .s_axis_data_tready ({s_ep4_in0_tready}),
+    .m_axis_data_tdata  ({m_ep4_out0_tdata}),
+    .m_axis_data_tlast  ({m_ep4_out0_tlast}),
+    .m_axis_data_tvalid ({m_ep4_out0_tvalid}),
+    .m_axis_data_tready ({m_ep4_out0_tready}),
+    .s_axis_ctrl_tdata  (s_ep4_ctrl_tdata ),
+    .s_axis_ctrl_tlast  (s_ep4_ctrl_tlast ),
+    .s_axis_ctrl_tvalid (s_ep4_ctrl_tvalid),
+    .s_axis_ctrl_tready (s_ep4_ctrl_tready),
+    .m_axis_ctrl_tdata  (m_ep4_ctrl_tdata ),
+    .m_axis_ctrl_tlast  (m_ep4_ctrl_tlast ),
+    .m_axis_ctrl_tvalid (m_ep4_ctrl_tvalid),
+    .m_axis_ctrl_tready (m_ep4_ctrl_tready),
+    .strm_seq_err_stb   (                  ),
+    .strm_data_err_stb  (                  ),
+    .strm_route_err_stb (                  ),
+    .signal_data_err    (1'b0              )
+  );
+
+  wire [CHDR_W-1:0] m_ep5_out0_tdata;
+  wire              m_ep5_out0_tlast;
+  wire              m_ep5_out0_tvalid;
+  wire              m_ep5_out0_tready;
+  wire [CHDR_W-1:0] s_ep5_in0_tdata;
+  wire              s_ep5_in0_tlast;
+  wire              s_ep5_in0_tvalid;
+  wire              s_ep5_in0_tready;
+  wire [31:0]       m_ep5_ctrl_tdata , s_ep5_ctrl_tdata ;
+  wire              m_ep5_ctrl_tlast , s_ep5_ctrl_tlast ;
+  wire              m_ep5_ctrl_tvalid, s_ep5_ctrl_tvalid;
+  wire              m_ep5_ctrl_tready, s_ep5_ctrl_tready;
+
+  chdr_stream_endpoint #(
+    .PROTOVER           (PROTOVER),
+    .CHDR_W             (CHDR_W),
+    .AXIS_CTRL_EN       (0),
+    .AXIS_DATA_EN       (1),
+    .NUM_DATA_I         (1),
+    .NUM_DATA_O         (1),
+    .INST_NUM           (5),
+    .CTRL_XBAR_PORT     (6),
+    .INGRESS_BUFF_SIZE  (12),
+    .MTU                (MTU),
+    .REPORT_STRM_ERRS   (1)
+  ) ep5_i (
+    .rfnoc_chdr_clk     (rfnoc_chdr_clk    ),
+    .rfnoc_chdr_rst     (rfnoc_chdr_rst    ),
+    .rfnoc_ctrl_clk     (rfnoc_ctrl_clk    ),
+    .rfnoc_ctrl_rst     (rfnoc_ctrl_rst    ),
+    .device_id          (device_id         ),
+    .s_axis_chdr_tdata  (xb_to_ep5_tdata  ),
+    .s_axis_chdr_tlast  (xb_to_ep5_tlast  ),
+    .s_axis_chdr_tvalid (xb_to_ep5_tvalid ),
+    .s_axis_chdr_tready (xb_to_ep5_tready ),
+    .m_axis_chdr_tdata  (ep5_to_xb_tdata  ),
+    .m_axis_chdr_tlast  (ep5_to_xb_tlast  ),
+    .m_axis_chdr_tvalid (ep5_to_xb_tvalid ),
+    .m_axis_chdr_tready (ep5_to_xb_tready ),
+    .s_axis_data_tdata  ({s_ep5_in0_tdata}),
+    .s_axis_data_tlast  ({s_ep5_in0_tlast}),
+    .s_axis_data_tvalid ({s_ep5_in0_tvalid}),
+    .s_axis_data_tready ({s_ep5_in0_tready}),
+    .m_axis_data_tdata  ({m_ep5_out0_tdata}),
+    .m_axis_data_tlast  ({m_ep5_out0_tlast}),
+    .m_axis_data_tvalid ({m_ep5_out0_tvalid}),
+    .m_axis_data_tready ({m_ep5_out0_tready}),
+    .s_axis_ctrl_tdata  (s_ep5_ctrl_tdata ),
+    .s_axis_ctrl_tlast  (s_ep5_ctrl_tlast ),
+    .s_axis_ctrl_tvalid (s_ep5_ctrl_tvalid),
+    .s_axis_ctrl_tready (s_ep5_ctrl_tready),
+    .m_axis_ctrl_tdata  (m_ep5_ctrl_tdata ),
+    .m_axis_ctrl_tlast  (m_ep5_ctrl_tlast ),
+    .m_axis_ctrl_tvalid (m_ep5_ctrl_tvalid),
+    .m_axis_ctrl_tready (m_ep5_ctrl_tready),
+    .strm_seq_err_stb   (                  ),
+    .strm_data_err_stb  (                  ),
+    .strm_route_err_stb (                  ),
+    .signal_data_err    (1'b0              )
+  );
+
+  wire [CHDR_W-1:0] m_ep6_out0_tdata;
+  wire              m_ep6_out0_tlast;
+  wire              m_ep6_out0_tvalid;
+  wire              m_ep6_out0_tready;
+  wire [CHDR_W-1:0] s_ep6_in0_tdata;
+  wire              s_ep6_in0_tlast;
+  wire              s_ep6_in0_tvalid;
+  wire              s_ep6_in0_tready;
+  wire [31:0]       m_ep6_ctrl_tdata , s_ep6_ctrl_tdata ;
+  wire              m_ep6_ctrl_tlast , s_ep6_ctrl_tlast ;
+  wire              m_ep6_ctrl_tvalid, s_ep6_ctrl_tvalid;
+  wire              m_ep6_ctrl_tready, s_ep6_ctrl_tready;
+
+  chdr_stream_endpoint #(
+    .PROTOVER           (PROTOVER),
+    .CHDR_W             (CHDR_W),
+    .AXIS_CTRL_EN       (0),
+    .AXIS_DATA_EN       (1),
+    .NUM_DATA_I         (1),
+    .NUM_DATA_O         (1),
+    .INST_NUM           (6),
+    .CTRL_XBAR_PORT     (7),
+    .INGRESS_BUFF_SIZE  (12),
+    .MTU                (MTU),
+    .REPORT_STRM_ERRS   (1)
+  ) ep6_i (
+    .rfnoc_chdr_clk     (rfnoc_chdr_clk    ),
+    .rfnoc_chdr_rst     (rfnoc_chdr_rst    ),
+    .rfnoc_ctrl_clk     (rfnoc_ctrl_clk    ),
+    .rfnoc_ctrl_rst     (rfnoc_ctrl_rst    ),
+    .device_id          (device_id         ),
+    .s_axis_chdr_tdata  (xb_to_ep6_tdata  ),
+    .s_axis_chdr_tlast  (xb_to_ep6_tlast  ),
+    .s_axis_chdr_tvalid (xb_to_ep6_tvalid ),
+    .s_axis_chdr_tready (xb_to_ep6_tready ),
+    .m_axis_chdr_tdata  (ep6_to_xb_tdata  ),
+    .m_axis_chdr_tlast  (ep6_to_xb_tlast  ),
+    .m_axis_chdr_tvalid (ep6_to_xb_tvalid ),
+    .m_axis_chdr_tready (ep6_to_xb_tready ),
+    .s_axis_data_tdata  ({s_ep6_in0_tdata}),
+    .s_axis_data_tlast  ({s_ep6_in0_tlast}),
+    .s_axis_data_tvalid ({s_ep6_in0_tvalid}),
+    .s_axis_data_tready ({s_ep6_in0_tready}),
+    .m_axis_data_tdata  ({m_ep6_out0_tdata}),
+    .m_axis_data_tlast  ({m_ep6_out0_tlast}),
+    .m_axis_data_tvalid ({m_ep6_out0_tvalid}),
+    .m_axis_data_tready ({m_ep6_out0_tready}),
+    .s_axis_ctrl_tdata  (s_ep6_ctrl_tdata ),
+    .s_axis_ctrl_tlast  (s_ep6_ctrl_tlast ),
+    .s_axis_ctrl_tvalid (s_ep6_ctrl_tvalid),
+    .s_axis_ctrl_tready (s_ep6_ctrl_tready),
+    .m_axis_ctrl_tdata  (m_ep6_ctrl_tdata ),
+    .m_axis_ctrl_tlast  (m_ep6_ctrl_tlast ),
+    .m_axis_ctrl_tvalid (m_ep6_ctrl_tvalid),
+    .m_axis_ctrl_tready (m_ep6_ctrl_tready),
+    .strm_seq_err_stb   (                  ),
+    .strm_data_err_stb  (                  ),
+    .strm_route_err_stb (                  ),
+    .signal_data_err    (1'b0              )
+  );
+
+  wire [CHDR_W-1:0] m_ep7_out0_tdata;
+  wire              m_ep7_out0_tlast;
+  wire              m_ep7_out0_tvalid;
+  wire              m_ep7_out0_tready;
+  wire [CHDR_W-1:0] s_ep7_in0_tdata;
+  wire              s_ep7_in0_tlast;
+  wire              s_ep7_in0_tvalid;
+  wire              s_ep7_in0_tready;
+  wire [31:0]       m_ep7_ctrl_tdata , s_ep7_ctrl_tdata ;
+  wire              m_ep7_ctrl_tlast , s_ep7_ctrl_tlast ;
+  wire              m_ep7_ctrl_tvalid, s_ep7_ctrl_tvalid;
+  wire              m_ep7_ctrl_tready, s_ep7_ctrl_tready;
+
+  chdr_stream_endpoint #(
+    .PROTOVER           (PROTOVER),
+    .CHDR_W             (CHDR_W),
+    .AXIS_CTRL_EN       (0),
+    .AXIS_DATA_EN       (1),
+    .NUM_DATA_I         (1),
+    .NUM_DATA_O         (1),
+    .INST_NUM           (7),
+    .CTRL_XBAR_PORT     (8),
+    .INGRESS_BUFF_SIZE  (12),
+    .MTU                (MTU),
+    .REPORT_STRM_ERRS   (1)
+  ) ep7_i (
+    .rfnoc_chdr_clk     (rfnoc_chdr_clk    ),
+    .rfnoc_chdr_rst     (rfnoc_chdr_rst    ),
+    .rfnoc_ctrl_clk     (rfnoc_ctrl_clk    ),
+    .rfnoc_ctrl_rst     (rfnoc_ctrl_rst    ),
+    .device_id          (device_id         ),
+    .s_axis_chdr_tdata  (xb_to_ep7_tdata  ),
+    .s_axis_chdr_tlast  (xb_to_ep7_tlast  ),
+    .s_axis_chdr_tvalid (xb_to_ep7_tvalid ),
+    .s_axis_chdr_tready (xb_to_ep7_tready ),
+    .m_axis_chdr_tdata  (ep7_to_xb_tdata  ),
+    .m_axis_chdr_tlast  (ep7_to_xb_tlast  ),
+    .m_axis_chdr_tvalid (ep7_to_xb_tvalid ),
+    .m_axis_chdr_tready (ep7_to_xb_tready ),
+    .s_axis_data_tdata  ({s_ep7_in0_tdata}),
+    .s_axis_data_tlast  ({s_ep7_in0_tlast}),
+    .s_axis_data_tvalid ({s_ep7_in0_tvalid}),
+    .s_axis_data_tready ({s_ep7_in0_tready}),
+    .m_axis_data_tdata  ({m_ep7_out0_tdata}),
+    .m_axis_data_tlast  ({m_ep7_out0_tlast}),
+    .m_axis_data_tvalid ({m_ep7_out0_tvalid}),
+    .m_axis_data_tready ({m_ep7_out0_tready}),
+    .s_axis_ctrl_tdata  (s_ep7_ctrl_tdata ),
+    .s_axis_ctrl_tlast  (s_ep7_ctrl_tlast ),
+    .s_axis_ctrl_tvalid (s_ep7_ctrl_tvalid),
+    .s_axis_ctrl_tready (s_ep7_ctrl_tready),
+    .m_axis_ctrl_tdata  (m_ep7_ctrl_tdata ),
+    .m_axis_ctrl_tlast  (m_ep7_ctrl_tlast ),
+    .m_axis_ctrl_tvalid (m_ep7_ctrl_tvalid),
+    .m_axis_ctrl_tready (m_ep7_ctrl_tready),
+    .strm_seq_err_stb   (                  ),
+    .strm_data_err_stb  (                  ),
+    .strm_route_err_stb (                  ),
+    .signal_data_err    (1'b0              )
+  );
+
 
 
   // ----------------------------------------------------
@@ -490,10 +766,14 @@ module rfnoc_image_core #(
   wire              m_radio1_ctrl_tlast ,   s_radio1_ctrl_tlast ;
   wire              m_radio1_ctrl_tvalid,   s_radio1_ctrl_tvalid;
   wire              m_radio1_ctrl_tready,   s_radio1_ctrl_tready;
+  wire [31:0]       m_replay0_ctrl_tdata ,   s_replay0_ctrl_tdata ;
+  wire              m_replay0_ctrl_tlast ,   s_replay0_ctrl_tlast ;
+  wire              m_replay0_ctrl_tvalid,   s_replay0_ctrl_tvalid;
+  wire              m_replay0_ctrl_tready,   s_replay0_ctrl_tready;
 
   axis_ctrl_crossbar_nxn #(
     .WIDTH            (32),
-    .NPORTS           (8),
+    .NPORTS           (9),
     .TOPOLOGY         ("TORUS"),
     .INGRESS_BUFF_SIZE(5),
     .ROUTER_BUFF_SIZE (5),
@@ -502,32 +782,32 @@ module rfnoc_image_core #(
   ) ctrl_xb_i (
     .clk              (rfnoc_ctrl_clk),
     .reset            (rfnoc_ctrl_rst),
-    .s_axis_tdata     ({m_radio1_ctrl_tdata , m_ddc1_ctrl_tdata , m_duc1_ctrl_tdata , m_radio0_ctrl_tdata , m_ddc0_ctrl_tdata , m_duc0_ctrl_tdata , m_ep0_ctrl_tdata , m_core_ctrl_tdata }),
-    .s_axis_tvalid    ({m_radio1_ctrl_tvalid, m_ddc1_ctrl_tvalid, m_duc1_ctrl_tvalid, m_radio0_ctrl_tvalid, m_ddc0_ctrl_tvalid, m_duc0_ctrl_tvalid, m_ep0_ctrl_tvalid, m_core_ctrl_tvalid}),
-    .s_axis_tlast     ({m_radio1_ctrl_tlast , m_ddc1_ctrl_tlast , m_duc1_ctrl_tlast , m_radio0_ctrl_tlast , m_ddc0_ctrl_tlast , m_duc0_ctrl_tlast , m_ep0_ctrl_tlast , m_core_ctrl_tlast }),
-    .s_axis_tready    ({m_radio1_ctrl_tready, m_ddc1_ctrl_tready, m_duc1_ctrl_tready, m_radio0_ctrl_tready, m_ddc0_ctrl_tready, m_duc0_ctrl_tready, m_ep0_ctrl_tready, m_core_ctrl_tready}),
-    .m_axis_tdata     ({s_radio1_ctrl_tdata , s_ddc1_ctrl_tdata , s_duc1_ctrl_tdata , s_radio0_ctrl_tdata , s_ddc0_ctrl_tdata , s_duc0_ctrl_tdata , s_ep0_ctrl_tdata , s_core_ctrl_tdata }),
-    .m_axis_tvalid    ({s_radio1_ctrl_tvalid, s_ddc1_ctrl_tvalid, s_duc1_ctrl_tvalid, s_radio0_ctrl_tvalid, s_ddc0_ctrl_tvalid, s_duc0_ctrl_tvalid, s_ep0_ctrl_tvalid, s_core_ctrl_tvalid}),
-    .m_axis_tlast     ({s_radio1_ctrl_tlast , s_ddc1_ctrl_tlast , s_duc1_ctrl_tlast , s_radio0_ctrl_tlast , s_ddc0_ctrl_tlast , s_duc0_ctrl_tlast , s_ep0_ctrl_tlast , s_core_ctrl_tlast }),
-    .m_axis_tready    ({s_radio1_ctrl_tready, s_ddc1_ctrl_tready, s_duc1_ctrl_tready, s_radio0_ctrl_tready, s_ddc0_ctrl_tready, s_duc0_ctrl_tready, s_ep0_ctrl_tready, s_core_ctrl_tready}),
+    .s_axis_tdata     ({m_replay0_ctrl_tdata , m_radio1_ctrl_tdata , m_ddc1_ctrl_tdata , m_duc1_ctrl_tdata , m_radio0_ctrl_tdata , m_ddc0_ctrl_tdata , m_duc0_ctrl_tdata , m_ep0_ctrl_tdata , m_core_ctrl_tdata }),
+    .s_axis_tvalid    ({m_replay0_ctrl_tvalid, m_radio1_ctrl_tvalid, m_ddc1_ctrl_tvalid, m_duc1_ctrl_tvalid, m_radio0_ctrl_tvalid, m_ddc0_ctrl_tvalid, m_duc0_ctrl_tvalid, m_ep0_ctrl_tvalid, m_core_ctrl_tvalid}),
+    .s_axis_tlast     ({m_replay0_ctrl_tlast , m_radio1_ctrl_tlast , m_ddc1_ctrl_tlast , m_duc1_ctrl_tlast , m_radio0_ctrl_tlast , m_ddc0_ctrl_tlast , m_duc0_ctrl_tlast , m_ep0_ctrl_tlast , m_core_ctrl_tlast }),
+    .s_axis_tready    ({m_replay0_ctrl_tready, m_radio1_ctrl_tready, m_ddc1_ctrl_tready, m_duc1_ctrl_tready, m_radio0_ctrl_tready, m_ddc0_ctrl_tready, m_duc0_ctrl_tready, m_ep0_ctrl_tready, m_core_ctrl_tready}),
+    .m_axis_tdata     ({s_replay0_ctrl_tdata , s_radio1_ctrl_tdata , s_ddc1_ctrl_tdata , s_duc1_ctrl_tdata , s_radio0_ctrl_tdata , s_ddc0_ctrl_tdata , s_duc0_ctrl_tdata , s_ep0_ctrl_tdata , s_core_ctrl_tdata }),
+    .m_axis_tvalid    ({s_replay0_ctrl_tvalid, s_radio1_ctrl_tvalid, s_ddc1_ctrl_tvalid, s_duc1_ctrl_tvalid, s_radio0_ctrl_tvalid, s_ddc0_ctrl_tvalid, s_duc0_ctrl_tvalid, s_ep0_ctrl_tvalid, s_core_ctrl_tvalid}),
+    .m_axis_tlast     ({s_replay0_ctrl_tlast , s_radio1_ctrl_tlast , s_ddc1_ctrl_tlast , s_duc1_ctrl_tlast , s_radio0_ctrl_tlast , s_ddc0_ctrl_tlast , s_duc0_ctrl_tlast , s_ep0_ctrl_tlast , s_core_ctrl_tlast }),
+    .m_axis_tready    ({s_replay0_ctrl_tready, s_radio1_ctrl_tready, s_ddc1_ctrl_tready, s_duc1_ctrl_tready, s_radio0_ctrl_tready, s_ddc0_ctrl_tready, s_duc0_ctrl_tready, s_ep0_ctrl_tready, s_core_ctrl_tready}),
     .deadlock_detected()
   );
 
   // ----------------------------------------------------
   // RFNoC Core Kernel
   // ----------------------------------------------------
-  wire [(512*6)-1:0] rfnoc_core_config, rfnoc_core_status;
+  wire [(512*7)-1:0] rfnoc_core_config, rfnoc_core_status;
 
   rfnoc_core_kernel #(
     .PROTOVER            (PROTOVER),
     .DEVICE_TYPE         (16'h1300),
     .DEVICE_FAMILY       ("7SERIES"),
     .SAFE_START_CLKS     (0),
-    .NUM_BLOCKS          (6),
-    .NUM_STREAM_ENDPOINTS(4),
+    .NUM_BLOCKS          (7),
+    .NUM_STREAM_ENDPOINTS(8),
     .NUM_ENDPOINTS_CTRL  (1),
     .NUM_TRANSPORTS      (3),
-    .NUM_EDGES           (16),
+    .NUM_EDGES           (24),
     .CHDR_XBAR_PRESENT   (1),
     .EDGE_TBL_FILE       (EDGE_TBL_FILE)
   ) core_kernel_i (
@@ -916,6 +1196,145 @@ module rfnoc_image_core #(
 
 
   // ----------------------------------------------------
+  // replay0
+  // ----------------------------------------------------
+  wire              replay0_mem_clk;
+  wire [CHDR_W-1:0] s_replay0_in_3_tdata , s_replay0_in_2_tdata , s_replay0_in_1_tdata , s_replay0_in_0_tdata ;
+  wire              s_replay0_in_3_tlast , s_replay0_in_2_tlast , s_replay0_in_1_tlast , s_replay0_in_0_tlast ;
+  wire              s_replay0_in_3_tvalid, s_replay0_in_2_tvalid, s_replay0_in_1_tvalid, s_replay0_in_0_tvalid;
+  wire              s_replay0_in_3_tready, s_replay0_in_2_tready, s_replay0_in_1_tready, s_replay0_in_0_tready;
+  wire [CHDR_W-1:0] m_replay0_out_3_tdata , m_replay0_out_2_tdata , m_replay0_out_1_tdata , m_replay0_out_0_tdata ;
+  wire              m_replay0_out_3_tlast , m_replay0_out_2_tlast , m_replay0_out_1_tlast , m_replay0_out_0_tlast ;
+  wire              m_replay0_out_3_tvalid, m_replay0_out_2_tvalid, m_replay0_out_1_tvalid, m_replay0_out_0_tvalid;
+  wire              m_replay0_out_3_tready, m_replay0_out_2_tready, m_replay0_out_1_tready, m_replay0_out_0_tready;
+
+  //  axi_ram
+  wire [  1-1:0] replay0_axi_rst;
+  wire [  4-1:0] replay0_m_axi_awid;
+  wire [128-1:0] replay0_m_axi_awaddr;
+  wire [ 32-1:0] replay0_m_axi_awlen;
+  wire [ 12-1:0] replay0_m_axi_awsize;
+  wire [  8-1:0] replay0_m_axi_awburst;
+  wire [  4-1:0] replay0_m_axi_awlock;
+  wire [ 16-1:0] replay0_m_axi_awcache;
+  wire [ 12-1:0] replay0_m_axi_awprot;
+  wire [ 16-1:0] replay0_m_axi_awqos;
+  wire [ 16-1:0] replay0_m_axi_awregion;
+  wire [  4-1:0] replay0_m_axi_awuser;
+  wire [  4-1:0] replay0_m_axi_awvalid;
+  wire [  4-1:0] replay0_m_axi_awready;
+  wire [256-1:0] replay0_m_axi_wdata;
+  wire [ 32-1:0] replay0_m_axi_wstrb;
+  wire [  4-1:0] replay0_m_axi_wlast;
+  wire [  4-1:0] replay0_m_axi_wuser;
+  wire [  4-1:0] replay0_m_axi_wvalid;
+  wire [  4-1:0] replay0_m_axi_wready;
+  wire [  4-1:0] replay0_m_axi_bid;
+  wire [  8-1:0] replay0_m_axi_bresp;
+  wire [  4-1:0] replay0_m_axi_buser;
+  wire [  4-1:0] replay0_m_axi_bvalid;
+  wire [  4-1:0] replay0_m_axi_bready;
+  wire [  4-1:0] replay0_m_axi_arid;
+  wire [128-1:0] replay0_m_axi_araddr;
+  wire [ 32-1:0] replay0_m_axi_arlen;
+  wire [ 12-1:0] replay0_m_axi_arsize;
+  wire [  8-1:0] replay0_m_axi_arburst;
+  wire [  4-1:0] replay0_m_axi_arlock;
+  wire [ 16-1:0] replay0_m_axi_arcache;
+  wire [ 12-1:0] replay0_m_axi_arprot;
+  wire [ 16-1:0] replay0_m_axi_arqos;
+  wire [ 16-1:0] replay0_m_axi_arregion;
+  wire [  4-1:0] replay0_m_axi_aruser;
+  wire [  4-1:0] replay0_m_axi_arvalid;
+  wire [  4-1:0] replay0_m_axi_arready;
+  wire [  4-1:0] replay0_m_axi_rid;
+  wire [256-1:0] replay0_m_axi_rdata;
+  wire [  8-1:0] replay0_m_axi_rresp;
+  wire [  4-1:0] replay0_m_axi_rlast;
+  wire [  4-1:0] replay0_m_axi_ruser;
+  wire [  4-1:0] replay0_m_axi_rvalid;
+  wire [  4-1:0] replay0_m_axi_rready;
+
+  rfnoc_block_replay #(
+    .THIS_PORTID(8),
+    .CHDR_W(CHDR_W),
+    .NUM_PORTS(4),
+    .MEM_ADDR_W(31),
+    .MEM_DATA_W(64),
+    .MTU(MTU)
+  ) b_replay0_6 (
+    .rfnoc_chdr_clk     (rfnoc_chdr_clk),
+    .rfnoc_ctrl_clk     (rfnoc_ctrl_clk),
+    .mem_clk(replay0_mem_clk),
+    .rfnoc_core_config  (rfnoc_core_config[512*7-1:512*6]),
+    .rfnoc_core_status  (rfnoc_core_status[512*7-1:512*6]),
+
+    .axi_rst(replay0_axi_rst),
+    .m_axi_awid(replay0_m_axi_awid),
+    .m_axi_awaddr(replay0_m_axi_awaddr),
+    .m_axi_awlen(replay0_m_axi_awlen),
+    .m_axi_awsize(replay0_m_axi_awsize),
+    .m_axi_awburst(replay0_m_axi_awburst),
+    .m_axi_awlock(replay0_m_axi_awlock),
+    .m_axi_awcache(replay0_m_axi_awcache),
+    .m_axi_awprot(replay0_m_axi_awprot),
+    .m_axi_awqos(replay0_m_axi_awqos),
+    .m_axi_awregion(replay0_m_axi_awregion),
+    .m_axi_awuser(replay0_m_axi_awuser),
+    .m_axi_awvalid(replay0_m_axi_awvalid),
+    .m_axi_awready(replay0_m_axi_awready),
+    .m_axi_wdata(replay0_m_axi_wdata),
+    .m_axi_wstrb(replay0_m_axi_wstrb),
+    .m_axi_wlast(replay0_m_axi_wlast),
+    .m_axi_wuser(replay0_m_axi_wuser),
+    .m_axi_wvalid(replay0_m_axi_wvalid),
+    .m_axi_wready(replay0_m_axi_wready),
+    .m_axi_bid(replay0_m_axi_bid),
+    .m_axi_bresp(replay0_m_axi_bresp),
+    .m_axi_buser(replay0_m_axi_buser),
+    .m_axi_bvalid(replay0_m_axi_bvalid),
+    .m_axi_bready(replay0_m_axi_bready),
+    .m_axi_arid(replay0_m_axi_arid),
+    .m_axi_araddr(replay0_m_axi_araddr),
+    .m_axi_arlen(replay0_m_axi_arlen),
+    .m_axi_arsize(replay0_m_axi_arsize),
+    .m_axi_arburst(replay0_m_axi_arburst),
+    .m_axi_arlock(replay0_m_axi_arlock),
+    .m_axi_arcache(replay0_m_axi_arcache),
+    .m_axi_arprot(replay0_m_axi_arprot),
+    .m_axi_arqos(replay0_m_axi_arqos),
+    .m_axi_arregion(replay0_m_axi_arregion),
+    .m_axi_aruser(replay0_m_axi_aruser),
+    .m_axi_arvalid(replay0_m_axi_arvalid),
+    .m_axi_arready(replay0_m_axi_arready),
+    .m_axi_rid(replay0_m_axi_rid),
+    .m_axi_rdata(replay0_m_axi_rdata),
+    .m_axi_rresp(replay0_m_axi_rresp),
+    .m_axi_rlast(replay0_m_axi_rlast),
+    .m_axi_ruser(replay0_m_axi_ruser),
+    .m_axi_rvalid(replay0_m_axi_rvalid),
+    .m_axi_rready(replay0_m_axi_rready),
+
+    .s_rfnoc_chdr_tdata ({s_replay0_in_3_tdata , s_replay0_in_2_tdata , s_replay0_in_1_tdata , s_replay0_in_0_tdata }),
+    .s_rfnoc_chdr_tlast ({s_replay0_in_3_tlast , s_replay0_in_2_tlast , s_replay0_in_1_tlast , s_replay0_in_0_tlast }),
+    .s_rfnoc_chdr_tvalid({s_replay0_in_3_tvalid, s_replay0_in_2_tvalid, s_replay0_in_1_tvalid, s_replay0_in_0_tvalid}),
+    .s_rfnoc_chdr_tready({s_replay0_in_3_tready, s_replay0_in_2_tready, s_replay0_in_1_tready, s_replay0_in_0_tready}),
+    .m_rfnoc_chdr_tdata ({m_replay0_out_3_tdata , m_replay0_out_2_tdata , m_replay0_out_1_tdata , m_replay0_out_0_tdata }),
+    .m_rfnoc_chdr_tlast ({m_replay0_out_3_tlast , m_replay0_out_2_tlast , m_replay0_out_1_tlast , m_replay0_out_0_tlast }),
+    .m_rfnoc_chdr_tvalid({m_replay0_out_3_tvalid, m_replay0_out_2_tvalid, m_replay0_out_1_tvalid, m_replay0_out_0_tvalid}),
+    .m_rfnoc_chdr_tready({m_replay0_out_3_tready, m_replay0_out_2_tready, m_replay0_out_1_tready, m_replay0_out_0_tready}),
+    .s_rfnoc_ctrl_tdata (s_replay0_ctrl_tdata ),
+    .s_rfnoc_ctrl_tlast (s_replay0_ctrl_tlast ),
+    .s_rfnoc_ctrl_tvalid(s_replay0_ctrl_tvalid),
+    .s_rfnoc_ctrl_tready(s_replay0_ctrl_tready),
+    .m_rfnoc_ctrl_tdata (m_replay0_ctrl_tdata ),
+    .m_rfnoc_ctrl_tlast (m_replay0_ctrl_tlast ),
+    .m_rfnoc_ctrl_tvalid(m_replay0_ctrl_tvalid),
+    .m_rfnoc_ctrl_tready(m_replay0_ctrl_tready)
+  );
+
+
+  // ----------------------------------------------------
   // Static Router
   // ----------------------------------------------------
   assign s_duc0_in_0_tdata = m_ep0_out0_tdata ;
@@ -998,6 +1417,46 @@ module rfnoc_image_core #(
   assign s_ep3_in0_tvalid = m_ddc1_out_1_tvalid;
   assign m_ddc1_out_1_tready = s_ep3_in0_tready;
 
+  assign s_replay0_in_0_tdata = m_ep4_out0_tdata ;
+  assign s_replay0_in_0_tlast = m_ep4_out0_tlast ;
+  assign s_replay0_in_0_tvalid = m_ep4_out0_tvalid;
+  assign m_ep4_out0_tready = s_replay0_in_0_tready;
+
+  assign s_ep4_in0_tdata = m_replay0_out_0_tdata ;
+  assign s_ep4_in0_tlast = m_replay0_out_0_tlast ;
+  assign s_ep4_in0_tvalid = m_replay0_out_0_tvalid;
+  assign m_replay0_out_0_tready = s_ep4_in0_tready;
+
+  assign s_replay0_in_1_tdata = m_ep5_out0_tdata ;
+  assign s_replay0_in_1_tlast = m_ep5_out0_tlast ;
+  assign s_replay0_in_1_tvalid = m_ep5_out0_tvalid;
+  assign m_ep5_out0_tready = s_replay0_in_1_tready;
+
+  assign s_ep5_in0_tdata = m_replay0_out_1_tdata ;
+  assign s_ep5_in0_tlast = m_replay0_out_1_tlast ;
+  assign s_ep5_in0_tvalid = m_replay0_out_1_tvalid;
+  assign m_replay0_out_1_tready = s_ep5_in0_tready;
+
+  assign s_replay0_in_2_tdata = m_ep6_out0_tdata ;
+  assign s_replay0_in_2_tlast = m_ep6_out0_tlast ;
+  assign s_replay0_in_2_tvalid = m_ep6_out0_tvalid;
+  assign m_ep6_out0_tready = s_replay0_in_2_tready;
+
+  assign s_ep6_in0_tdata = m_replay0_out_2_tdata ;
+  assign s_ep6_in0_tlast = m_replay0_out_2_tlast ;
+  assign s_ep6_in0_tvalid = m_replay0_out_2_tvalid;
+  assign m_replay0_out_2_tready = s_ep6_in0_tready;
+
+  assign s_replay0_in_3_tdata = m_ep7_out0_tdata ;
+  assign s_replay0_in_3_tlast = m_ep7_out0_tlast ;
+  assign s_replay0_in_3_tvalid = m_ep7_out0_tvalid;
+  assign m_ep7_out0_tready = s_replay0_in_3_tready;
+
+  assign s_ep7_in0_tdata = m_replay0_out_3_tdata ;
+  assign s_ep7_in0_tlast = m_replay0_out_3_tlast ;
+  assign s_ep7_in0_tvalid = m_replay0_out_3_tvalid;
+  assign m_replay0_out_3_tready = s_ep7_in0_tready;
+
 
   // ----------------------------------------------------
   // Unused Ports
@@ -1012,6 +1471,7 @@ module rfnoc_image_core #(
   assign radio1_radio_clk = radio_clk;
   assign ddc1_ce_clk = rfnoc_chdr_clk;
   assign duc1_ce_clk = rfnoc_chdr_clk;
+  assign replay0_mem_clk = dram_clk;
 
 
   // ----------------------------------------------------
@@ -1040,6 +1500,52 @@ module rfnoc_image_core #(
   assign radio1_m_ctrlport_resp_status = m_ctrlport_radio1_resp_status;
   assign radio1_m_ctrlport_resp_data = m_ctrlport_radio1_resp_data;
 
+  assign replay0_axi_rst = axi_rst;
+  assign m_axi_awid = replay0_m_axi_awid;
+  assign m_axi_awaddr = replay0_m_axi_awaddr;
+  assign m_axi_awlen = replay0_m_axi_awlen;
+  assign m_axi_awsize = replay0_m_axi_awsize;
+  assign m_axi_awburst = replay0_m_axi_awburst;
+  assign m_axi_awlock = replay0_m_axi_awlock;
+  assign m_axi_awcache = replay0_m_axi_awcache;
+  assign m_axi_awprot = replay0_m_axi_awprot;
+  assign m_axi_awqos = replay0_m_axi_awqos;
+  assign m_axi_awregion = replay0_m_axi_awregion;
+  assign m_axi_awuser = replay0_m_axi_awuser;
+  assign m_axi_awvalid = replay0_m_axi_awvalid;
+  assign replay0_m_axi_awready = m_axi_awready;
+  assign m_axi_wdata = replay0_m_axi_wdata;
+  assign m_axi_wstrb = replay0_m_axi_wstrb;
+  assign m_axi_wlast = replay0_m_axi_wlast;
+  assign m_axi_wuser = replay0_m_axi_wuser;
+  assign m_axi_wvalid = replay0_m_axi_wvalid;
+  assign replay0_m_axi_wready = m_axi_wready;
+  assign replay0_m_axi_bid = m_axi_bid;
+  assign replay0_m_axi_bresp = m_axi_bresp;
+  assign replay0_m_axi_buser = m_axi_buser;
+  assign replay0_m_axi_bvalid = m_axi_bvalid;
+  assign m_axi_bready = replay0_m_axi_bready;
+  assign m_axi_arid = replay0_m_axi_arid;
+  assign m_axi_araddr = replay0_m_axi_araddr;
+  assign m_axi_arlen = replay0_m_axi_arlen;
+  assign m_axi_arsize = replay0_m_axi_arsize;
+  assign m_axi_arburst = replay0_m_axi_arburst;
+  assign m_axi_arlock = replay0_m_axi_arlock;
+  assign m_axi_arcache = replay0_m_axi_arcache;
+  assign m_axi_arprot = replay0_m_axi_arprot;
+  assign m_axi_arqos = replay0_m_axi_arqos;
+  assign m_axi_arregion = replay0_m_axi_arregion;
+  assign m_axi_aruser = replay0_m_axi_aruser;
+  assign m_axi_arvalid = replay0_m_axi_arvalid;
+  assign replay0_m_axi_arready = m_axi_arready;
+  assign replay0_m_axi_rid = m_axi_rid;
+  assign replay0_m_axi_rdata = m_axi_rdata;
+  assign replay0_m_axi_rresp = m_axi_rresp;
+  assign replay0_m_axi_rlast = m_axi_rlast;
+  assign replay0_m_axi_ruser = m_axi_ruser;
+  assign replay0_m_axi_rvalid = m_axi_rvalid;
+  assign m_axi_rready = replay0_m_axi_rready;
+
   assign radio0_radio_rx_data = radio_rx_data_radio0;
   assign radio0_radio_rx_stb = radio_rx_stb_radio0;
   assign radio_rx_running_radio0 = radio0_radio_rx_running;
diff --git a/fpga/usrp3/top/n3xx/n310_rfnoc_image_core.yml b/fpga/usrp3/top/n3xx/n310_rfnoc_image_core.yml
index d930baf6f..abef58afc 100644
--- a/fpga/usrp3/top/n3xx/n310_rfnoc_image_core.yml
+++ b/fpga/usrp3/top/n3xx/n310_rfnoc_image_core.yml
@@ -28,6 +28,22 @@ stream_endpoints:
     ctrl: False                     # Endpoint passes control traffic
     data: True                      # Endpoint passes data traffic
     buff_size: 32768                # Ingress buffer size for data
+  ep4:                       # Stream endpoint name
+    ctrl: False                     # Endpoint passes control traffic
+    data: True                      # Endpoint passes data traffic
+    buff_size: 4096                 # Ingress buffer size for data
+  ep5:                       # Stream endpoint name
+    ctrl: False                     # Endpoint passes control traffic
+    data: True                      # Endpoint passes data traffic
+    buff_size: 4096                 # Ingress buffer size for data
+  ep6:                       # Stream endpoint name
+    ctrl: False                     # Endpoint passes control traffic
+    data: True                      # Endpoint passes data traffic
+    buff_size: 4096                 # Ingress buffer size for data
+  ep7:                       # Stream endpoint name
+    ctrl: False                     # Endpoint passes control traffic
+    data: True                      # Endpoint passes data traffic
+    buff_size: 4096                 # Ingress buffer size for data
 
 # A list of all NoC blocks in design
 # ----------------------------------
@@ -52,16 +68,11 @@ noc_blocks:
       NUM_PORTS: 2
   radio1:
     block_desc: 'radio_2x64.yml'
-  #fifo0:
-    #block_desc: 'axi_ram_fifo_4x64.yml'
-    #parameters:
-      ## These parameters match the memory interface on the N3XX
-      #NUM_PORTS: 4
-      #MEM_DATA_W: 64
-      #MEM_ADDR_W: 31
-      #FIFO_ADDR_BASE: "{30'h06000000, 30'h04000000, 30'h02000000, 30'h00000000}"
-      #FIFO_ADDR_MASK: "{30'h01FFFFFF, 30'h01FFFFFF, 30'h01FFFFFF, 30'h01FFFFFF}"
-      #MEM_CLK_RATE: "303819444" # 166.666666 MHz * 21.875 / 4 / 3 = 303.819444 MHz
+  replay0:
+    block_desc: 'replay.yml'
+    parameters:
+      NUM_PORTS: 4
+      MEM_ADDR_W: 31
 
 # A list of all static connections in design
 # ------------------------------------------
@@ -87,8 +98,17 @@ connections:
   - { srcblk: duc1,   srcport: out_1, dstblk: radio1, dstport: in_1 }
   - { srcblk: radio1, srcport: out_1, dstblk: ddc1,   dstport: in_1 }
   - { srcblk: ddc1,   srcport: out_1, dstblk: ep3,    dstport: in0  }
+  - { srcblk: ep4,     srcport: out0,  dstblk: replay0, dstport: in_0 }
+  - { srcblk: replay0, srcport: out_0, dstblk: ep4,     dstport: in0  }
+  - { srcblk: ep5,     srcport: out0,  dstblk: replay0, dstport: in_1 }
+  - { srcblk: replay0, srcport: out_1, dstblk: ep5,     dstport: in0  }
+  - { srcblk: ep6,     srcport: out0,  dstblk: replay0, dstport: in_2 }
+  - { srcblk: replay0, srcport: out_2, dstblk: ep6,     dstport: in0  }
+  - { srcblk: ep7,     srcport: out0,  dstblk: replay0, dstport: in_3 }
+  - { srcblk: replay0, srcport: out_3, dstblk: ep7,     dstport: in0  }
   - { srcblk: radio0, srcport: ctrl_port, dstblk: _device_, dstport: ctrlport_radio0 }
   - { srcblk: radio1, srcport: ctrl_port, dstblk: _device_, dstport: ctrlport_radio1 }
+  - { srcblk: replay0, srcport: axi_ram, dstblk: _device_, dstport: dram }
   - { srcblk: _device_, srcport: x300_radio0, dstblk: radio0, dstport: x300_radio }
   - { srcblk: _device_, srcport: x300_radio1, dstblk: radio1, dstport: x300_radio }
   - { srcblk: _device_, srcport: time_keeper, dstblk: radio0, dstport: time_keeper }
@@ -108,4 +128,4 @@ clk_domains:
   - { srcblk: _device_, srcport: radio,      dstblk: radio1, dstport: radio }
   - { srcblk: _device_, srcport: rfnoc_chdr, dstblk: ddc1,   dstport: ce    }
   - { srcblk: _device_, srcport: rfnoc_chdr, dstblk: duc1,   dstport: ce    }
-# - { srcblk: _device_, srcport: dram,       dstblk: fifo0,  dstport: mem   }
+  - { srcblk: _device_, srcport: dram,  dstblk: replay0, dstport: mem  }
diff --git a/fpga/usrp3/top/n3xx/n310_static_router.hex b/fpga/usrp3/top/n3xx/n310_static_router.hex
index 73449b968..99d1452cd 100644
--- a/fpga/usrp3/top/n3xx/n310_static_router.hex
+++ b/fpga/usrp3/top/n3xx/n310_static_router.hex
@@ -1,17 +1,25 @@
-00000010
-00400140
-014001c0
-01c00180
-01800040
-00800141
-014101c1
-01c10181
-01810080
-00c00200
-02000280
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diff --git a/fpga/usrp3/top/n3xx/n320_rfnoc_image_core.v b/fpga/usrp3/top/n3xx/n320_rfnoc_image_core.v
index 40c76d629..6196836eb 100644
--- a/fpga/usrp3/top/n3xx/n320_rfnoc_image_core.v
+++ b/fpga/usrp3/top/n3xx/n320_rfnoc_image_core.v
@@ -7,9 +7,9 @@
 // Module: rfnoc_image_core (for n320)
 // This file was autogenerated by UHD's image builder tool (rfnoc_image_builder)
 // Re-running that tool will overwrite this file!
-// File generated on: 2020-08-10T16:16:40.486292
+// File generated on: 2020-09-02T12:03:04.264797
 // Source: ./n320_rfnoc_image_core.yml
-// Source SHA256: dd1cf12171ae4b9c0e66dca548a881337bb27815a1ed9c18cd151459939de6bf
+// Source SHA256: a059eb9043ce1c034abc0a0db7daad88a5e584207994c53030a98b3bea1bce39
 
 module rfnoc_image_core #(
   parameter [15:0] PROTOVER = {8'd1, 8'd0}
@@ -162,10 +162,26 @@ module rfnoc_image_core #(
   wire              ep1_to_xb_tlast ;
   wire              ep1_to_xb_tvalid;
   wire              ep1_to_xb_tready;
+  wire [CHDR_W-1:0] xb_to_ep2_tdata ;
+  wire              xb_to_ep2_tlast ;
+  wire              xb_to_ep2_tvalid;
+  wire              xb_to_ep2_tready;
+  wire [CHDR_W-1:0] ep2_to_xb_tdata ;
+  wire              ep2_to_xb_tlast ;
+  wire              ep2_to_xb_tvalid;
+  wire              ep2_to_xb_tready;
+  wire [CHDR_W-1:0] xb_to_ep3_tdata ;
+  wire              xb_to_ep3_tlast ;
+  wire              xb_to_ep3_tvalid;
+  wire              xb_to_ep3_tready;
+  wire [CHDR_W-1:0] ep3_to_xb_tdata ;
+  wire              ep3_to_xb_tlast ;
+  wire              ep3_to_xb_tvalid;
+  wire              ep3_to_xb_tready;
 
   chdr_crossbar_nxn #(
     .CHDR_W         (CHDR_W),
-    .NPORTS         (5),
+    .NPORTS         (7),
     .DEFAULT_PORT   (0),
     .MTU            (MTU),
     .ROUTE_TBL_SIZE (6),
@@ -178,14 +194,14 @@ module rfnoc_image_core #(
     .clk            (rfnoc_chdr_clk),
     .reset          (rfnoc_chdr_rst),
     .device_id      (device_id),
-    .s_axis_tdata   ({ep1_to_xb_tdata, ep0_to_xb_tdata, s_dma_tdata, s_eth1_tdata, s_eth0_tdata}),
-    .s_axis_tlast   ({ep1_to_xb_tlast, ep0_to_xb_tlast, s_dma_tlast, s_eth1_tlast, s_eth0_tlast}),
-    .s_axis_tvalid  ({ep1_to_xb_tvalid, ep0_to_xb_tvalid, s_dma_tvalid, s_eth1_tvalid, s_eth0_tvalid}),
-    .s_axis_tready  ({ep1_to_xb_tready, ep0_to_xb_tready, s_dma_tready, s_eth1_tready, s_eth0_tready}),
-    .m_axis_tdata   ({xb_to_ep1_tdata, xb_to_ep0_tdata, m_dma_tdata, m_eth1_tdata, m_eth0_tdata}),
-    .m_axis_tlast   ({xb_to_ep1_tlast, xb_to_ep0_tlast, m_dma_tlast, m_eth1_tlast, m_eth0_tlast}),
-    .m_axis_tvalid  ({xb_to_ep1_tvalid, xb_to_ep0_tvalid, m_dma_tvalid, m_eth1_tvalid, m_eth0_tvalid}),
-    .m_axis_tready  ({xb_to_ep1_tready, xb_to_ep0_tready, m_dma_tready, m_eth1_tready, m_eth0_tready}),
+    .s_axis_tdata   ({ep3_to_xb_tdata, ep2_to_xb_tdata, ep1_to_xb_tdata, ep0_to_xb_tdata, s_dma_tdata, s_eth1_tdata, s_eth0_tdata}),
+    .s_axis_tlast   ({ep3_to_xb_tlast, ep2_to_xb_tlast, ep1_to_xb_tlast, ep0_to_xb_tlast, s_dma_tlast, s_eth1_tlast, s_eth0_tlast}),
+    .s_axis_tvalid  ({ep3_to_xb_tvalid, ep2_to_xb_tvalid, ep1_to_xb_tvalid, ep0_to_xb_tvalid, s_dma_tvalid, s_eth1_tvalid, s_eth0_tvalid}),
+    .s_axis_tready  ({ep3_to_xb_tready, ep2_to_xb_tready, ep1_to_xb_tready, ep0_to_xb_tready, s_dma_tready, s_eth1_tready, s_eth0_tready}),
+    .m_axis_tdata   ({xb_to_ep3_tdata, xb_to_ep2_tdata, xb_to_ep1_tdata, xb_to_ep0_tdata, m_dma_tdata, m_eth1_tdata, m_eth0_tdata}),
+    .m_axis_tlast   ({xb_to_ep3_tlast, xb_to_ep2_tlast, xb_to_ep1_tlast, xb_to_ep0_tlast, m_dma_tlast, m_eth1_tlast, m_eth0_tlast}),
+    .m_axis_tvalid  ({xb_to_ep3_tvalid, xb_to_ep2_tvalid, xb_to_ep1_tvalid, xb_to_ep0_tvalid, m_dma_tvalid, m_eth1_tvalid, m_eth0_tvalid}),
+    .m_axis_tready  ({xb_to_ep3_tready, xb_to_ep2_tready, xb_to_ep1_tready, xb_to_ep0_tready, m_dma_tready, m_eth1_tready, m_eth0_tready}),
     .ext_rtcfg_stb  (1'h0),
     .ext_rtcfg_addr (16'h0),
     .ext_rtcfg_data (32'h0),
@@ -318,6 +334,128 @@ module rfnoc_image_core #(
     .signal_data_err    (1'b0              )
   );
 
+  wire [CHDR_W-1:0] m_ep2_out0_tdata;
+  wire              m_ep2_out0_tlast;
+  wire              m_ep2_out0_tvalid;
+  wire              m_ep2_out0_tready;
+  wire [CHDR_W-1:0] s_ep2_in0_tdata;
+  wire              s_ep2_in0_tlast;
+  wire              s_ep2_in0_tvalid;
+  wire              s_ep2_in0_tready;
+  wire [31:0]       m_ep2_ctrl_tdata , s_ep2_ctrl_tdata ;
+  wire              m_ep2_ctrl_tlast , s_ep2_ctrl_tlast ;
+  wire              m_ep2_ctrl_tvalid, s_ep2_ctrl_tvalid;
+  wire              m_ep2_ctrl_tready, s_ep2_ctrl_tready;
+
+  chdr_stream_endpoint #(
+    .PROTOVER           (PROTOVER),
+    .CHDR_W             (CHDR_W),
+    .AXIS_CTRL_EN       (0),
+    .AXIS_DATA_EN       (1),
+    .NUM_DATA_I         (1),
+    .NUM_DATA_O         (1),
+    .INST_NUM           (2),
+    .CTRL_XBAR_PORT     (3),
+    .INGRESS_BUFF_SIZE  (12),
+    .MTU                (MTU),
+    .REPORT_STRM_ERRS   (1)
+  ) ep2_i (
+    .rfnoc_chdr_clk     (rfnoc_chdr_clk    ),
+    .rfnoc_chdr_rst     (rfnoc_chdr_rst    ),
+    .rfnoc_ctrl_clk     (rfnoc_ctrl_clk    ),
+    .rfnoc_ctrl_rst     (rfnoc_ctrl_rst    ),
+    .device_id          (device_id         ),
+    .s_axis_chdr_tdata  (xb_to_ep2_tdata  ),
+    .s_axis_chdr_tlast  (xb_to_ep2_tlast  ),
+    .s_axis_chdr_tvalid (xb_to_ep2_tvalid ),
+    .s_axis_chdr_tready (xb_to_ep2_tready ),
+    .m_axis_chdr_tdata  (ep2_to_xb_tdata  ),
+    .m_axis_chdr_tlast  (ep2_to_xb_tlast  ),
+    .m_axis_chdr_tvalid (ep2_to_xb_tvalid ),
+    .m_axis_chdr_tready (ep2_to_xb_tready ),
+    .s_axis_data_tdata  ({s_ep2_in0_tdata}),
+    .s_axis_data_tlast  ({s_ep2_in0_tlast}),
+    .s_axis_data_tvalid ({s_ep2_in0_tvalid}),
+    .s_axis_data_tready ({s_ep2_in0_tready}),
+    .m_axis_data_tdata  ({m_ep2_out0_tdata}),
+    .m_axis_data_tlast  ({m_ep2_out0_tlast}),
+    .m_axis_data_tvalid ({m_ep2_out0_tvalid}),
+    .m_axis_data_tready ({m_ep2_out0_tready}),
+    .s_axis_ctrl_tdata  (s_ep2_ctrl_tdata ),
+    .s_axis_ctrl_tlast  (s_ep2_ctrl_tlast ),
+    .s_axis_ctrl_tvalid (s_ep2_ctrl_tvalid),
+    .s_axis_ctrl_tready (s_ep2_ctrl_tready),
+    .m_axis_ctrl_tdata  (m_ep2_ctrl_tdata ),
+    .m_axis_ctrl_tlast  (m_ep2_ctrl_tlast ),
+    .m_axis_ctrl_tvalid (m_ep2_ctrl_tvalid),
+    .m_axis_ctrl_tready (m_ep2_ctrl_tready),
+    .strm_seq_err_stb   (                  ),
+    .strm_data_err_stb  (                  ),
+    .strm_route_err_stb (                  ),
+    .signal_data_err    (1'b0              )
+  );
+
+  wire [CHDR_W-1:0] m_ep3_out0_tdata;
+  wire              m_ep3_out0_tlast;
+  wire              m_ep3_out0_tvalid;
+  wire              m_ep3_out0_tready;
+  wire [CHDR_W-1:0] s_ep3_in0_tdata;
+  wire              s_ep3_in0_tlast;
+  wire              s_ep3_in0_tvalid;
+  wire              s_ep3_in0_tready;
+  wire [31:0]       m_ep3_ctrl_tdata , s_ep3_ctrl_tdata ;
+  wire              m_ep3_ctrl_tlast , s_ep3_ctrl_tlast ;
+  wire              m_ep3_ctrl_tvalid, s_ep3_ctrl_tvalid;
+  wire              m_ep3_ctrl_tready, s_ep3_ctrl_tready;
+
+  chdr_stream_endpoint #(
+    .PROTOVER           (PROTOVER),
+    .CHDR_W             (CHDR_W),
+    .AXIS_CTRL_EN       (0),
+    .AXIS_DATA_EN       (1),
+    .NUM_DATA_I         (1),
+    .NUM_DATA_O         (1),
+    .INST_NUM           (3),
+    .CTRL_XBAR_PORT     (4),
+    .INGRESS_BUFF_SIZE  (12),
+    .MTU                (MTU),
+    .REPORT_STRM_ERRS   (1)
+  ) ep3_i (
+    .rfnoc_chdr_clk     (rfnoc_chdr_clk    ),
+    .rfnoc_chdr_rst     (rfnoc_chdr_rst    ),
+    .rfnoc_ctrl_clk     (rfnoc_ctrl_clk    ),
+    .rfnoc_ctrl_rst     (rfnoc_ctrl_rst    ),
+    .device_id          (device_id         ),
+    .s_axis_chdr_tdata  (xb_to_ep3_tdata  ),
+    .s_axis_chdr_tlast  (xb_to_ep3_tlast  ),
+    .s_axis_chdr_tvalid (xb_to_ep3_tvalid ),
+    .s_axis_chdr_tready (xb_to_ep3_tready ),
+    .m_axis_chdr_tdata  (ep3_to_xb_tdata  ),
+    .m_axis_chdr_tlast  (ep3_to_xb_tlast  ),
+    .m_axis_chdr_tvalid (ep3_to_xb_tvalid ),
+    .m_axis_chdr_tready (ep3_to_xb_tready ),
+    .s_axis_data_tdata  ({s_ep3_in0_tdata}),
+    .s_axis_data_tlast  ({s_ep3_in0_tlast}),
+    .s_axis_data_tvalid ({s_ep3_in0_tvalid}),
+    .s_axis_data_tready ({s_ep3_in0_tready}),
+    .m_axis_data_tdata  ({m_ep3_out0_tdata}),
+    .m_axis_data_tlast  ({m_ep3_out0_tlast}),
+    .m_axis_data_tvalid ({m_ep3_out0_tvalid}),
+    .m_axis_data_tready ({m_ep3_out0_tready}),
+    .s_axis_ctrl_tdata  (s_ep3_ctrl_tdata ),
+    .s_axis_ctrl_tlast  (s_ep3_ctrl_tlast ),
+    .s_axis_ctrl_tvalid (s_ep3_ctrl_tvalid),
+    .s_axis_ctrl_tready (s_ep3_ctrl_tready),
+    .m_axis_ctrl_tdata  (m_ep3_ctrl_tdata ),
+    .m_axis_ctrl_tlast  (m_ep3_ctrl_tlast ),
+    .m_axis_ctrl_tvalid (m_ep3_ctrl_tvalid),
+    .m_axis_ctrl_tready (m_ep3_ctrl_tready),
+    .strm_seq_err_stb   (                  ),
+    .strm_data_err_stb  (                  ),
+    .strm_route_err_stb (                  ),
+    .signal_data_err    (1'b0              )
+  );
+
 
 
   // ----------------------------------------------------
@@ -352,10 +490,14 @@ module rfnoc_image_core #(
   wire              m_radio1_ctrl_tlast ,   s_radio1_ctrl_tlast ;
   wire              m_radio1_ctrl_tvalid,   s_radio1_ctrl_tvalid;
   wire              m_radio1_ctrl_tready,   s_radio1_ctrl_tready;
+  wire [31:0]       m_replay0_ctrl_tdata ,   s_replay0_ctrl_tdata ;
+  wire              m_replay0_ctrl_tlast ,   s_replay0_ctrl_tlast ;
+  wire              m_replay0_ctrl_tvalid,   s_replay0_ctrl_tvalid;
+  wire              m_replay0_ctrl_tready,   s_replay0_ctrl_tready;
 
   axis_ctrl_crossbar_nxn #(
     .WIDTH            (32),
-    .NPORTS           (8),
+    .NPORTS           (9),
     .TOPOLOGY         ("TORUS"),
     .INGRESS_BUFF_SIZE(5),
     .ROUTER_BUFF_SIZE (5),
@@ -364,32 +506,32 @@ module rfnoc_image_core #(
   ) ctrl_xb_i (
     .clk              (rfnoc_ctrl_clk),
     .reset            (rfnoc_ctrl_rst),
-    .s_axis_tdata     ({m_radio1_ctrl_tdata , m_ddc1_ctrl_tdata , m_duc1_ctrl_tdata , m_radio0_ctrl_tdata , m_ddc0_ctrl_tdata , m_duc0_ctrl_tdata , m_ep0_ctrl_tdata , m_core_ctrl_tdata }),
-    .s_axis_tvalid    ({m_radio1_ctrl_tvalid, m_ddc1_ctrl_tvalid, m_duc1_ctrl_tvalid, m_radio0_ctrl_tvalid, m_ddc0_ctrl_tvalid, m_duc0_ctrl_tvalid, m_ep0_ctrl_tvalid, m_core_ctrl_tvalid}),
-    .s_axis_tlast     ({m_radio1_ctrl_tlast , m_ddc1_ctrl_tlast , m_duc1_ctrl_tlast , m_radio0_ctrl_tlast , m_ddc0_ctrl_tlast , m_duc0_ctrl_tlast , m_ep0_ctrl_tlast , m_core_ctrl_tlast }),
-    .s_axis_tready    ({m_radio1_ctrl_tready, m_ddc1_ctrl_tready, m_duc1_ctrl_tready, m_radio0_ctrl_tready, m_ddc0_ctrl_tready, m_duc0_ctrl_tready, m_ep0_ctrl_tready, m_core_ctrl_tready}),
-    .m_axis_tdata     ({s_radio1_ctrl_tdata , s_ddc1_ctrl_tdata , s_duc1_ctrl_tdata , s_radio0_ctrl_tdata , s_ddc0_ctrl_tdata , s_duc0_ctrl_tdata , s_ep0_ctrl_tdata , s_core_ctrl_tdata }),
-    .m_axis_tvalid    ({s_radio1_ctrl_tvalid, s_ddc1_ctrl_tvalid, s_duc1_ctrl_tvalid, s_radio0_ctrl_tvalid, s_ddc0_ctrl_tvalid, s_duc0_ctrl_tvalid, s_ep0_ctrl_tvalid, s_core_ctrl_tvalid}),
-    .m_axis_tlast     ({s_radio1_ctrl_tlast , s_ddc1_ctrl_tlast , s_duc1_ctrl_tlast , s_radio0_ctrl_tlast , s_ddc0_ctrl_tlast , s_duc0_ctrl_tlast , s_ep0_ctrl_tlast , s_core_ctrl_tlast }),
-    .m_axis_tready    ({s_radio1_ctrl_tready, s_ddc1_ctrl_tready, s_duc1_ctrl_tready, s_radio0_ctrl_tready, s_ddc0_ctrl_tready, s_duc0_ctrl_tready, s_ep0_ctrl_tready, s_core_ctrl_tready}),
+    .s_axis_tdata     ({m_replay0_ctrl_tdata , m_radio1_ctrl_tdata , m_ddc1_ctrl_tdata , m_duc1_ctrl_tdata , m_radio0_ctrl_tdata , m_ddc0_ctrl_tdata , m_duc0_ctrl_tdata , m_ep0_ctrl_tdata , m_core_ctrl_tdata }),
+    .s_axis_tvalid    ({m_replay0_ctrl_tvalid, m_radio1_ctrl_tvalid, m_ddc1_ctrl_tvalid, m_duc1_ctrl_tvalid, m_radio0_ctrl_tvalid, m_ddc0_ctrl_tvalid, m_duc0_ctrl_tvalid, m_ep0_ctrl_tvalid, m_core_ctrl_tvalid}),
+    .s_axis_tlast     ({m_replay0_ctrl_tlast , m_radio1_ctrl_tlast , m_ddc1_ctrl_tlast , m_duc1_ctrl_tlast , m_radio0_ctrl_tlast , m_ddc0_ctrl_tlast , m_duc0_ctrl_tlast , m_ep0_ctrl_tlast , m_core_ctrl_tlast }),
+    .s_axis_tready    ({m_replay0_ctrl_tready, m_radio1_ctrl_tready, m_ddc1_ctrl_tready, m_duc1_ctrl_tready, m_radio0_ctrl_tready, m_ddc0_ctrl_tready, m_duc0_ctrl_tready, m_ep0_ctrl_tready, m_core_ctrl_tready}),
+    .m_axis_tdata     ({s_replay0_ctrl_tdata , s_radio1_ctrl_tdata , s_ddc1_ctrl_tdata , s_duc1_ctrl_tdata , s_radio0_ctrl_tdata , s_ddc0_ctrl_tdata , s_duc0_ctrl_tdata , s_ep0_ctrl_tdata , s_core_ctrl_tdata }),
+    .m_axis_tvalid    ({s_replay0_ctrl_tvalid, s_radio1_ctrl_tvalid, s_ddc1_ctrl_tvalid, s_duc1_ctrl_tvalid, s_radio0_ctrl_tvalid, s_ddc0_ctrl_tvalid, s_duc0_ctrl_tvalid, s_ep0_ctrl_tvalid, s_core_ctrl_tvalid}),
+    .m_axis_tlast     ({s_replay0_ctrl_tlast , s_radio1_ctrl_tlast , s_ddc1_ctrl_tlast , s_duc1_ctrl_tlast , s_radio0_ctrl_tlast , s_ddc0_ctrl_tlast , s_duc0_ctrl_tlast , s_ep0_ctrl_tlast , s_core_ctrl_tlast }),
+    .m_axis_tready    ({s_replay0_ctrl_tready, s_radio1_ctrl_tready, s_ddc1_ctrl_tready, s_duc1_ctrl_tready, s_radio0_ctrl_tready, s_ddc0_ctrl_tready, s_duc0_ctrl_tready, s_ep0_ctrl_tready, s_core_ctrl_tready}),
     .deadlock_detected()
   );
 
   // ----------------------------------------------------
   // RFNoC Core Kernel
   // ----------------------------------------------------
-  wire [(512*6)-1:0] rfnoc_core_config, rfnoc_core_status;
+  wire [(512*7)-1:0] rfnoc_core_config, rfnoc_core_status;
 
   rfnoc_core_kernel #(
     .PROTOVER            (PROTOVER),
     .DEVICE_TYPE         (16'h1320),
     .DEVICE_FAMILY       ("7SERIES"),
     .SAFE_START_CLKS     (0),
-    .NUM_BLOCKS          (6),
-    .NUM_STREAM_ENDPOINTS(2),
+    .NUM_BLOCKS          (7),
+    .NUM_STREAM_ENDPOINTS(4),
     .NUM_ENDPOINTS_CTRL  (1),
     .NUM_TRANSPORTS      (3),
-    .NUM_EDGES           (8),
+    .NUM_EDGES           (12),
     .CHDR_XBAR_PRESENT   (1),
     .EDGE_TBL_FILE       (EDGE_TBL_FILE)
   ) core_kernel_i (
@@ -778,6 +920,145 @@ module rfnoc_image_core #(
 
 
   // ----------------------------------------------------
+  // replay0
+  // ----------------------------------------------------
+  wire              replay0_mem_clk;
+  wire [CHDR_W-1:0] s_replay0_in_1_tdata , s_replay0_in_0_tdata ;
+  wire              s_replay0_in_1_tlast , s_replay0_in_0_tlast ;
+  wire              s_replay0_in_1_tvalid, s_replay0_in_0_tvalid;
+  wire              s_replay0_in_1_tready, s_replay0_in_0_tready;
+  wire [CHDR_W-1:0] m_replay0_out_1_tdata , m_replay0_out_0_tdata ;
+  wire              m_replay0_out_1_tlast , m_replay0_out_0_tlast ;
+  wire              m_replay0_out_1_tvalid, m_replay0_out_0_tvalid;
+  wire              m_replay0_out_1_tready, m_replay0_out_0_tready;
+
+  //  axi_ram
+  wire [  1-1:0] replay0_axi_rst;
+  wire [  4-1:0] replay0_m_axi_awid;
+  wire [128-1:0] replay0_m_axi_awaddr;
+  wire [ 32-1:0] replay0_m_axi_awlen;
+  wire [ 12-1:0] replay0_m_axi_awsize;
+  wire [  8-1:0] replay0_m_axi_awburst;
+  wire [  4-1:0] replay0_m_axi_awlock;
+  wire [ 16-1:0] replay0_m_axi_awcache;
+  wire [ 12-1:0] replay0_m_axi_awprot;
+  wire [ 16-1:0] replay0_m_axi_awqos;
+  wire [ 16-1:0] replay0_m_axi_awregion;
+  wire [  4-1:0] replay0_m_axi_awuser;
+  wire [  4-1:0] replay0_m_axi_awvalid;
+  wire [  4-1:0] replay0_m_axi_awready;
+  wire [256-1:0] replay0_m_axi_wdata;
+  wire [ 32-1:0] replay0_m_axi_wstrb;
+  wire [  4-1:0] replay0_m_axi_wlast;
+  wire [  4-1:0] replay0_m_axi_wuser;
+  wire [  4-1:0] replay0_m_axi_wvalid;
+  wire [  4-1:0] replay0_m_axi_wready;
+  wire [  4-1:0] replay0_m_axi_bid;
+  wire [  8-1:0] replay0_m_axi_bresp;
+  wire [  4-1:0] replay0_m_axi_buser;
+  wire [  4-1:0] replay0_m_axi_bvalid;
+  wire [  4-1:0] replay0_m_axi_bready;
+  wire [  4-1:0] replay0_m_axi_arid;
+  wire [128-1:0] replay0_m_axi_araddr;
+  wire [ 32-1:0] replay0_m_axi_arlen;
+  wire [ 12-1:0] replay0_m_axi_arsize;
+  wire [  8-1:0] replay0_m_axi_arburst;
+  wire [  4-1:0] replay0_m_axi_arlock;
+  wire [ 16-1:0] replay0_m_axi_arcache;
+  wire [ 12-1:0] replay0_m_axi_arprot;
+  wire [ 16-1:0] replay0_m_axi_arqos;
+  wire [ 16-1:0] replay0_m_axi_arregion;
+  wire [  4-1:0] replay0_m_axi_aruser;
+  wire [  4-1:0] replay0_m_axi_arvalid;
+  wire [  4-1:0] replay0_m_axi_arready;
+  wire [  4-1:0] replay0_m_axi_rid;
+  wire [256-1:0] replay0_m_axi_rdata;
+  wire [  8-1:0] replay0_m_axi_rresp;
+  wire [  4-1:0] replay0_m_axi_rlast;
+  wire [  4-1:0] replay0_m_axi_ruser;
+  wire [  4-1:0] replay0_m_axi_rvalid;
+  wire [  4-1:0] replay0_m_axi_rready;
+
+  rfnoc_block_replay #(
+    .THIS_PORTID(8),
+    .CHDR_W(CHDR_W),
+    .NUM_PORTS(2),
+    .MEM_ADDR_W(31),
+    .MEM_DATA_W(64),
+    .MTU(MTU)
+  ) b_replay0_6 (
+    .rfnoc_chdr_clk     (rfnoc_chdr_clk),
+    .rfnoc_ctrl_clk     (rfnoc_ctrl_clk),
+    .mem_clk(replay0_mem_clk),
+    .rfnoc_core_config  (rfnoc_core_config[512*7-1:512*6]),
+    .rfnoc_core_status  (rfnoc_core_status[512*7-1:512*6]),
+
+    .axi_rst(replay0_axi_rst),
+    .m_axi_awid(replay0_m_axi_awid),
+    .m_axi_awaddr(replay0_m_axi_awaddr),
+    .m_axi_awlen(replay0_m_axi_awlen),
+    .m_axi_awsize(replay0_m_axi_awsize),
+    .m_axi_awburst(replay0_m_axi_awburst),
+    .m_axi_awlock(replay0_m_axi_awlock),
+    .m_axi_awcache(replay0_m_axi_awcache),
+    .m_axi_awprot(replay0_m_axi_awprot),
+    .m_axi_awqos(replay0_m_axi_awqos),
+    .m_axi_awregion(replay0_m_axi_awregion),
+    .m_axi_awuser(replay0_m_axi_awuser),
+    .m_axi_awvalid(replay0_m_axi_awvalid),
+    .m_axi_awready(replay0_m_axi_awready),
+    .m_axi_wdata(replay0_m_axi_wdata),
+    .m_axi_wstrb(replay0_m_axi_wstrb),
+    .m_axi_wlast(replay0_m_axi_wlast),
+    .m_axi_wuser(replay0_m_axi_wuser),
+    .m_axi_wvalid(replay0_m_axi_wvalid),
+    .m_axi_wready(replay0_m_axi_wready),
+    .m_axi_bid(replay0_m_axi_bid),
+    .m_axi_bresp(replay0_m_axi_bresp),
+    .m_axi_buser(replay0_m_axi_buser),
+    .m_axi_bvalid(replay0_m_axi_bvalid),
+    .m_axi_bready(replay0_m_axi_bready),
+    .m_axi_arid(replay0_m_axi_arid),
+    .m_axi_araddr(replay0_m_axi_araddr),
+    .m_axi_arlen(replay0_m_axi_arlen),
+    .m_axi_arsize(replay0_m_axi_arsize),
+    .m_axi_arburst(replay0_m_axi_arburst),
+    .m_axi_arlock(replay0_m_axi_arlock),
+    .m_axi_arcache(replay0_m_axi_arcache),
+    .m_axi_arprot(replay0_m_axi_arprot),
+    .m_axi_arqos(replay0_m_axi_arqos),
+    .m_axi_arregion(replay0_m_axi_arregion),
+    .m_axi_aruser(replay0_m_axi_aruser),
+    .m_axi_arvalid(replay0_m_axi_arvalid),
+    .m_axi_arready(replay0_m_axi_arready),
+    .m_axi_rid(replay0_m_axi_rid),
+    .m_axi_rdata(replay0_m_axi_rdata),
+    .m_axi_rresp(replay0_m_axi_rresp),
+    .m_axi_rlast(replay0_m_axi_rlast),
+    .m_axi_ruser(replay0_m_axi_ruser),
+    .m_axi_rvalid(replay0_m_axi_rvalid),
+    .m_axi_rready(replay0_m_axi_rready),
+
+    .s_rfnoc_chdr_tdata ({s_replay0_in_1_tdata , s_replay0_in_0_tdata }),
+    .s_rfnoc_chdr_tlast ({s_replay0_in_1_tlast , s_replay0_in_0_tlast }),
+    .s_rfnoc_chdr_tvalid({s_replay0_in_1_tvalid, s_replay0_in_0_tvalid}),
+    .s_rfnoc_chdr_tready({s_replay0_in_1_tready, s_replay0_in_0_tready}),
+    .m_rfnoc_chdr_tdata ({m_replay0_out_1_tdata , m_replay0_out_0_tdata }),
+    .m_rfnoc_chdr_tlast ({m_replay0_out_1_tlast , m_replay0_out_0_tlast }),
+    .m_rfnoc_chdr_tvalid({m_replay0_out_1_tvalid, m_replay0_out_0_tvalid}),
+    .m_rfnoc_chdr_tready({m_replay0_out_1_tready, m_replay0_out_0_tready}),
+    .s_rfnoc_ctrl_tdata (s_replay0_ctrl_tdata ),
+    .s_rfnoc_ctrl_tlast (s_replay0_ctrl_tlast ),
+    .s_rfnoc_ctrl_tvalid(s_replay0_ctrl_tvalid),
+    .s_rfnoc_ctrl_tready(s_replay0_ctrl_tready),
+    .m_rfnoc_ctrl_tdata (m_replay0_ctrl_tdata ),
+    .m_rfnoc_ctrl_tlast (m_replay0_ctrl_tlast ),
+    .m_rfnoc_ctrl_tvalid(m_replay0_ctrl_tvalid),
+    .m_rfnoc_ctrl_tready(m_replay0_ctrl_tready)
+  );
+
+
+  // ----------------------------------------------------
   // Static Router
   // ----------------------------------------------------
   assign s_duc0_in_0_tdata = m_ep0_out0_tdata ;
@@ -820,6 +1101,26 @@ module rfnoc_image_core #(
   assign s_ep1_in0_tvalid = m_ddc1_out_0_tvalid;
   assign m_ddc1_out_0_tready = s_ep1_in0_tready;
 
+  assign s_replay0_in_0_tdata = m_ep2_out0_tdata ;
+  assign s_replay0_in_0_tlast = m_ep2_out0_tlast ;
+  assign s_replay0_in_0_tvalid = m_ep2_out0_tvalid;
+  assign m_ep2_out0_tready = s_replay0_in_0_tready;
+
+  assign s_ep2_in0_tdata = m_replay0_out_0_tdata ;
+  assign s_ep2_in0_tlast = m_replay0_out_0_tlast ;
+  assign s_ep2_in0_tvalid = m_replay0_out_0_tvalid;
+  assign m_replay0_out_0_tready = s_ep2_in0_tready;
+
+  assign s_replay0_in_1_tdata = m_ep3_out0_tdata ;
+  assign s_replay0_in_1_tlast = m_ep3_out0_tlast ;
+  assign s_replay0_in_1_tvalid = m_ep3_out0_tvalid;
+  assign m_ep3_out0_tready = s_replay0_in_1_tready;
+
+  assign s_ep3_in0_tdata = m_replay0_out_1_tdata ;
+  assign s_ep3_in0_tlast = m_replay0_out_1_tlast ;
+  assign s_ep3_in0_tvalid = m_replay0_out_1_tvalid;
+  assign m_replay0_out_1_tready = s_ep3_in0_tready;
+
 
   // ----------------------------------------------------
   // Unused Ports
@@ -834,6 +1135,7 @@ module rfnoc_image_core #(
   assign radio1_radio_clk = radio_clk;
   assign ddc1_ce_clk = radio_clk;
   assign duc1_ce_clk = radio_clk;
+  assign replay0_mem_clk = dram_clk;
 
 
   // ----------------------------------------------------
@@ -862,6 +1164,52 @@ module rfnoc_image_core #(
   assign radio1_m_ctrlport_resp_status = m_ctrlport_radio1_resp_status;
   assign radio1_m_ctrlport_resp_data = m_ctrlport_radio1_resp_data;
 
+  assign replay0_axi_rst = axi_rst;
+  assign m_axi_awid = replay0_m_axi_awid;
+  assign m_axi_awaddr = replay0_m_axi_awaddr;
+  assign m_axi_awlen = replay0_m_axi_awlen;
+  assign m_axi_awsize = replay0_m_axi_awsize;
+  assign m_axi_awburst = replay0_m_axi_awburst;
+  assign m_axi_awlock = replay0_m_axi_awlock;
+  assign m_axi_awcache = replay0_m_axi_awcache;
+  assign m_axi_awprot = replay0_m_axi_awprot;
+  assign m_axi_awqos = replay0_m_axi_awqos;
+  assign m_axi_awregion = replay0_m_axi_awregion;
+  assign m_axi_awuser = replay0_m_axi_awuser;
+  assign m_axi_awvalid = replay0_m_axi_awvalid;
+  assign replay0_m_axi_awready = m_axi_awready;
+  assign m_axi_wdata = replay0_m_axi_wdata;
+  assign m_axi_wstrb = replay0_m_axi_wstrb;
+  assign m_axi_wlast = replay0_m_axi_wlast;
+  assign m_axi_wuser = replay0_m_axi_wuser;
+  assign m_axi_wvalid = replay0_m_axi_wvalid;
+  assign replay0_m_axi_wready = m_axi_wready;
+  assign replay0_m_axi_bid = m_axi_bid;
+  assign replay0_m_axi_bresp = m_axi_bresp;
+  assign replay0_m_axi_buser = m_axi_buser;
+  assign replay0_m_axi_bvalid = m_axi_bvalid;
+  assign m_axi_bready = replay0_m_axi_bready;
+  assign m_axi_arid = replay0_m_axi_arid;
+  assign m_axi_araddr = replay0_m_axi_araddr;
+  assign m_axi_arlen = replay0_m_axi_arlen;
+  assign m_axi_arsize = replay0_m_axi_arsize;
+  assign m_axi_arburst = replay0_m_axi_arburst;
+  assign m_axi_arlock = replay0_m_axi_arlock;
+  assign m_axi_arcache = replay0_m_axi_arcache;
+  assign m_axi_arprot = replay0_m_axi_arprot;
+  assign m_axi_arqos = replay0_m_axi_arqos;
+  assign m_axi_arregion = replay0_m_axi_arregion;
+  assign m_axi_aruser = replay0_m_axi_aruser;
+  assign m_axi_arvalid = replay0_m_axi_arvalid;
+  assign replay0_m_axi_arready = m_axi_arready;
+  assign replay0_m_axi_rid = m_axi_rid;
+  assign replay0_m_axi_rdata = m_axi_rdata;
+  assign replay0_m_axi_rresp = m_axi_rresp;
+  assign replay0_m_axi_rlast = m_axi_rlast;
+  assign replay0_m_axi_ruser = m_axi_ruser;
+  assign replay0_m_axi_rvalid = m_axi_rvalid;
+  assign m_axi_rready = replay0_m_axi_rready;
+
   assign radio0_radio_rx_data = radio_rx_data_radio0;
   assign radio0_radio_rx_stb = radio_rx_stb_radio0;
   assign radio_rx_running_radio0 = radio0_radio_rx_running;
diff --git a/fpga/usrp3/top/n3xx/n320_rfnoc_image_core.yml b/fpga/usrp3/top/n3xx/n320_rfnoc_image_core.yml
index 5f1850d52..ecddcc3d0 100644
--- a/fpga/usrp3/top/n3xx/n320_rfnoc_image_core.yml
+++ b/fpga/usrp3/top/n3xx/n320_rfnoc_image_core.yml
@@ -20,6 +20,14 @@ stream_endpoints:
     ctrl: False                       # Endpoint passes control traffic
     data: True                        # Endpoint passes data traffic
     buff_size: 65536                  # Ingress buffer size for data
+  ep2:                       # Stream endpoint name
+    ctrl: False                     # Endpoint passes control traffic
+    data: True                      # Endpoint passes data traffic
+    buff_size: 4096                 # Ingress buffer size for data
+  ep3:                       # Stream endpoint name
+    ctrl: False                     # Endpoint passes control traffic
+    data: True                      # Endpoint passes data traffic
+    buff_size: 4096                 # Ingress buffer size for data
 
 # A list of all NoC blocks in design
 # ----------------------------------
@@ -44,16 +52,11 @@ noc_blocks:
       NUM_PORTS: 1
   radio1:
     block_desc: 'radio_1x64.yml'
-  #fifo0:
-    #block_desc: 'axi_ram_fifo_4x64.yml'
-    #parameters:
-      ## These parameters match the memory interface on the N3XX
-      #NUM_PORTS: 4
-      #MEM_DATA_W: 64
-      #MEM_ADDR_W: 31
-      #FIFO_ADDR_BASE: "{30'h06000000, 30'h04000000, 30'h02000000, 30'h00000000}"
-      #FIFO_ADDR_MASK: "{30'h01FFFFFF, 30'h01FFFFFF, 30'h01FFFFFF, 30'h01FFFFFF}"
-      #MEM_CLK_RATE: "303819444" # 166.666666 MHz * 21.875 / 4 / 3 = 303.819444 MHz
+  replay0:
+    block_desc: 'replay.yml'
+    parameters:
+      NUM_PORTS: 2
+      MEM_ADDR_W: 31
 
 # A list of all static connections in design
 # ------------------------------------------
@@ -71,8 +74,13 @@ connections:
   - { srcblk: duc1,   srcport: out_0, dstblk: radio1, dstport: in_0 }
   - { srcblk: radio1, srcport: out_0, dstblk: ddc1,   dstport: in_0 }
   - { srcblk: ddc1,   srcport: out_0, dstblk: ep1,    dstport: in0  }
+  - { srcblk: ep2,     srcport: out0,  dstblk: replay0, dstport: in_0 }
+  - { srcblk: replay0, srcport: out_0, dstblk: ep2,     dstport: in0  }
+  - { srcblk: ep3,     srcport: out0,  dstblk: replay0, dstport: in_1 }
+  - { srcblk: replay0, srcport: out_1, dstblk: ep3,     dstport: in0  }
   - { srcblk: radio0, srcport: ctrl_port, dstblk: _device_, dstport: ctrlport_radio0 }
   - { srcblk: radio1, srcport: ctrl_port, dstblk: _device_, dstport: ctrlport_radio1 }
+  - { srcblk: replay0, srcport: axi_ram, dstblk: _device_, dstport: dram }
   - { srcblk: _device_, srcport: radio_ch0, dstblk: radio0, dstport: radio_iface }
   - { srcblk: _device_, srcport: radio_ch1, dstblk: radio1, dstport: radio_iface }
   - { srcblk: _device_, srcport: time_keeper, dstblk: radio0, dstport: time_keeper }
@@ -92,4 +100,4 @@ clk_domains:
   - { srcblk: _device_, srcport: radio, dstblk: radio1, dstport: radio }
   - { srcblk: _device_, srcport: radio, dstblk: ddc1,   dstport: ce    }
   - { srcblk: _device_, srcport: radio, dstblk: duc1,   dstport: ce    }
-# - { srcblk: _device_, srcport: dram,  dstblk: fifo0,  dstport: mem   }
+  - { srcblk: _device_, srcport: dram,  dstblk: replay0, dstport: mem  }
diff --git a/fpga/usrp3/top/n3xx/n320_static_router.hex b/fpga/usrp3/top/n3xx/n320_static_router.hex
index eeaf5024d..5fa678758 100644
--- a/fpga/usrp3/top/n3xx/n320_static_router.hex
+++ b/fpga/usrp3/top/n3xx/n320_static_router.hex
@@ -1,9 +1,13 @@
-00000008
-004000c0
-00c00140
-01400100
-01000040
-00800180
-01800200
-020001c0
-01c00080
+0000000C
+00400140
+014001c0
+01c00180
+01800040
+00800200
+02000280
+02800240
+02400080
+00c002c0
+02c000c0
+010002c1
+02c10100
diff --git a/fpga/usrp3/top/x300/Makefile.x300.inc b/fpga/usrp3/top/x300/Makefile.x300.inc
index a1810e628..1f18cbf02 100644
--- a/fpga/usrp3/top/x300/Makefile.x300.inc
+++ b/fpga/usrp3/top/x300/Makefile.x300.inc
@@ -37,12 +37,13 @@ include $(LIB_DIR)/axi/Makefile.srcs
 include $(LIB_DIR)/io_cap_gen/Makefile.srcs
 include $(LIB_DIR)/rfnoc/Makefile.srcs
 # For sake of convenience, we include the Makefile.srcs for DRAM FIFO, DDC, and
-# DUC, and of course the radio. Any other block needs to use the
+# DUC, Replay, and of course the radio. Any other block needs to use the
 # RFNOC_OOT_MAKEFILE_SRCS variable (see below).
 include $(LIB_DIR)/rfnoc/blocks/rfnoc_block_axi_ram_fifo/Makefile.srcs
 include $(LIB_DIR)/rfnoc/blocks/rfnoc_block_radio/Makefile.srcs
 include $(LIB_DIR)/rfnoc/blocks/rfnoc_block_ddc/Makefile.srcs
 include $(LIB_DIR)/rfnoc/blocks/rfnoc_block_duc/Makefile.srcs
+include $(LIB_DIR)/rfnoc/blocks/rfnoc_block_replay/Makefile.srcs
 # If out-of-tree modules want to be compiled into this image, then they need to
 # pass in the RFNOC_OOT_MAKEFILE_SRCS as a list of Makefile.srcs files.
 # Those files need to amend the RFNOC_OOT_SRCS variable with a list of actual
@@ -109,6 +110,7 @@ $(RFNOC_SRCS) $(LIB_IP_XCI_SRCS) \
 $(RFNOC_FRAMEWORK_SRCS) \
 $(RFNOC_BLOCK_DUC_SRCS) $(RFNOC_BLOCK_DDC_SRCS) $(RFNOC_BLOCK_RADIO_SRCS) \
 $(RFNOC_BLOCK_AXI_RAM_FIFO_SRCS) \
+$(RFNOC_BLOCK_REPLAY_SRCS) \
 $(RFNOC_OOT_SRCS)
 
 EDGE_TBL_DEF="RFNOC_EDGE_TBL_FILE=$(call RESOLVE_PATH,$(EDGE_FILE))"
diff --git a/fpga/usrp3/top/x300/x300_rfnoc_image_core.v b/fpga/usrp3/top/x300/x300_rfnoc_image_core.v
index 0c0518f5e..dc6fc4708 100644
--- a/fpga/usrp3/top/x300/x300_rfnoc_image_core.v
+++ b/fpga/usrp3/top/x300/x300_rfnoc_image_core.v
@@ -1,5 +1,5 @@
 //
-// Copyright 2019 Ettus Research, A National Instruments Brand
+// Copyright 2020 Ettus Research, A National Instruments Brand
 //
 // SPDX-License-Identifier: LGPL-3.0-or-later
 //
@@ -7,9 +7,9 @@
 // Module: rfnoc_image_core (for x300)
 // This file was autogenerated by UHD's image builder tool (rfnoc_image_builder)
 // Re-running that tool will overwrite this file!
-// File generated on: 2019-11-12T07:57:49.576474
-// Source: ./x300/x300_rfnoc_image_core.yml
-// Source SHA256: 883fe3d3773daf082a166936eec214ce68c3925a5928d7442302f8a75058d989
+// File generated on: 2020-09-02T12:02:29.163114
+// Source: ./x300_rfnoc_image_core.yml
+// Source SHA256: f64f8b03f805ae93e92c29cbdf8874c497d7ad93d546947e26fa8da501df6e18
 
 module rfnoc_image_core #(
   parameter [15:0] PROTOVER = {8'd1, 8'd0}
@@ -64,50 +64,50 @@ module rfnoc_image_core #(
   output wire [  2-1:0] radio_tx_running_radio1,
 //  dram
   input  wire [  1-1:0] axi_rst,
-  output wire [  2-1:0] m_axi_awid,
-  output wire [ 64-1:0] m_axi_awaddr,
-  output wire [ 16-1:0] m_axi_awlen,
-  output wire [  6-1:0] m_axi_awsize,
-  output wire [  4-1:0] m_axi_awburst,
-  output wire [  2-1:0] m_axi_awlock,
-  output wire [  8-1:0] m_axi_awcache,
-  output wire [  6-1:0] m_axi_awprot,
-  output wire [  8-1:0] m_axi_awqos,
-  output wire [  8-1:0] m_axi_awregion,
-  output wire [  2-1:0] m_axi_awuser,
-  output wire [  2-1:0] m_axi_awvalid,
-  input  wire [  2-1:0] m_axi_awready,
-  output wire [128-1:0] m_axi_wdata,
-  output wire [ 16-1:0] m_axi_wstrb,
-  output wire [  2-1:0] m_axi_wlast,
-  output wire [  2-1:0] m_axi_wuser,
-  output wire [  2-1:0] m_axi_wvalid,
-  input  wire [  2-1:0] m_axi_wready,
-  input  wire [  2-1:0] m_axi_bid,
-  input  wire [  4-1:0] m_axi_bresp,
-  input  wire [  2-1:0] m_axi_buser,
-  input  wire [  2-1:0] m_axi_bvalid,
-  output wire [  2-1:0] m_axi_bready,
-  output wire [  2-1:0] m_axi_arid,
-  output wire [ 64-1:0] m_axi_araddr,
-  output wire [ 16-1:0] m_axi_arlen,
-  output wire [  6-1:0] m_axi_arsize,
-  output wire [  4-1:0] m_axi_arburst,
-  output wire [  2-1:0] m_axi_arlock,
-  output wire [  8-1:0] m_axi_arcache,
-  output wire [  6-1:0] m_axi_arprot,
-  output wire [  8-1:0] m_axi_arqos,
-  output wire [  8-1:0] m_axi_arregion,
-  output wire [  2-1:0] m_axi_aruser,
-  output wire [  2-1:0] m_axi_arvalid,
-  input  wire [  2-1:0] m_axi_arready,
-  input  wire [  2-1:0] m_axi_rid,
-  input  wire [128-1:0] m_axi_rdata,
-  input  wire [  4-1:0] m_axi_rresp,
-  input  wire [  2-1:0] m_axi_rlast,
-  input  wire [  2-1:0] m_axi_ruser,
-  input  wire [  2-1:0] m_axi_rvalid,
-  output wire [  2-1:0] m_axi_rready,
+  output wire [  4-1:0] m_axi_awid,
+  output wire [128-1:0] m_axi_awaddr,
+  output wire [ 32-1:0] m_axi_awlen,
+  output wire [ 12-1:0] m_axi_awsize,
+  output wire [  8-1:0] m_axi_awburst,
+  output wire [  4-1:0] m_axi_awlock,
+  output wire [ 16-1:0] m_axi_awcache,
+  output wire [ 12-1:0] m_axi_awprot,
+  output wire [ 16-1:0] m_axi_awqos,
+  output wire [ 16-1:0] m_axi_awregion,
+  output wire [  4-1:0] m_axi_awuser,
+  output wire [  4-1:0] m_axi_awvalid,
+  input  wire [  4-1:0] m_axi_awready,
+  output wire [256-1:0] m_axi_wdata,
+  output wire [ 32-1:0] m_axi_wstrb,
+  output wire [  4-1:0] m_axi_wlast,
+  output wire [  4-1:0] m_axi_wuser,
+  output wire [  4-1:0] m_axi_wvalid,
+  input  wire [  4-1:0] m_axi_wready,
+  input  wire [  4-1:0] m_axi_bid,
+  input  wire [  8-1:0] m_axi_bresp,
+  input  wire [  4-1:0] m_axi_buser,
+  input  wire [  4-1:0] m_axi_bvalid,
+  output wire [  4-1:0] m_axi_bready,
+  output wire [  4-1:0] m_axi_arid,
+  output wire [128-1:0] m_axi_araddr,
+  output wire [ 32-1:0] m_axi_arlen,
+  output wire [ 12-1:0] m_axi_arsize,
+  output wire [  8-1:0] m_axi_arburst,
+  output wire [  4-1:0] m_axi_arlock,
+  output wire [ 16-1:0] m_axi_arcache,
+  output wire [ 12-1:0] m_axi_arprot,
+  output wire [ 16-1:0] m_axi_arqos,
+  output wire [ 16-1:0] m_axi_arregion,
+  output wire [  4-1:0] m_axi_aruser,
+  output wire [  4-1:0] m_axi_arvalid,
+  input  wire [  4-1:0] m_axi_arready,
+  input  wire [  4-1:0] m_axi_rid,
+  input  wire [256-1:0] m_axi_rdata,
+  input  wire [  8-1:0] m_axi_rresp,
+  input  wire [  4-1:0] m_axi_rlast,
+  input  wire [  4-1:0] m_axi_ruser,
+  input  wire [  4-1:0] m_axi_rvalid,
+  output wire [  4-1:0] m_axi_rready,
   // Transport 0 (eth0 10G)
   input  wire [64-1:0]  s_eth0_tdata,
   input  wire         s_eth0_tlast,
@@ -179,10 +179,26 @@ module rfnoc_image_core #(
   wire              ep3_to_xb_tlast ;
   wire              ep3_to_xb_tvalid;
   wire              ep3_to_xb_tready;
+  wire [CHDR_W-1:0] xb_to_ep4_tdata ;
+  wire              xb_to_ep4_tlast ;
+  wire              xb_to_ep4_tvalid;
+  wire              xb_to_ep4_tready;
+  wire [CHDR_W-1:0] ep4_to_xb_tdata ;
+  wire              ep4_to_xb_tlast ;
+  wire              ep4_to_xb_tvalid;
+  wire              ep4_to_xb_tready;
+  wire [CHDR_W-1:0] xb_to_ep5_tdata ;
+  wire              xb_to_ep5_tlast ;
+  wire              xb_to_ep5_tvalid;
+  wire              xb_to_ep5_tready;
+  wire [CHDR_W-1:0] ep5_to_xb_tdata ;
+  wire              ep5_to_xb_tlast ;
+  wire              ep5_to_xb_tvalid;
+  wire              ep5_to_xb_tready;
 
   chdr_crossbar_nxn #(
     .CHDR_W         (CHDR_W),
-    .NPORTS         (7),
+    .NPORTS         (9),
     .DEFAULT_PORT   (0),
     .MTU            (MTU),
     .ROUTE_TBL_SIZE (6),
@@ -195,14 +211,14 @@ module rfnoc_image_core #(
     .clk            (rfnoc_chdr_clk),
     .reset          (rfnoc_chdr_rst),
     .device_id      (device_id),
-    .s_axis_tdata   ({ep3_to_xb_tdata, ep2_to_xb_tdata, ep1_to_xb_tdata, ep0_to_xb_tdata, s_pcie_tdata, s_eth1_tdata, s_eth0_tdata}),
-    .s_axis_tlast   ({ep3_to_xb_tlast, ep2_to_xb_tlast, ep1_to_xb_tlast, ep0_to_xb_tlast, s_pcie_tlast, s_eth1_tlast, s_eth0_tlast}),
-    .s_axis_tvalid  ({ep3_to_xb_tvalid, ep2_to_xb_tvalid, ep1_to_xb_tvalid, ep0_to_xb_tvalid, s_pcie_tvalid, s_eth1_tvalid, s_eth0_tvalid}),
-    .s_axis_tready  ({ep3_to_xb_tready, ep2_to_xb_tready, ep1_to_xb_tready, ep0_to_xb_tready, s_pcie_tready, s_eth1_tready, s_eth0_tready}),
-    .m_axis_tdata   ({xb_to_ep3_tdata, xb_to_ep2_tdata, xb_to_ep1_tdata, xb_to_ep0_tdata, m_pcie_tdata, m_eth1_tdata, m_eth0_tdata}),
-    .m_axis_tlast   ({xb_to_ep3_tlast, xb_to_ep2_tlast, xb_to_ep1_tlast, xb_to_ep0_tlast, m_pcie_tlast, m_eth1_tlast, m_eth0_tlast}),
-    .m_axis_tvalid  ({xb_to_ep3_tvalid, xb_to_ep2_tvalid, xb_to_ep1_tvalid, xb_to_ep0_tvalid, m_pcie_tvalid, m_eth1_tvalid, m_eth0_tvalid}),
-    .m_axis_tready  ({xb_to_ep3_tready, xb_to_ep2_tready, xb_to_ep1_tready, xb_to_ep0_tready, m_pcie_tready, m_eth1_tready, m_eth0_tready}),
+    .s_axis_tdata   ({ep5_to_xb_tdata, ep4_to_xb_tdata, ep3_to_xb_tdata, ep2_to_xb_tdata, ep1_to_xb_tdata, ep0_to_xb_tdata, s_pcie_tdata, s_eth1_tdata, s_eth0_tdata}),
+    .s_axis_tlast   ({ep5_to_xb_tlast, ep4_to_xb_tlast, ep3_to_xb_tlast, ep2_to_xb_tlast, ep1_to_xb_tlast, ep0_to_xb_tlast, s_pcie_tlast, s_eth1_tlast, s_eth0_tlast}),
+    .s_axis_tvalid  ({ep5_to_xb_tvalid, ep4_to_xb_tvalid, ep3_to_xb_tvalid, ep2_to_xb_tvalid, ep1_to_xb_tvalid, ep0_to_xb_tvalid, s_pcie_tvalid, s_eth1_tvalid, s_eth0_tvalid}),
+    .s_axis_tready  ({ep5_to_xb_tready, ep4_to_xb_tready, ep3_to_xb_tready, ep2_to_xb_tready, ep1_to_xb_tready, ep0_to_xb_tready, s_pcie_tready, s_eth1_tready, s_eth0_tready}),
+    .m_axis_tdata   ({xb_to_ep5_tdata, xb_to_ep4_tdata, xb_to_ep3_tdata, xb_to_ep2_tdata, xb_to_ep1_tdata, xb_to_ep0_tdata, m_pcie_tdata, m_eth1_tdata, m_eth0_tdata}),
+    .m_axis_tlast   ({xb_to_ep5_tlast, xb_to_ep4_tlast, xb_to_ep3_tlast, xb_to_ep2_tlast, xb_to_ep1_tlast, xb_to_ep0_tlast, m_pcie_tlast, m_eth1_tlast, m_eth0_tlast}),
+    .m_axis_tvalid  ({xb_to_ep5_tvalid, xb_to_ep4_tvalid, xb_to_ep3_tvalid, xb_to_ep2_tvalid, xb_to_ep1_tvalid, xb_to_ep0_tvalid, m_pcie_tvalid, m_eth1_tvalid, m_eth0_tvalid}),
+    .m_axis_tready  ({xb_to_ep5_tready, xb_to_ep4_tready, xb_to_ep3_tready, xb_to_ep2_tready, xb_to_ep1_tready, xb_to_ep0_tready, m_pcie_tready, m_eth1_tready, m_eth0_tready}),
     .ext_rtcfg_stb  (1'h0),
     .ext_rtcfg_addr (16'h0),
     .ext_rtcfg_data (32'h0),
@@ -457,6 +473,128 @@ module rfnoc_image_core #(
     .signal_data_err    (1'b0              )
   );
 
+  wire [CHDR_W-1:0] m_ep4_out0_tdata;
+  wire              m_ep4_out0_tlast;
+  wire              m_ep4_out0_tvalid;
+  wire              m_ep4_out0_tready;
+  wire [CHDR_W-1:0] s_ep4_in0_tdata;
+  wire              s_ep4_in0_tlast;
+  wire              s_ep4_in0_tvalid;
+  wire              s_ep4_in0_tready;
+  wire [31:0]       m_ep4_ctrl_tdata , s_ep4_ctrl_tdata ;
+  wire              m_ep4_ctrl_tlast , s_ep4_ctrl_tlast ;
+  wire              m_ep4_ctrl_tvalid, s_ep4_ctrl_tvalid;
+  wire              m_ep4_ctrl_tready, s_ep4_ctrl_tready;
+
+  chdr_stream_endpoint #(
+    .PROTOVER           (PROTOVER),
+    .CHDR_W             (CHDR_W),
+    .AXIS_CTRL_EN       (0),
+    .AXIS_DATA_EN       (1),
+    .NUM_DATA_I         (1),
+    .NUM_DATA_O         (1),
+    .INST_NUM           (4),
+    .CTRL_XBAR_PORT     (5),
+    .INGRESS_BUFF_SIZE  (12),
+    .MTU                (MTU),
+    .REPORT_STRM_ERRS   (1)
+  ) ep4_i (
+    .rfnoc_chdr_clk     (rfnoc_chdr_clk    ),
+    .rfnoc_chdr_rst     (rfnoc_chdr_rst    ),
+    .rfnoc_ctrl_clk     (rfnoc_ctrl_clk    ),
+    .rfnoc_ctrl_rst     (rfnoc_ctrl_rst    ),
+    .device_id          (device_id         ),
+    .s_axis_chdr_tdata  (xb_to_ep4_tdata  ),
+    .s_axis_chdr_tlast  (xb_to_ep4_tlast  ),
+    .s_axis_chdr_tvalid (xb_to_ep4_tvalid ),
+    .s_axis_chdr_tready (xb_to_ep4_tready ),
+    .m_axis_chdr_tdata  (ep4_to_xb_tdata  ),
+    .m_axis_chdr_tlast  (ep4_to_xb_tlast  ),
+    .m_axis_chdr_tvalid (ep4_to_xb_tvalid ),
+    .m_axis_chdr_tready (ep4_to_xb_tready ),
+    .s_axis_data_tdata  ({s_ep4_in0_tdata}),
+    .s_axis_data_tlast  ({s_ep4_in0_tlast}),
+    .s_axis_data_tvalid ({s_ep4_in0_tvalid}),
+    .s_axis_data_tready ({s_ep4_in0_tready}),
+    .m_axis_data_tdata  ({m_ep4_out0_tdata}),
+    .m_axis_data_tlast  ({m_ep4_out0_tlast}),
+    .m_axis_data_tvalid ({m_ep4_out0_tvalid}),
+    .m_axis_data_tready ({m_ep4_out0_tready}),
+    .s_axis_ctrl_tdata  (s_ep4_ctrl_tdata ),
+    .s_axis_ctrl_tlast  (s_ep4_ctrl_tlast ),
+    .s_axis_ctrl_tvalid (s_ep4_ctrl_tvalid),
+    .s_axis_ctrl_tready (s_ep4_ctrl_tready),
+    .m_axis_ctrl_tdata  (m_ep4_ctrl_tdata ),
+    .m_axis_ctrl_tlast  (m_ep4_ctrl_tlast ),
+    .m_axis_ctrl_tvalid (m_ep4_ctrl_tvalid),
+    .m_axis_ctrl_tready (m_ep4_ctrl_tready),
+    .strm_seq_err_stb   (                  ),
+    .strm_data_err_stb  (                  ),
+    .strm_route_err_stb (                  ),
+    .signal_data_err    (1'b0              )
+  );
+
+  wire [CHDR_W-1:0] m_ep5_out0_tdata;
+  wire              m_ep5_out0_tlast;
+  wire              m_ep5_out0_tvalid;
+  wire              m_ep5_out0_tready;
+  wire [CHDR_W-1:0] s_ep5_in0_tdata;
+  wire              s_ep5_in0_tlast;
+  wire              s_ep5_in0_tvalid;
+  wire              s_ep5_in0_tready;
+  wire [31:0]       m_ep5_ctrl_tdata , s_ep5_ctrl_tdata ;
+  wire              m_ep5_ctrl_tlast , s_ep5_ctrl_tlast ;
+  wire              m_ep5_ctrl_tvalid, s_ep5_ctrl_tvalid;
+  wire              m_ep5_ctrl_tready, s_ep5_ctrl_tready;
+
+  chdr_stream_endpoint #(
+    .PROTOVER           (PROTOVER),
+    .CHDR_W             (CHDR_W),
+    .AXIS_CTRL_EN       (0),
+    .AXIS_DATA_EN       (1),
+    .NUM_DATA_I         (1),
+    .NUM_DATA_O         (1),
+    .INST_NUM           (5),
+    .CTRL_XBAR_PORT     (6),
+    .INGRESS_BUFF_SIZE  (12),
+    .MTU                (MTU),
+    .REPORT_STRM_ERRS   (1)
+  ) ep5_i (
+    .rfnoc_chdr_clk     (rfnoc_chdr_clk    ),
+    .rfnoc_chdr_rst     (rfnoc_chdr_rst    ),
+    .rfnoc_ctrl_clk     (rfnoc_ctrl_clk    ),
+    .rfnoc_ctrl_rst     (rfnoc_ctrl_rst    ),
+    .device_id          (device_id         ),
+    .s_axis_chdr_tdata  (xb_to_ep5_tdata  ),
+    .s_axis_chdr_tlast  (xb_to_ep5_tlast  ),
+    .s_axis_chdr_tvalid (xb_to_ep5_tvalid ),
+    .s_axis_chdr_tready (xb_to_ep5_tready ),
+    .m_axis_chdr_tdata  (ep5_to_xb_tdata  ),
+    .m_axis_chdr_tlast  (ep5_to_xb_tlast  ),
+    .m_axis_chdr_tvalid (ep5_to_xb_tvalid ),
+    .m_axis_chdr_tready (ep5_to_xb_tready ),
+    .s_axis_data_tdata  ({s_ep5_in0_tdata}),
+    .s_axis_data_tlast  ({s_ep5_in0_tlast}),
+    .s_axis_data_tvalid ({s_ep5_in0_tvalid}),
+    .s_axis_data_tready ({s_ep5_in0_tready}),
+    .m_axis_data_tdata  ({m_ep5_out0_tdata}),
+    .m_axis_data_tlast  ({m_ep5_out0_tlast}),
+    .m_axis_data_tvalid ({m_ep5_out0_tvalid}),
+    .m_axis_data_tready ({m_ep5_out0_tready}),
+    .s_axis_ctrl_tdata  (s_ep5_ctrl_tdata ),
+    .s_axis_ctrl_tlast  (s_ep5_ctrl_tlast ),
+    .s_axis_ctrl_tvalid (s_ep5_ctrl_tvalid),
+    .s_axis_ctrl_tready (s_ep5_ctrl_tready),
+    .m_axis_ctrl_tdata  (m_ep5_ctrl_tdata ),
+    .m_axis_ctrl_tlast  (m_ep5_ctrl_tlast ),
+    .m_axis_ctrl_tvalid (m_ep5_ctrl_tvalid),
+    .m_axis_ctrl_tready (m_ep5_ctrl_tready),
+    .strm_seq_err_stb   (                  ),
+    .strm_data_err_stb  (                  ),
+    .strm_route_err_stb (                  ),
+    .signal_data_err    (1'b0              )
+  );
+
 
 
   // ----------------------------------------------------
@@ -491,10 +629,14 @@ module rfnoc_image_core #(
   wire              m_radio1_ctrl_tlast ,   s_radio1_ctrl_tlast ;
   wire              m_radio1_ctrl_tvalid,   s_radio1_ctrl_tvalid;
   wire              m_radio1_ctrl_tready,   s_radio1_ctrl_tready;
+  wire [31:0]       m_replay0_ctrl_tdata ,   s_replay0_ctrl_tdata ;
+  wire              m_replay0_ctrl_tlast ,   s_replay0_ctrl_tlast ;
+  wire              m_replay0_ctrl_tvalid,   s_replay0_ctrl_tvalid;
+  wire              m_replay0_ctrl_tready,   s_replay0_ctrl_tready;
 
   axis_ctrl_crossbar_nxn #(
     .WIDTH            (32),
-    .NPORTS           (8),
+    .NPORTS           (9),
     .TOPOLOGY         ("TORUS"),
     .INGRESS_BUFF_SIZE(5),
     .ROUTER_BUFF_SIZE (5),
@@ -503,32 +645,32 @@ module rfnoc_image_core #(
   ) ctrl_xb_i (
     .clk              (rfnoc_ctrl_clk),
     .reset            (rfnoc_ctrl_rst),
-    .s_axis_tdata     ({m_radio1_ctrl_tdata , m_ddc1_ctrl_tdata , m_duc1_ctrl_tdata , m_radio0_ctrl_tdata , m_ddc0_ctrl_tdata , m_duc0_ctrl_tdata , m_ep0_ctrl_tdata , m_core_ctrl_tdata }),
-    .s_axis_tvalid    ({m_radio1_ctrl_tvalid, m_ddc1_ctrl_tvalid, m_duc1_ctrl_tvalid, m_radio0_ctrl_tvalid, m_ddc0_ctrl_tvalid, m_duc0_ctrl_tvalid, m_ep0_ctrl_tvalid, m_core_ctrl_tvalid}),
-    .s_axis_tlast     ({m_radio1_ctrl_tlast , m_ddc1_ctrl_tlast , m_duc1_ctrl_tlast , m_radio0_ctrl_tlast , m_ddc0_ctrl_tlast , m_duc0_ctrl_tlast , m_ep0_ctrl_tlast , m_core_ctrl_tlast }),
-    .s_axis_tready    ({m_radio1_ctrl_tready, m_ddc1_ctrl_tready, m_duc1_ctrl_tready, m_radio0_ctrl_tready, m_ddc0_ctrl_tready, m_duc0_ctrl_tready, m_ep0_ctrl_tready, m_core_ctrl_tready}),
-    .m_axis_tdata     ({s_radio1_ctrl_tdata , s_ddc1_ctrl_tdata , s_duc1_ctrl_tdata , s_radio0_ctrl_tdata , s_ddc0_ctrl_tdata , s_duc0_ctrl_tdata , s_ep0_ctrl_tdata , s_core_ctrl_tdata }),
-    .m_axis_tvalid    ({s_radio1_ctrl_tvalid, s_ddc1_ctrl_tvalid, s_duc1_ctrl_tvalid, s_radio0_ctrl_tvalid, s_ddc0_ctrl_tvalid, s_duc0_ctrl_tvalid, s_ep0_ctrl_tvalid, s_core_ctrl_tvalid}),
-    .m_axis_tlast     ({s_radio1_ctrl_tlast , s_ddc1_ctrl_tlast , s_duc1_ctrl_tlast , s_radio0_ctrl_tlast , s_ddc0_ctrl_tlast , s_duc0_ctrl_tlast , s_ep0_ctrl_tlast , s_core_ctrl_tlast }),
-    .m_axis_tready    ({s_radio1_ctrl_tready, s_ddc1_ctrl_tready, s_duc1_ctrl_tready, s_radio0_ctrl_tready, s_ddc0_ctrl_tready, s_duc0_ctrl_tready, s_ep0_ctrl_tready, s_core_ctrl_tready}),
+    .s_axis_tdata     ({m_replay0_ctrl_tdata , m_radio1_ctrl_tdata , m_ddc1_ctrl_tdata , m_duc1_ctrl_tdata , m_radio0_ctrl_tdata , m_ddc0_ctrl_tdata , m_duc0_ctrl_tdata , m_ep0_ctrl_tdata , m_core_ctrl_tdata }),
+    .s_axis_tvalid    ({m_replay0_ctrl_tvalid, m_radio1_ctrl_tvalid, m_ddc1_ctrl_tvalid, m_duc1_ctrl_tvalid, m_radio0_ctrl_tvalid, m_ddc0_ctrl_tvalid, m_duc0_ctrl_tvalid, m_ep0_ctrl_tvalid, m_core_ctrl_tvalid}),
+    .s_axis_tlast     ({m_replay0_ctrl_tlast , m_radio1_ctrl_tlast , m_ddc1_ctrl_tlast , m_duc1_ctrl_tlast , m_radio0_ctrl_tlast , m_ddc0_ctrl_tlast , m_duc0_ctrl_tlast , m_ep0_ctrl_tlast , m_core_ctrl_tlast }),
+    .s_axis_tready    ({m_replay0_ctrl_tready, m_radio1_ctrl_tready, m_ddc1_ctrl_tready, m_duc1_ctrl_tready, m_radio0_ctrl_tready, m_ddc0_ctrl_tready, m_duc0_ctrl_tready, m_ep0_ctrl_tready, m_core_ctrl_tready}),
+    .m_axis_tdata     ({s_replay0_ctrl_tdata , s_radio1_ctrl_tdata , s_ddc1_ctrl_tdata , s_duc1_ctrl_tdata , s_radio0_ctrl_tdata , s_ddc0_ctrl_tdata , s_duc0_ctrl_tdata , s_ep0_ctrl_tdata , s_core_ctrl_tdata }),
+    .m_axis_tvalid    ({s_replay0_ctrl_tvalid, s_radio1_ctrl_tvalid, s_ddc1_ctrl_tvalid, s_duc1_ctrl_tvalid, s_radio0_ctrl_tvalid, s_ddc0_ctrl_tvalid, s_duc0_ctrl_tvalid, s_ep0_ctrl_tvalid, s_core_ctrl_tvalid}),
+    .m_axis_tlast     ({s_replay0_ctrl_tlast , s_radio1_ctrl_tlast , s_ddc1_ctrl_tlast , s_duc1_ctrl_tlast , s_radio0_ctrl_tlast , s_ddc0_ctrl_tlast , s_duc0_ctrl_tlast , s_ep0_ctrl_tlast , s_core_ctrl_tlast }),
+    .m_axis_tready    ({s_replay0_ctrl_tready, s_radio1_ctrl_tready, s_ddc1_ctrl_tready, s_duc1_ctrl_tready, s_radio0_ctrl_tready, s_ddc0_ctrl_tready, s_duc0_ctrl_tready, s_ep0_ctrl_tready, s_core_ctrl_tready}),
     .deadlock_detected()
   );
 
   // ----------------------------------------------------
   // RFNoC Core Kernel
   // ----------------------------------------------------
-  wire [(512*6)-1:0] rfnoc_core_config, rfnoc_core_status;
+  wire [(512*7)-1:0] rfnoc_core_config, rfnoc_core_status;
 
   rfnoc_core_kernel #(
     .PROTOVER            (PROTOVER),
     .DEVICE_TYPE         (16'hA300),
     .DEVICE_FAMILY       ("7SERIES"),
     .SAFE_START_CLKS     (0),
-    .NUM_BLOCKS          (6),
-    .NUM_STREAM_ENDPOINTS(4),
+    .NUM_BLOCKS          (7),
+    .NUM_STREAM_ENDPOINTS(6),
     .NUM_ENDPOINTS_CTRL  (1),
     .NUM_TRANSPORTS      (3),
-    .NUM_EDGES           (12),
+    .NUM_EDGES           (16),
     .CHDR_XBAR_PRESENT   (1),
     .EDGE_TBL_FILE       (EDGE_TBL_FILE)
   ) core_kernel_i (
@@ -917,6 +1059,145 @@ module rfnoc_image_core #(
 
 
   // ----------------------------------------------------
+  // replay0
+  // ----------------------------------------------------
+  wire              replay0_mem_clk;
+  wire [CHDR_W-1:0] s_replay0_in_1_tdata , s_replay0_in_0_tdata ;
+  wire              s_replay0_in_1_tlast , s_replay0_in_0_tlast ;
+  wire              s_replay0_in_1_tvalid, s_replay0_in_0_tvalid;
+  wire              s_replay0_in_1_tready, s_replay0_in_0_tready;
+  wire [CHDR_W-1:0] m_replay0_out_1_tdata , m_replay0_out_0_tdata ;
+  wire              m_replay0_out_1_tlast , m_replay0_out_0_tlast ;
+  wire              m_replay0_out_1_tvalid, m_replay0_out_0_tvalid;
+  wire              m_replay0_out_1_tready, m_replay0_out_0_tready;
+
+  //  axi_ram
+  wire [  1-1:0] replay0_axi_rst;
+  wire [  4-1:0] replay0_m_axi_awid;
+  wire [128-1:0] replay0_m_axi_awaddr;
+  wire [ 32-1:0] replay0_m_axi_awlen;
+  wire [ 12-1:0] replay0_m_axi_awsize;
+  wire [  8-1:0] replay0_m_axi_awburst;
+  wire [  4-1:0] replay0_m_axi_awlock;
+  wire [ 16-1:0] replay0_m_axi_awcache;
+  wire [ 12-1:0] replay0_m_axi_awprot;
+  wire [ 16-1:0] replay0_m_axi_awqos;
+  wire [ 16-1:0] replay0_m_axi_awregion;
+  wire [  4-1:0] replay0_m_axi_awuser;
+  wire [  4-1:0] replay0_m_axi_awvalid;
+  wire [  4-1:0] replay0_m_axi_awready;
+  wire [256-1:0] replay0_m_axi_wdata;
+  wire [ 32-1:0] replay0_m_axi_wstrb;
+  wire [  4-1:0] replay0_m_axi_wlast;
+  wire [  4-1:0] replay0_m_axi_wuser;
+  wire [  4-1:0] replay0_m_axi_wvalid;
+  wire [  4-1:0] replay0_m_axi_wready;
+  wire [  4-1:0] replay0_m_axi_bid;
+  wire [  8-1:0] replay0_m_axi_bresp;
+  wire [  4-1:0] replay0_m_axi_buser;
+  wire [  4-1:0] replay0_m_axi_bvalid;
+  wire [  4-1:0] replay0_m_axi_bready;
+  wire [  4-1:0] replay0_m_axi_arid;
+  wire [128-1:0] replay0_m_axi_araddr;
+  wire [ 32-1:0] replay0_m_axi_arlen;
+  wire [ 12-1:0] replay0_m_axi_arsize;
+  wire [  8-1:0] replay0_m_axi_arburst;
+  wire [  4-1:0] replay0_m_axi_arlock;
+  wire [ 16-1:0] replay0_m_axi_arcache;
+  wire [ 12-1:0] replay0_m_axi_arprot;
+  wire [ 16-1:0] replay0_m_axi_arqos;
+  wire [ 16-1:0] replay0_m_axi_arregion;
+  wire [  4-1:0] replay0_m_axi_aruser;
+  wire [  4-1:0] replay0_m_axi_arvalid;
+  wire [  4-1:0] replay0_m_axi_arready;
+  wire [  4-1:0] replay0_m_axi_rid;
+  wire [256-1:0] replay0_m_axi_rdata;
+  wire [  8-1:0] replay0_m_axi_rresp;
+  wire [  4-1:0] replay0_m_axi_rlast;
+  wire [  4-1:0] replay0_m_axi_ruser;
+  wire [  4-1:0] replay0_m_axi_rvalid;
+  wire [  4-1:0] replay0_m_axi_rready;
+
+  rfnoc_block_replay #(
+    .THIS_PORTID(8),
+    .CHDR_W(CHDR_W),
+    .NUM_PORTS(2),
+    .MEM_ADDR_W(30),
+    .MEM_DATA_W(64),
+    .MTU(MTU)
+  ) b_replay0_6 (
+    .rfnoc_chdr_clk     (rfnoc_chdr_clk),
+    .rfnoc_ctrl_clk     (rfnoc_ctrl_clk),
+    .mem_clk(replay0_mem_clk),
+    .rfnoc_core_config  (rfnoc_core_config[512*7-1:512*6]),
+    .rfnoc_core_status  (rfnoc_core_status[512*7-1:512*6]),
+
+    .axi_rst(replay0_axi_rst),
+    .m_axi_awid(replay0_m_axi_awid),
+    .m_axi_awaddr(replay0_m_axi_awaddr),
+    .m_axi_awlen(replay0_m_axi_awlen),
+    .m_axi_awsize(replay0_m_axi_awsize),
+    .m_axi_awburst(replay0_m_axi_awburst),
+    .m_axi_awlock(replay0_m_axi_awlock),
+    .m_axi_awcache(replay0_m_axi_awcache),
+    .m_axi_awprot(replay0_m_axi_awprot),
+    .m_axi_awqos(replay0_m_axi_awqos),
+    .m_axi_awregion(replay0_m_axi_awregion),
+    .m_axi_awuser(replay0_m_axi_awuser),
+    .m_axi_awvalid(replay0_m_axi_awvalid),
+    .m_axi_awready(replay0_m_axi_awready),
+    .m_axi_wdata(replay0_m_axi_wdata),
+    .m_axi_wstrb(replay0_m_axi_wstrb),
+    .m_axi_wlast(replay0_m_axi_wlast),
+    .m_axi_wuser(replay0_m_axi_wuser),
+    .m_axi_wvalid(replay0_m_axi_wvalid),
+    .m_axi_wready(replay0_m_axi_wready),
+    .m_axi_bid(replay0_m_axi_bid),
+    .m_axi_bresp(replay0_m_axi_bresp),
+    .m_axi_buser(replay0_m_axi_buser),
+    .m_axi_bvalid(replay0_m_axi_bvalid),
+    .m_axi_bready(replay0_m_axi_bready),
+    .m_axi_arid(replay0_m_axi_arid),
+    .m_axi_araddr(replay0_m_axi_araddr),
+    .m_axi_arlen(replay0_m_axi_arlen),
+    .m_axi_arsize(replay0_m_axi_arsize),
+    .m_axi_arburst(replay0_m_axi_arburst),
+    .m_axi_arlock(replay0_m_axi_arlock),
+    .m_axi_arcache(replay0_m_axi_arcache),
+    .m_axi_arprot(replay0_m_axi_arprot),
+    .m_axi_arqos(replay0_m_axi_arqos),
+    .m_axi_arregion(replay0_m_axi_arregion),
+    .m_axi_aruser(replay0_m_axi_aruser),
+    .m_axi_arvalid(replay0_m_axi_arvalid),
+    .m_axi_arready(replay0_m_axi_arready),
+    .m_axi_rid(replay0_m_axi_rid),
+    .m_axi_rdata(replay0_m_axi_rdata),
+    .m_axi_rresp(replay0_m_axi_rresp),
+    .m_axi_rlast(replay0_m_axi_rlast),
+    .m_axi_ruser(replay0_m_axi_ruser),
+    .m_axi_rvalid(replay0_m_axi_rvalid),
+    .m_axi_rready(replay0_m_axi_rready),
+
+    .s_rfnoc_chdr_tdata ({s_replay0_in_1_tdata , s_replay0_in_0_tdata }),
+    .s_rfnoc_chdr_tlast ({s_replay0_in_1_tlast , s_replay0_in_0_tlast }),
+    .s_rfnoc_chdr_tvalid({s_replay0_in_1_tvalid, s_replay0_in_0_tvalid}),
+    .s_rfnoc_chdr_tready({s_replay0_in_1_tready, s_replay0_in_0_tready}),
+    .m_rfnoc_chdr_tdata ({m_replay0_out_1_tdata , m_replay0_out_0_tdata }),
+    .m_rfnoc_chdr_tlast ({m_replay0_out_1_tlast , m_replay0_out_0_tlast }),
+    .m_rfnoc_chdr_tvalid({m_replay0_out_1_tvalid, m_replay0_out_0_tvalid}),
+    .m_rfnoc_chdr_tready({m_replay0_out_1_tready, m_replay0_out_0_tready}),
+    .s_rfnoc_ctrl_tdata (s_replay0_ctrl_tdata ),
+    .s_rfnoc_ctrl_tlast (s_replay0_ctrl_tlast ),
+    .s_rfnoc_ctrl_tvalid(s_replay0_ctrl_tvalid),
+    .s_rfnoc_ctrl_tready(s_replay0_ctrl_tready),
+    .m_rfnoc_ctrl_tdata (m_replay0_ctrl_tdata ),
+    .m_rfnoc_ctrl_tlast (m_replay0_ctrl_tlast ),
+    .m_rfnoc_ctrl_tvalid(m_replay0_ctrl_tvalid),
+    .m_rfnoc_ctrl_tready(m_replay0_ctrl_tready)
+  );
+
+
+  // ----------------------------------------------------
   // Static Router
   // ----------------------------------------------------
   assign s_duc0_in_0_tdata = m_ep0_out0_tdata ;
@@ -979,6 +1260,26 @@ module rfnoc_image_core #(
   assign s_ep3_in0_tvalid = m_ddc1_out_1_tvalid;
   assign m_ddc1_out_1_tready = s_ep3_in0_tready;
 
+  assign s_replay0_in_0_tdata = m_ep4_out0_tdata ;
+  assign s_replay0_in_0_tlast = m_ep4_out0_tlast ;
+  assign s_replay0_in_0_tvalid = m_ep4_out0_tvalid;
+  assign m_ep4_out0_tready = s_replay0_in_0_tready;
+
+  assign s_ep4_in0_tdata = m_replay0_out_0_tdata ;
+  assign s_ep4_in0_tlast = m_replay0_out_0_tlast ;
+  assign s_ep4_in0_tvalid = m_replay0_out_0_tvalid;
+  assign m_replay0_out_0_tready = s_ep4_in0_tready;
+
+  assign s_replay0_in_1_tdata = m_ep5_out0_tdata ;
+  assign s_replay0_in_1_tlast = m_ep5_out0_tlast ;
+  assign s_replay0_in_1_tvalid = m_ep5_out0_tvalid;
+  assign m_ep5_out0_tready = s_replay0_in_1_tready;
+
+  assign s_ep5_in0_tdata = m_replay0_out_1_tdata ;
+  assign s_ep5_in0_tlast = m_replay0_out_1_tlast ;
+  assign s_ep5_in0_tvalid = m_replay0_out_1_tvalid;
+  assign m_replay0_out_1_tready = s_ep5_in0_tready;
+
 
   // ----------------------------------------------------
   // Unused Ports
@@ -1001,6 +1302,7 @@ module rfnoc_image_core #(
   assign radio1_radio_clk = radio_clk;
   assign ddc1_ce_clk = ce_clk;
   assign duc1_ce_clk = ce_clk;
+  assign replay0_mem_clk = dram_clk;
 
 
   // ----------------------------------------------------
@@ -1029,6 +1331,52 @@ module rfnoc_image_core #(
   assign radio1_m_ctrlport_resp_status = m_ctrlport_radio1_resp_status;
   assign radio1_m_ctrlport_resp_data = m_ctrlport_radio1_resp_data;
 
+  assign replay0_axi_rst = axi_rst;
+  assign m_axi_awid = replay0_m_axi_awid;
+  assign m_axi_awaddr = replay0_m_axi_awaddr;
+  assign m_axi_awlen = replay0_m_axi_awlen;
+  assign m_axi_awsize = replay0_m_axi_awsize;
+  assign m_axi_awburst = replay0_m_axi_awburst;
+  assign m_axi_awlock = replay0_m_axi_awlock;
+  assign m_axi_awcache = replay0_m_axi_awcache;
+  assign m_axi_awprot = replay0_m_axi_awprot;
+  assign m_axi_awqos = replay0_m_axi_awqos;
+  assign m_axi_awregion = replay0_m_axi_awregion;
+  assign m_axi_awuser = replay0_m_axi_awuser;
+  assign m_axi_awvalid = replay0_m_axi_awvalid;
+  assign replay0_m_axi_awready = m_axi_awready;
+  assign m_axi_wdata = replay0_m_axi_wdata;
+  assign m_axi_wstrb = replay0_m_axi_wstrb;
+  assign m_axi_wlast = replay0_m_axi_wlast;
+  assign m_axi_wuser = replay0_m_axi_wuser;
+  assign m_axi_wvalid = replay0_m_axi_wvalid;
+  assign replay0_m_axi_wready = m_axi_wready;
+  assign replay0_m_axi_bid = m_axi_bid;
+  assign replay0_m_axi_bresp = m_axi_bresp;
+  assign replay0_m_axi_buser = m_axi_buser;
+  assign replay0_m_axi_bvalid = m_axi_bvalid;
+  assign m_axi_bready = replay0_m_axi_bready;
+  assign m_axi_arid = replay0_m_axi_arid;
+  assign m_axi_araddr = replay0_m_axi_araddr;
+  assign m_axi_arlen = replay0_m_axi_arlen;
+  assign m_axi_arsize = replay0_m_axi_arsize;
+  assign m_axi_arburst = replay0_m_axi_arburst;
+  assign m_axi_arlock = replay0_m_axi_arlock;
+  assign m_axi_arcache = replay0_m_axi_arcache;
+  assign m_axi_arprot = replay0_m_axi_arprot;
+  assign m_axi_arqos = replay0_m_axi_arqos;
+  assign m_axi_arregion = replay0_m_axi_arregion;
+  assign m_axi_aruser = replay0_m_axi_aruser;
+  assign m_axi_arvalid = replay0_m_axi_arvalid;
+  assign replay0_m_axi_arready = m_axi_arready;
+  assign replay0_m_axi_rid = m_axi_rid;
+  assign replay0_m_axi_rdata = m_axi_rdata;
+  assign replay0_m_axi_rresp = m_axi_rresp;
+  assign replay0_m_axi_rlast = m_axi_rlast;
+  assign replay0_m_axi_ruser = m_axi_ruser;
+  assign replay0_m_axi_rvalid = m_axi_rvalid;
+  assign m_axi_rready = replay0_m_axi_rready;
+
   assign radio0_radio_rx_data = radio_rx_data_radio0;
   assign radio0_radio_rx_stb = radio_rx_stb_radio0;
   assign radio_rx_running_radio0 = radio0_radio_rx_running;
diff --git a/fpga/usrp3/top/x300/x300_rfnoc_image_core.yml b/fpga/usrp3/top/x300/x300_rfnoc_image_core.yml
index 08a8e82c2..d9570b8ef 100644
--- a/fpga/usrp3/top/x300/x300_rfnoc_image_core.yml
+++ b/fpga/usrp3/top/x300/x300_rfnoc_image_core.yml
@@ -28,6 +28,14 @@ stream_endpoints:
     ctrl: False                     # Endpoint passes control traffic
     data: True                      # Endpoint passes data traffic
     buff_size: 0                    # Ingress buffer size for data
+  ep4:                       # Stream endpoint name
+    ctrl: False                     # Endpoint passes control traffic
+    data: True                      # Endpoint passes data traffic
+    buff_size: 4096                 # Ingress buffer size for data
+  ep5:                       # Stream endpoint name
+    ctrl: False                     # Endpoint passes control traffic
+    data: True                      # Endpoint passes data traffic
+    buff_size: 4096                 # Ingress buffer size for data
 
 # A list of all NoC blocks in design
 # ----------------------------------
@@ -52,6 +60,11 @@ noc_blocks:
       NUM_PORTS: 2
   radio1:
     block_desc: 'radio_2x64.yml'
+  replay0:
+    block_desc: 'replay.yml'
+    parameters:
+      NUM_PORTS: 2
+      MEM_ADDR_W: 30
 
 # A list of all static connections in design
 # ------------------------------------------
@@ -79,9 +92,18 @@ connections:
   # radio0(1) to ep3 - RFA RX
   - { srcblk: radio1, srcport: out_1, dstblk: ddc1,   dstport: in_1 }
   - { srcblk: ddc1,   srcport: out_1, dstblk: ep3,    dstport: in0  }
+  # ep4 to replay0(0)
+  - { srcblk: ep4,     srcport: out0,  dstblk: replay0, dstport: in_0 }
+  # replay0(0) to ep4
+  - { srcblk: replay0, srcport: out_0, dstblk: ep4,     dstport: in0  }
+  # ep5 to replay0(1)
+  - { srcblk: ep5,     srcport: out0,  dstblk: replay0, dstport: in_1 }
+  # replay0(1) to ep5
+  - { srcblk: replay0, srcport: out_1, dstblk: ep5,     dstport: in0  }
   # BSP Connections
   - { srcblk: radio0, srcport: ctrl_port, dstblk: _device_, dstport: ctrlport_radio0 }
   - { srcblk: radio1, srcport: ctrl_port, dstblk: _device_, dstport: ctrlport_radio1 }
+  - { srcblk: replay0, srcport: axi_ram, dstblk: _device_, dstport: dram }
   - { srcblk: _device_, srcport: x300_radio0, dstblk: radio0, dstport: x300_radio }
   - { srcblk: _device_, srcport: x300_radio1, dstblk: radio1, dstport: x300_radio }
   - { srcblk: _device_, srcport: time_keeper, dstblk: radio0, dstport: time_keeper }
@@ -101,3 +123,4 @@ clk_domains:
   - { srcblk: _device_, srcport: radio, dstblk: radio1, dstport: radio }
   - { srcblk: _device_, srcport: ce,    dstblk: ddc1,   dstport: ce    }
   - { srcblk: _device_, srcport: ce,    dstblk: duc1,   dstport: ce    }
+  - { srcblk: _device_, srcport: dram,  dstblk: replay0, dstport: mem  }
diff --git a/fpga/usrp3/top/x300/x300_static_router.hex b/fpga/usrp3/top/x300/x300_static_router.hex
index 53635706f..eb493cee8 100644
--- a/fpga/usrp3/top/x300/x300_static_router.hex
+++ b/fpga/usrp3/top/x300/x300_static_router.hex
@@ -1,13 +1,17 @@
-0000000C
-00400140
-014001c0
-01c00180
-01800040
-01c10181
-01810080
-00c00200
-02000280
-02800240
-024000c0
-02810241
-02410100
+00000010
+004001c0
+01c00240
+02400200
+02000040
+02410201
+02010080
+00c00280
+02800300
+030002c0
+02c000c0
+030102c1
+02c10100
+01400340
+03400140
+01800341
+03410180
diff --git a/fpga/usrp3/top/x300/x310_rfnoc_image_core.v b/fpga/usrp3/top/x300/x310_rfnoc_image_core.v
index 73124f119..4dc38bd11 100644
--- a/fpga/usrp3/top/x300/x310_rfnoc_image_core.v
+++ b/fpga/usrp3/top/x300/x310_rfnoc_image_core.v
@@ -1,5 +1,5 @@
 //
-// Copyright 2019 Ettus Research, A National Instruments Brand
+// Copyright 2020 Ettus Research, A National Instruments Brand
 //
 // SPDX-License-Identifier: LGPL-3.0-or-later
 //
@@ -7,9 +7,9 @@
 // Module: rfnoc_image_core (for x300)
 // This file was autogenerated by UHD's image builder tool (rfnoc_image_builder)
 // Re-running that tool will overwrite this file!
-// File generated on: 2019-11-14T12:14:56.022475
+// File generated on: 2020-09-02T12:02:33.545638
 // Source: ./x310_rfnoc_image_core.yml
-// Source SHA256: 41b259b31e2a09272ffb146ef99afe1672a44c86dd51104fa4d1821ad24d5518
+// Source SHA256: acc39ec2e56ad0a5dd482a8db6b4dbb7e9790c03074d7461a38e0b5356456a83
 
 module rfnoc_image_core #(
   parameter [15:0] PROTOVER = {8'd1, 8'd0}
@@ -64,50 +64,50 @@ module rfnoc_image_core #(
   output wire [  2-1:0] radio_tx_running_radio1,
 //  dram
   input  wire [  1-1:0] axi_rst,
-  output wire [  2-1:0] m_axi_awid,
-  output wire [ 64-1:0] m_axi_awaddr,
-  output wire [ 16-1:0] m_axi_awlen,
-  output wire [  6-1:0] m_axi_awsize,
-  output wire [  4-1:0] m_axi_awburst,
-  output wire [  2-1:0] m_axi_awlock,
-  output wire [  8-1:0] m_axi_awcache,
-  output wire [  6-1:0] m_axi_awprot,
-  output wire [  8-1:0] m_axi_awqos,
-  output wire [  8-1:0] m_axi_awregion,
-  output wire [  2-1:0] m_axi_awuser,
-  output wire [  2-1:0] m_axi_awvalid,
-  input  wire [  2-1:0] m_axi_awready,
-  output wire [128-1:0] m_axi_wdata,
-  output wire [ 16-1:0] m_axi_wstrb,
-  output wire [  2-1:0] m_axi_wlast,
-  output wire [  2-1:0] m_axi_wuser,
-  output wire [  2-1:0] m_axi_wvalid,
-  input  wire [  2-1:0] m_axi_wready,
-  input  wire [  2-1:0] m_axi_bid,
-  input  wire [  4-1:0] m_axi_bresp,
-  input  wire [  2-1:0] m_axi_buser,
-  input  wire [  2-1:0] m_axi_bvalid,
-  output wire [  2-1:0] m_axi_bready,
-  output wire [  2-1:0] m_axi_arid,
-  output wire [ 64-1:0] m_axi_araddr,
-  output wire [ 16-1:0] m_axi_arlen,
-  output wire [  6-1:0] m_axi_arsize,
-  output wire [  4-1:0] m_axi_arburst,
-  output wire [  2-1:0] m_axi_arlock,
-  output wire [  8-1:0] m_axi_arcache,
-  output wire [  6-1:0] m_axi_arprot,
-  output wire [  8-1:0] m_axi_arqos,
-  output wire [  8-1:0] m_axi_arregion,
-  output wire [  2-1:0] m_axi_aruser,
-  output wire [  2-1:0] m_axi_arvalid,
-  input  wire [  2-1:0] m_axi_arready,
-  input  wire [  2-1:0] m_axi_rid,
-  input  wire [128-1:0] m_axi_rdata,
-  input  wire [  4-1:0] m_axi_rresp,
-  input  wire [  2-1:0] m_axi_rlast,
-  input  wire [  2-1:0] m_axi_ruser,
-  input  wire [  2-1:0] m_axi_rvalid,
-  output wire [  2-1:0] m_axi_rready,
+  output wire [  4-1:0] m_axi_awid,
+  output wire [128-1:0] m_axi_awaddr,
+  output wire [ 32-1:0] m_axi_awlen,
+  output wire [ 12-1:0] m_axi_awsize,
+  output wire [  8-1:0] m_axi_awburst,
+  output wire [  4-1:0] m_axi_awlock,
+  output wire [ 16-1:0] m_axi_awcache,
+  output wire [ 12-1:0] m_axi_awprot,
+  output wire [ 16-1:0] m_axi_awqos,
+  output wire [ 16-1:0] m_axi_awregion,
+  output wire [  4-1:0] m_axi_awuser,
+  output wire [  4-1:0] m_axi_awvalid,
+  input  wire [  4-1:0] m_axi_awready,
+  output wire [256-1:0] m_axi_wdata,
+  output wire [ 32-1:0] m_axi_wstrb,
+  output wire [  4-1:0] m_axi_wlast,
+  output wire [  4-1:0] m_axi_wuser,
+  output wire [  4-1:0] m_axi_wvalid,
+  input  wire [  4-1:0] m_axi_wready,
+  input  wire [  4-1:0] m_axi_bid,
+  input  wire [  8-1:0] m_axi_bresp,
+  input  wire [  4-1:0] m_axi_buser,
+  input  wire [  4-1:0] m_axi_bvalid,
+  output wire [  4-1:0] m_axi_bready,
+  output wire [  4-1:0] m_axi_arid,
+  output wire [128-1:0] m_axi_araddr,
+  output wire [ 32-1:0] m_axi_arlen,
+  output wire [ 12-1:0] m_axi_arsize,
+  output wire [  8-1:0] m_axi_arburst,
+  output wire [  4-1:0] m_axi_arlock,
+  output wire [ 16-1:0] m_axi_arcache,
+  output wire [ 12-1:0] m_axi_arprot,
+  output wire [ 16-1:0] m_axi_arqos,
+  output wire [ 16-1:0] m_axi_arregion,
+  output wire [  4-1:0] m_axi_aruser,
+  output wire [  4-1:0] m_axi_arvalid,
+  input  wire [  4-1:0] m_axi_arready,
+  input  wire [  4-1:0] m_axi_rid,
+  input  wire [256-1:0] m_axi_rdata,
+  input  wire [  8-1:0] m_axi_rresp,
+  input  wire [  4-1:0] m_axi_rlast,
+  input  wire [  4-1:0] m_axi_ruser,
+  input  wire [  4-1:0] m_axi_rvalid,
+  output wire [  4-1:0] m_axi_rready,
   // Transport 0 (eth0 10G)
   input  wire [64-1:0]  s_eth0_tdata,
   input  wire         s_eth0_tlast,
@@ -179,10 +179,26 @@ module rfnoc_image_core #(
   wire              ep3_to_xb_tlast ;
   wire              ep3_to_xb_tvalid;
   wire              ep3_to_xb_tready;
+  wire [CHDR_W-1:0] xb_to_ep4_tdata ;
+  wire              xb_to_ep4_tlast ;
+  wire              xb_to_ep4_tvalid;
+  wire              xb_to_ep4_tready;
+  wire [CHDR_W-1:0] ep4_to_xb_tdata ;
+  wire              ep4_to_xb_tlast ;
+  wire              ep4_to_xb_tvalid;
+  wire              ep4_to_xb_tready;
+  wire [CHDR_W-1:0] xb_to_ep5_tdata ;
+  wire              xb_to_ep5_tlast ;
+  wire              xb_to_ep5_tvalid;
+  wire              xb_to_ep5_tready;
+  wire [CHDR_W-1:0] ep5_to_xb_tdata ;
+  wire              ep5_to_xb_tlast ;
+  wire              ep5_to_xb_tvalid;
+  wire              ep5_to_xb_tready;
 
   chdr_crossbar_nxn #(
     .CHDR_W         (CHDR_W),
-    .NPORTS         (7),
+    .NPORTS         (9),
     .DEFAULT_PORT   (0),
     .MTU            (MTU),
     .ROUTE_TBL_SIZE (6),
@@ -195,14 +211,14 @@ module rfnoc_image_core #(
     .clk            (rfnoc_chdr_clk),
     .reset          (rfnoc_chdr_rst),
     .device_id      (device_id),
-    .s_axis_tdata   ({ep3_to_xb_tdata, ep2_to_xb_tdata, ep1_to_xb_tdata, ep0_to_xb_tdata, s_pcie_tdata, s_eth1_tdata, s_eth0_tdata}),
-    .s_axis_tlast   ({ep3_to_xb_tlast, ep2_to_xb_tlast, ep1_to_xb_tlast, ep0_to_xb_tlast, s_pcie_tlast, s_eth1_tlast, s_eth0_tlast}),
-    .s_axis_tvalid  ({ep3_to_xb_tvalid, ep2_to_xb_tvalid, ep1_to_xb_tvalid, ep0_to_xb_tvalid, s_pcie_tvalid, s_eth1_tvalid, s_eth0_tvalid}),
-    .s_axis_tready  ({ep3_to_xb_tready, ep2_to_xb_tready, ep1_to_xb_tready, ep0_to_xb_tready, s_pcie_tready, s_eth1_tready, s_eth0_tready}),
-    .m_axis_tdata   ({xb_to_ep3_tdata, xb_to_ep2_tdata, xb_to_ep1_tdata, xb_to_ep0_tdata, m_pcie_tdata, m_eth1_tdata, m_eth0_tdata}),
-    .m_axis_tlast   ({xb_to_ep3_tlast, xb_to_ep2_tlast, xb_to_ep1_tlast, xb_to_ep0_tlast, m_pcie_tlast, m_eth1_tlast, m_eth0_tlast}),
-    .m_axis_tvalid  ({xb_to_ep3_tvalid, xb_to_ep2_tvalid, xb_to_ep1_tvalid, xb_to_ep0_tvalid, m_pcie_tvalid, m_eth1_tvalid, m_eth0_tvalid}),
-    .m_axis_tready  ({xb_to_ep3_tready, xb_to_ep2_tready, xb_to_ep1_tready, xb_to_ep0_tready, m_pcie_tready, m_eth1_tready, m_eth0_tready}),
+    .s_axis_tdata   ({ep5_to_xb_tdata, ep4_to_xb_tdata, ep3_to_xb_tdata, ep2_to_xb_tdata, ep1_to_xb_tdata, ep0_to_xb_tdata, s_pcie_tdata, s_eth1_tdata, s_eth0_tdata}),
+    .s_axis_tlast   ({ep5_to_xb_tlast, ep4_to_xb_tlast, ep3_to_xb_tlast, ep2_to_xb_tlast, ep1_to_xb_tlast, ep0_to_xb_tlast, s_pcie_tlast, s_eth1_tlast, s_eth0_tlast}),
+    .s_axis_tvalid  ({ep5_to_xb_tvalid, ep4_to_xb_tvalid, ep3_to_xb_tvalid, ep2_to_xb_tvalid, ep1_to_xb_tvalid, ep0_to_xb_tvalid, s_pcie_tvalid, s_eth1_tvalid, s_eth0_tvalid}),
+    .s_axis_tready  ({ep5_to_xb_tready, ep4_to_xb_tready, ep3_to_xb_tready, ep2_to_xb_tready, ep1_to_xb_tready, ep0_to_xb_tready, s_pcie_tready, s_eth1_tready, s_eth0_tready}),
+    .m_axis_tdata   ({xb_to_ep5_tdata, xb_to_ep4_tdata, xb_to_ep3_tdata, xb_to_ep2_tdata, xb_to_ep1_tdata, xb_to_ep0_tdata, m_pcie_tdata, m_eth1_tdata, m_eth0_tdata}),
+    .m_axis_tlast   ({xb_to_ep5_tlast, xb_to_ep4_tlast, xb_to_ep3_tlast, xb_to_ep2_tlast, xb_to_ep1_tlast, xb_to_ep0_tlast, m_pcie_tlast, m_eth1_tlast, m_eth0_tlast}),
+    .m_axis_tvalid  ({xb_to_ep5_tvalid, xb_to_ep4_tvalid, xb_to_ep3_tvalid, xb_to_ep2_tvalid, xb_to_ep1_tvalid, xb_to_ep0_tvalid, m_pcie_tvalid, m_eth1_tvalid, m_eth0_tvalid}),
+    .m_axis_tready  ({xb_to_ep5_tready, xb_to_ep4_tready, xb_to_ep3_tready, xb_to_ep2_tready, xb_to_ep1_tready, xb_to_ep0_tready, m_pcie_tready, m_eth1_tready, m_eth0_tready}),
     .ext_rtcfg_stb  (1'h0),
     .ext_rtcfg_addr (16'h0),
     .ext_rtcfg_data (32'h0),
@@ -457,6 +473,128 @@ module rfnoc_image_core #(
     .signal_data_err    (1'b0              )
   );
 
+  wire [CHDR_W-1:0] m_ep4_out0_tdata;
+  wire              m_ep4_out0_tlast;
+  wire              m_ep4_out0_tvalid;
+  wire              m_ep4_out0_tready;
+  wire [CHDR_W-1:0] s_ep4_in0_tdata;
+  wire              s_ep4_in0_tlast;
+  wire              s_ep4_in0_tvalid;
+  wire              s_ep4_in0_tready;
+  wire [31:0]       m_ep4_ctrl_tdata , s_ep4_ctrl_tdata ;
+  wire              m_ep4_ctrl_tlast , s_ep4_ctrl_tlast ;
+  wire              m_ep4_ctrl_tvalid, s_ep4_ctrl_tvalid;
+  wire              m_ep4_ctrl_tready, s_ep4_ctrl_tready;
+
+  chdr_stream_endpoint #(
+    .PROTOVER           (PROTOVER),
+    .CHDR_W             (CHDR_W),
+    .AXIS_CTRL_EN       (0),
+    .AXIS_DATA_EN       (1),
+    .NUM_DATA_I         (1),
+    .NUM_DATA_O         (1),
+    .INST_NUM           (4),
+    .CTRL_XBAR_PORT     (5),
+    .INGRESS_BUFF_SIZE  (12),
+    .MTU                (MTU),
+    .REPORT_STRM_ERRS   (1)
+  ) ep4_i (
+    .rfnoc_chdr_clk     (rfnoc_chdr_clk    ),
+    .rfnoc_chdr_rst     (rfnoc_chdr_rst    ),
+    .rfnoc_ctrl_clk     (rfnoc_ctrl_clk    ),
+    .rfnoc_ctrl_rst     (rfnoc_ctrl_rst    ),
+    .device_id          (device_id         ),
+    .s_axis_chdr_tdata  (xb_to_ep4_tdata  ),
+    .s_axis_chdr_tlast  (xb_to_ep4_tlast  ),
+    .s_axis_chdr_tvalid (xb_to_ep4_tvalid ),
+    .s_axis_chdr_tready (xb_to_ep4_tready ),
+    .m_axis_chdr_tdata  (ep4_to_xb_tdata  ),
+    .m_axis_chdr_tlast  (ep4_to_xb_tlast  ),
+    .m_axis_chdr_tvalid (ep4_to_xb_tvalid ),
+    .m_axis_chdr_tready (ep4_to_xb_tready ),
+    .s_axis_data_tdata  ({s_ep4_in0_tdata}),
+    .s_axis_data_tlast  ({s_ep4_in0_tlast}),
+    .s_axis_data_tvalid ({s_ep4_in0_tvalid}),
+    .s_axis_data_tready ({s_ep4_in0_tready}),
+    .m_axis_data_tdata  ({m_ep4_out0_tdata}),
+    .m_axis_data_tlast  ({m_ep4_out0_tlast}),
+    .m_axis_data_tvalid ({m_ep4_out0_tvalid}),
+    .m_axis_data_tready ({m_ep4_out0_tready}),
+    .s_axis_ctrl_tdata  (s_ep4_ctrl_tdata ),
+    .s_axis_ctrl_tlast  (s_ep4_ctrl_tlast ),
+    .s_axis_ctrl_tvalid (s_ep4_ctrl_tvalid),
+    .s_axis_ctrl_tready (s_ep4_ctrl_tready),
+    .m_axis_ctrl_tdata  (m_ep4_ctrl_tdata ),
+    .m_axis_ctrl_tlast  (m_ep4_ctrl_tlast ),
+    .m_axis_ctrl_tvalid (m_ep4_ctrl_tvalid),
+    .m_axis_ctrl_tready (m_ep4_ctrl_tready),
+    .strm_seq_err_stb   (                  ),
+    .strm_data_err_stb  (                  ),
+    .strm_route_err_stb (                  ),
+    .signal_data_err    (1'b0              )
+  );
+
+  wire [CHDR_W-1:0] m_ep5_out0_tdata;
+  wire              m_ep5_out0_tlast;
+  wire              m_ep5_out0_tvalid;
+  wire              m_ep5_out0_tready;
+  wire [CHDR_W-1:0] s_ep5_in0_tdata;
+  wire              s_ep5_in0_tlast;
+  wire              s_ep5_in0_tvalid;
+  wire              s_ep5_in0_tready;
+  wire [31:0]       m_ep5_ctrl_tdata , s_ep5_ctrl_tdata ;
+  wire              m_ep5_ctrl_tlast , s_ep5_ctrl_tlast ;
+  wire              m_ep5_ctrl_tvalid, s_ep5_ctrl_tvalid;
+  wire              m_ep5_ctrl_tready, s_ep5_ctrl_tready;
+
+  chdr_stream_endpoint #(
+    .PROTOVER           (PROTOVER),
+    .CHDR_W             (CHDR_W),
+    .AXIS_CTRL_EN       (0),
+    .AXIS_DATA_EN       (1),
+    .NUM_DATA_I         (1),
+    .NUM_DATA_O         (1),
+    .INST_NUM           (5),
+    .CTRL_XBAR_PORT     (6),
+    .INGRESS_BUFF_SIZE  (12),
+    .MTU                (MTU),
+    .REPORT_STRM_ERRS   (1)
+  ) ep5_i (
+    .rfnoc_chdr_clk     (rfnoc_chdr_clk    ),
+    .rfnoc_chdr_rst     (rfnoc_chdr_rst    ),
+    .rfnoc_ctrl_clk     (rfnoc_ctrl_clk    ),
+    .rfnoc_ctrl_rst     (rfnoc_ctrl_rst    ),
+    .device_id          (device_id         ),
+    .s_axis_chdr_tdata  (xb_to_ep5_tdata  ),
+    .s_axis_chdr_tlast  (xb_to_ep5_tlast  ),
+    .s_axis_chdr_tvalid (xb_to_ep5_tvalid ),
+    .s_axis_chdr_tready (xb_to_ep5_tready ),
+    .m_axis_chdr_tdata  (ep5_to_xb_tdata  ),
+    .m_axis_chdr_tlast  (ep5_to_xb_tlast  ),
+    .m_axis_chdr_tvalid (ep5_to_xb_tvalid ),
+    .m_axis_chdr_tready (ep5_to_xb_tready ),
+    .s_axis_data_tdata  ({s_ep5_in0_tdata}),
+    .s_axis_data_tlast  ({s_ep5_in0_tlast}),
+    .s_axis_data_tvalid ({s_ep5_in0_tvalid}),
+    .s_axis_data_tready ({s_ep5_in0_tready}),
+    .m_axis_data_tdata  ({m_ep5_out0_tdata}),
+    .m_axis_data_tlast  ({m_ep5_out0_tlast}),
+    .m_axis_data_tvalid ({m_ep5_out0_tvalid}),
+    .m_axis_data_tready ({m_ep5_out0_tready}),
+    .s_axis_ctrl_tdata  (s_ep5_ctrl_tdata ),
+    .s_axis_ctrl_tlast  (s_ep5_ctrl_tlast ),
+    .s_axis_ctrl_tvalid (s_ep5_ctrl_tvalid),
+    .s_axis_ctrl_tready (s_ep5_ctrl_tready),
+    .m_axis_ctrl_tdata  (m_ep5_ctrl_tdata ),
+    .m_axis_ctrl_tlast  (m_ep5_ctrl_tlast ),
+    .m_axis_ctrl_tvalid (m_ep5_ctrl_tvalid),
+    .m_axis_ctrl_tready (m_ep5_ctrl_tready),
+    .strm_seq_err_stb   (                  ),
+    .strm_data_err_stb  (                  ),
+    .strm_route_err_stb (                  ),
+    .signal_data_err    (1'b0              )
+  );
+
 
 
   // ----------------------------------------------------
@@ -491,10 +629,14 @@ module rfnoc_image_core #(
   wire              m_radio1_ctrl_tlast ,   s_radio1_ctrl_tlast ;
   wire              m_radio1_ctrl_tvalid,   s_radio1_ctrl_tvalid;
   wire              m_radio1_ctrl_tready,   s_radio1_ctrl_tready;
+  wire [31:0]       m_replay0_ctrl_tdata ,   s_replay0_ctrl_tdata ;
+  wire              m_replay0_ctrl_tlast ,   s_replay0_ctrl_tlast ;
+  wire              m_replay0_ctrl_tvalid,   s_replay0_ctrl_tvalid;
+  wire              m_replay0_ctrl_tready,   s_replay0_ctrl_tready;
 
   axis_ctrl_crossbar_nxn #(
     .WIDTH            (32),
-    .NPORTS           (8),
+    .NPORTS           (9),
     .TOPOLOGY         ("TORUS"),
     .INGRESS_BUFF_SIZE(5),
     .ROUTER_BUFF_SIZE (5),
@@ -503,32 +645,32 @@ module rfnoc_image_core #(
   ) ctrl_xb_i (
     .clk              (rfnoc_ctrl_clk),
     .reset            (rfnoc_ctrl_rst),
-    .s_axis_tdata     ({m_radio1_ctrl_tdata , m_ddc1_ctrl_tdata , m_duc1_ctrl_tdata , m_radio0_ctrl_tdata , m_ddc0_ctrl_tdata , m_duc0_ctrl_tdata , m_ep0_ctrl_tdata , m_core_ctrl_tdata }),
-    .s_axis_tvalid    ({m_radio1_ctrl_tvalid, m_ddc1_ctrl_tvalid, m_duc1_ctrl_tvalid, m_radio0_ctrl_tvalid, m_ddc0_ctrl_tvalid, m_duc0_ctrl_tvalid, m_ep0_ctrl_tvalid, m_core_ctrl_tvalid}),
-    .s_axis_tlast     ({m_radio1_ctrl_tlast , m_ddc1_ctrl_tlast , m_duc1_ctrl_tlast , m_radio0_ctrl_tlast , m_ddc0_ctrl_tlast , m_duc0_ctrl_tlast , m_ep0_ctrl_tlast , m_core_ctrl_tlast }),
-    .s_axis_tready    ({m_radio1_ctrl_tready, m_ddc1_ctrl_tready, m_duc1_ctrl_tready, m_radio0_ctrl_tready, m_ddc0_ctrl_tready, m_duc0_ctrl_tready, m_ep0_ctrl_tready, m_core_ctrl_tready}),
-    .m_axis_tdata     ({s_radio1_ctrl_tdata , s_ddc1_ctrl_tdata , s_duc1_ctrl_tdata , s_radio0_ctrl_tdata , s_ddc0_ctrl_tdata , s_duc0_ctrl_tdata , s_ep0_ctrl_tdata , s_core_ctrl_tdata }),
-    .m_axis_tvalid    ({s_radio1_ctrl_tvalid, s_ddc1_ctrl_tvalid, s_duc1_ctrl_tvalid, s_radio0_ctrl_tvalid, s_ddc0_ctrl_tvalid, s_duc0_ctrl_tvalid, s_ep0_ctrl_tvalid, s_core_ctrl_tvalid}),
-    .m_axis_tlast     ({s_radio1_ctrl_tlast , s_ddc1_ctrl_tlast , s_duc1_ctrl_tlast , s_radio0_ctrl_tlast , s_ddc0_ctrl_tlast , s_duc0_ctrl_tlast , s_ep0_ctrl_tlast , s_core_ctrl_tlast }),
-    .m_axis_tready    ({s_radio1_ctrl_tready, s_ddc1_ctrl_tready, s_duc1_ctrl_tready, s_radio0_ctrl_tready, s_ddc0_ctrl_tready, s_duc0_ctrl_tready, s_ep0_ctrl_tready, s_core_ctrl_tready}),
+    .s_axis_tdata     ({m_replay0_ctrl_tdata , m_radio1_ctrl_tdata , m_ddc1_ctrl_tdata , m_duc1_ctrl_tdata , m_radio0_ctrl_tdata , m_ddc0_ctrl_tdata , m_duc0_ctrl_tdata , m_ep0_ctrl_tdata , m_core_ctrl_tdata }),
+    .s_axis_tvalid    ({m_replay0_ctrl_tvalid, m_radio1_ctrl_tvalid, m_ddc1_ctrl_tvalid, m_duc1_ctrl_tvalid, m_radio0_ctrl_tvalid, m_ddc0_ctrl_tvalid, m_duc0_ctrl_tvalid, m_ep0_ctrl_tvalid, m_core_ctrl_tvalid}),
+    .s_axis_tlast     ({m_replay0_ctrl_tlast , m_radio1_ctrl_tlast , m_ddc1_ctrl_tlast , m_duc1_ctrl_tlast , m_radio0_ctrl_tlast , m_ddc0_ctrl_tlast , m_duc0_ctrl_tlast , m_ep0_ctrl_tlast , m_core_ctrl_tlast }),
+    .s_axis_tready    ({m_replay0_ctrl_tready, m_radio1_ctrl_tready, m_ddc1_ctrl_tready, m_duc1_ctrl_tready, m_radio0_ctrl_tready, m_ddc0_ctrl_tready, m_duc0_ctrl_tready, m_ep0_ctrl_tready, m_core_ctrl_tready}),
+    .m_axis_tdata     ({s_replay0_ctrl_tdata , s_radio1_ctrl_tdata , s_ddc1_ctrl_tdata , s_duc1_ctrl_tdata , s_radio0_ctrl_tdata , s_ddc0_ctrl_tdata , s_duc0_ctrl_tdata , s_ep0_ctrl_tdata , s_core_ctrl_tdata }),
+    .m_axis_tvalid    ({s_replay0_ctrl_tvalid, s_radio1_ctrl_tvalid, s_ddc1_ctrl_tvalid, s_duc1_ctrl_tvalid, s_radio0_ctrl_tvalid, s_ddc0_ctrl_tvalid, s_duc0_ctrl_tvalid, s_ep0_ctrl_tvalid, s_core_ctrl_tvalid}),
+    .m_axis_tlast     ({s_replay0_ctrl_tlast , s_radio1_ctrl_tlast , s_ddc1_ctrl_tlast , s_duc1_ctrl_tlast , s_radio0_ctrl_tlast , s_ddc0_ctrl_tlast , s_duc0_ctrl_tlast , s_ep0_ctrl_tlast , s_core_ctrl_tlast }),
+    .m_axis_tready    ({s_replay0_ctrl_tready, s_radio1_ctrl_tready, s_ddc1_ctrl_tready, s_duc1_ctrl_tready, s_radio0_ctrl_tready, s_ddc0_ctrl_tready, s_duc0_ctrl_tready, s_ep0_ctrl_tready, s_core_ctrl_tready}),
     .deadlock_detected()
   );
 
   // ----------------------------------------------------
   // RFNoC Core Kernel
   // ----------------------------------------------------
-  wire [(512*6)-1:0] rfnoc_core_config, rfnoc_core_status;
+  wire [(512*7)-1:0] rfnoc_core_config, rfnoc_core_status;
 
   rfnoc_core_kernel #(
     .PROTOVER            (PROTOVER),
     .DEVICE_TYPE         (16'hA300),
     .DEVICE_FAMILY       ("7SERIES"),
     .SAFE_START_CLKS     (0),
-    .NUM_BLOCKS          (6),
-    .NUM_STREAM_ENDPOINTS(4),
+    .NUM_BLOCKS          (7),
+    .NUM_STREAM_ENDPOINTS(6),
     .NUM_ENDPOINTS_CTRL  (1),
     .NUM_TRANSPORTS      (3),
-    .NUM_EDGES           (12),
+    .NUM_EDGES           (16),
     .CHDR_XBAR_PRESENT   (1),
     .EDGE_TBL_FILE       (EDGE_TBL_FILE)
   ) core_kernel_i (
@@ -917,6 +1059,145 @@ module rfnoc_image_core #(
 
 
   // ----------------------------------------------------
+  // replay0
+  // ----------------------------------------------------
+  wire              replay0_mem_clk;
+  wire [CHDR_W-1:0] s_replay0_in_1_tdata , s_replay0_in_0_tdata ;
+  wire              s_replay0_in_1_tlast , s_replay0_in_0_tlast ;
+  wire              s_replay0_in_1_tvalid, s_replay0_in_0_tvalid;
+  wire              s_replay0_in_1_tready, s_replay0_in_0_tready;
+  wire [CHDR_W-1:0] m_replay0_out_1_tdata , m_replay0_out_0_tdata ;
+  wire              m_replay0_out_1_tlast , m_replay0_out_0_tlast ;
+  wire              m_replay0_out_1_tvalid, m_replay0_out_0_tvalid;
+  wire              m_replay0_out_1_tready, m_replay0_out_0_tready;
+
+  //  axi_ram
+  wire [  1-1:0] replay0_axi_rst;
+  wire [  4-1:0] replay0_m_axi_awid;
+  wire [128-1:0] replay0_m_axi_awaddr;
+  wire [ 32-1:0] replay0_m_axi_awlen;
+  wire [ 12-1:0] replay0_m_axi_awsize;
+  wire [  8-1:0] replay0_m_axi_awburst;
+  wire [  4-1:0] replay0_m_axi_awlock;
+  wire [ 16-1:0] replay0_m_axi_awcache;
+  wire [ 12-1:0] replay0_m_axi_awprot;
+  wire [ 16-1:0] replay0_m_axi_awqos;
+  wire [ 16-1:0] replay0_m_axi_awregion;
+  wire [  4-1:0] replay0_m_axi_awuser;
+  wire [  4-1:0] replay0_m_axi_awvalid;
+  wire [  4-1:0] replay0_m_axi_awready;
+  wire [256-1:0] replay0_m_axi_wdata;
+  wire [ 32-1:0] replay0_m_axi_wstrb;
+  wire [  4-1:0] replay0_m_axi_wlast;
+  wire [  4-1:0] replay0_m_axi_wuser;
+  wire [  4-1:0] replay0_m_axi_wvalid;
+  wire [  4-1:0] replay0_m_axi_wready;
+  wire [  4-1:0] replay0_m_axi_bid;
+  wire [  8-1:0] replay0_m_axi_bresp;
+  wire [  4-1:0] replay0_m_axi_buser;
+  wire [  4-1:0] replay0_m_axi_bvalid;
+  wire [  4-1:0] replay0_m_axi_bready;
+  wire [  4-1:0] replay0_m_axi_arid;
+  wire [128-1:0] replay0_m_axi_araddr;
+  wire [ 32-1:0] replay0_m_axi_arlen;
+  wire [ 12-1:0] replay0_m_axi_arsize;
+  wire [  8-1:0] replay0_m_axi_arburst;
+  wire [  4-1:0] replay0_m_axi_arlock;
+  wire [ 16-1:0] replay0_m_axi_arcache;
+  wire [ 12-1:0] replay0_m_axi_arprot;
+  wire [ 16-1:0] replay0_m_axi_arqos;
+  wire [ 16-1:0] replay0_m_axi_arregion;
+  wire [  4-1:0] replay0_m_axi_aruser;
+  wire [  4-1:0] replay0_m_axi_arvalid;
+  wire [  4-1:0] replay0_m_axi_arready;
+  wire [  4-1:0] replay0_m_axi_rid;
+  wire [256-1:0] replay0_m_axi_rdata;
+  wire [  8-1:0] replay0_m_axi_rresp;
+  wire [  4-1:0] replay0_m_axi_rlast;
+  wire [  4-1:0] replay0_m_axi_ruser;
+  wire [  4-1:0] replay0_m_axi_rvalid;
+  wire [  4-1:0] replay0_m_axi_rready;
+
+  rfnoc_block_replay #(
+    .THIS_PORTID(8),
+    .CHDR_W(CHDR_W),
+    .NUM_PORTS(2),
+    .MEM_ADDR_W(30),
+    .MEM_DATA_W(64),
+    .MTU(MTU)
+  ) b_replay0_6 (
+    .rfnoc_chdr_clk     (rfnoc_chdr_clk),
+    .rfnoc_ctrl_clk     (rfnoc_ctrl_clk),
+    .mem_clk(replay0_mem_clk),
+    .rfnoc_core_config  (rfnoc_core_config[512*7-1:512*6]),
+    .rfnoc_core_status  (rfnoc_core_status[512*7-1:512*6]),
+
+    .axi_rst(replay0_axi_rst),
+    .m_axi_awid(replay0_m_axi_awid),
+    .m_axi_awaddr(replay0_m_axi_awaddr),
+    .m_axi_awlen(replay0_m_axi_awlen),
+    .m_axi_awsize(replay0_m_axi_awsize),
+    .m_axi_awburst(replay0_m_axi_awburst),
+    .m_axi_awlock(replay0_m_axi_awlock),
+    .m_axi_awcache(replay0_m_axi_awcache),
+    .m_axi_awprot(replay0_m_axi_awprot),
+    .m_axi_awqos(replay0_m_axi_awqos),
+    .m_axi_awregion(replay0_m_axi_awregion),
+    .m_axi_awuser(replay0_m_axi_awuser),
+    .m_axi_awvalid(replay0_m_axi_awvalid),
+    .m_axi_awready(replay0_m_axi_awready),
+    .m_axi_wdata(replay0_m_axi_wdata),
+    .m_axi_wstrb(replay0_m_axi_wstrb),
+    .m_axi_wlast(replay0_m_axi_wlast),
+    .m_axi_wuser(replay0_m_axi_wuser),
+    .m_axi_wvalid(replay0_m_axi_wvalid),
+    .m_axi_wready(replay0_m_axi_wready),
+    .m_axi_bid(replay0_m_axi_bid),
+    .m_axi_bresp(replay0_m_axi_bresp),
+    .m_axi_buser(replay0_m_axi_buser),
+    .m_axi_bvalid(replay0_m_axi_bvalid),
+    .m_axi_bready(replay0_m_axi_bready),
+    .m_axi_arid(replay0_m_axi_arid),
+    .m_axi_araddr(replay0_m_axi_araddr),
+    .m_axi_arlen(replay0_m_axi_arlen),
+    .m_axi_arsize(replay0_m_axi_arsize),
+    .m_axi_arburst(replay0_m_axi_arburst),
+    .m_axi_arlock(replay0_m_axi_arlock),
+    .m_axi_arcache(replay0_m_axi_arcache),
+    .m_axi_arprot(replay0_m_axi_arprot),
+    .m_axi_arqos(replay0_m_axi_arqos),
+    .m_axi_arregion(replay0_m_axi_arregion),
+    .m_axi_aruser(replay0_m_axi_aruser),
+    .m_axi_arvalid(replay0_m_axi_arvalid),
+    .m_axi_arready(replay0_m_axi_arready),
+    .m_axi_rid(replay0_m_axi_rid),
+    .m_axi_rdata(replay0_m_axi_rdata),
+    .m_axi_rresp(replay0_m_axi_rresp),
+    .m_axi_rlast(replay0_m_axi_rlast),
+    .m_axi_ruser(replay0_m_axi_ruser),
+    .m_axi_rvalid(replay0_m_axi_rvalid),
+    .m_axi_rready(replay0_m_axi_rready),
+
+    .s_rfnoc_chdr_tdata ({s_replay0_in_1_tdata , s_replay0_in_0_tdata }),
+    .s_rfnoc_chdr_tlast ({s_replay0_in_1_tlast , s_replay0_in_0_tlast }),
+    .s_rfnoc_chdr_tvalid({s_replay0_in_1_tvalid, s_replay0_in_0_tvalid}),
+    .s_rfnoc_chdr_tready({s_replay0_in_1_tready, s_replay0_in_0_tready}),
+    .m_rfnoc_chdr_tdata ({m_replay0_out_1_tdata , m_replay0_out_0_tdata }),
+    .m_rfnoc_chdr_tlast ({m_replay0_out_1_tlast , m_replay0_out_0_tlast }),
+    .m_rfnoc_chdr_tvalid({m_replay0_out_1_tvalid, m_replay0_out_0_tvalid}),
+    .m_rfnoc_chdr_tready({m_replay0_out_1_tready, m_replay0_out_0_tready}),
+    .s_rfnoc_ctrl_tdata (s_replay0_ctrl_tdata ),
+    .s_rfnoc_ctrl_tlast (s_replay0_ctrl_tlast ),
+    .s_rfnoc_ctrl_tvalid(s_replay0_ctrl_tvalid),
+    .s_rfnoc_ctrl_tready(s_replay0_ctrl_tready),
+    .m_rfnoc_ctrl_tdata (m_replay0_ctrl_tdata ),
+    .m_rfnoc_ctrl_tlast (m_replay0_ctrl_tlast ),
+    .m_rfnoc_ctrl_tvalid(m_replay0_ctrl_tvalid),
+    .m_rfnoc_ctrl_tready(m_replay0_ctrl_tready)
+  );
+
+
+  // ----------------------------------------------------
   // Static Router
   // ----------------------------------------------------
   assign s_duc0_in_0_tdata = m_ep0_out0_tdata ;
@@ -979,6 +1260,26 @@ module rfnoc_image_core #(
   assign s_ep3_in0_tvalid = m_ddc1_out_1_tvalid;
   assign m_ddc1_out_1_tready = s_ep3_in0_tready;
 
+  assign s_replay0_in_0_tdata = m_ep4_out0_tdata ;
+  assign s_replay0_in_0_tlast = m_ep4_out0_tlast ;
+  assign s_replay0_in_0_tvalid = m_ep4_out0_tvalid;
+  assign m_ep4_out0_tready = s_replay0_in_0_tready;
+
+  assign s_ep4_in0_tdata = m_replay0_out_0_tdata ;
+  assign s_ep4_in0_tlast = m_replay0_out_0_tlast ;
+  assign s_ep4_in0_tvalid = m_replay0_out_0_tvalid;
+  assign m_replay0_out_0_tready = s_ep4_in0_tready;
+
+  assign s_replay0_in_1_tdata = m_ep5_out0_tdata ;
+  assign s_replay0_in_1_tlast = m_ep5_out0_tlast ;
+  assign s_replay0_in_1_tvalid = m_ep5_out0_tvalid;
+  assign m_ep5_out0_tready = s_replay0_in_1_tready;
+
+  assign s_ep5_in0_tdata = m_replay0_out_1_tdata ;
+  assign s_ep5_in0_tlast = m_replay0_out_1_tlast ;
+  assign s_ep5_in0_tvalid = m_replay0_out_1_tvalid;
+  assign m_replay0_out_1_tready = s_ep5_in0_tready;
+
 
   // ----------------------------------------------------
   // Unused Ports
@@ -1001,6 +1302,7 @@ module rfnoc_image_core #(
   assign radio1_radio_clk = radio_clk;
   assign ddc1_ce_clk = ce_clk;
   assign duc1_ce_clk = ce_clk;
+  assign replay0_mem_clk = dram_clk;
 
 
   // ----------------------------------------------------
@@ -1029,6 +1331,52 @@ module rfnoc_image_core #(
   assign radio1_m_ctrlport_resp_status = m_ctrlport_radio1_resp_status;
   assign radio1_m_ctrlport_resp_data = m_ctrlport_radio1_resp_data;
 
+  assign replay0_axi_rst = axi_rst;
+  assign m_axi_awid = replay0_m_axi_awid;
+  assign m_axi_awaddr = replay0_m_axi_awaddr;
+  assign m_axi_awlen = replay0_m_axi_awlen;
+  assign m_axi_awsize = replay0_m_axi_awsize;
+  assign m_axi_awburst = replay0_m_axi_awburst;
+  assign m_axi_awlock = replay0_m_axi_awlock;
+  assign m_axi_awcache = replay0_m_axi_awcache;
+  assign m_axi_awprot = replay0_m_axi_awprot;
+  assign m_axi_awqos = replay0_m_axi_awqos;
+  assign m_axi_awregion = replay0_m_axi_awregion;
+  assign m_axi_awuser = replay0_m_axi_awuser;
+  assign m_axi_awvalid = replay0_m_axi_awvalid;
+  assign replay0_m_axi_awready = m_axi_awready;
+  assign m_axi_wdata = replay0_m_axi_wdata;
+  assign m_axi_wstrb = replay0_m_axi_wstrb;
+  assign m_axi_wlast = replay0_m_axi_wlast;
+  assign m_axi_wuser = replay0_m_axi_wuser;
+  assign m_axi_wvalid = replay0_m_axi_wvalid;
+  assign replay0_m_axi_wready = m_axi_wready;
+  assign replay0_m_axi_bid = m_axi_bid;
+  assign replay0_m_axi_bresp = m_axi_bresp;
+  assign replay0_m_axi_buser = m_axi_buser;
+  assign replay0_m_axi_bvalid = m_axi_bvalid;
+  assign m_axi_bready = replay0_m_axi_bready;
+  assign m_axi_arid = replay0_m_axi_arid;
+  assign m_axi_araddr = replay0_m_axi_araddr;
+  assign m_axi_arlen = replay0_m_axi_arlen;
+  assign m_axi_arsize = replay0_m_axi_arsize;
+  assign m_axi_arburst = replay0_m_axi_arburst;
+  assign m_axi_arlock = replay0_m_axi_arlock;
+  assign m_axi_arcache = replay0_m_axi_arcache;
+  assign m_axi_arprot = replay0_m_axi_arprot;
+  assign m_axi_arqos = replay0_m_axi_arqos;
+  assign m_axi_arregion = replay0_m_axi_arregion;
+  assign m_axi_aruser = replay0_m_axi_aruser;
+  assign m_axi_arvalid = replay0_m_axi_arvalid;
+  assign replay0_m_axi_arready = m_axi_arready;
+  assign replay0_m_axi_rid = m_axi_rid;
+  assign replay0_m_axi_rdata = m_axi_rdata;
+  assign replay0_m_axi_rresp = m_axi_rresp;
+  assign replay0_m_axi_rlast = m_axi_rlast;
+  assign replay0_m_axi_ruser = m_axi_ruser;
+  assign replay0_m_axi_rvalid = m_axi_rvalid;
+  assign m_axi_rready = replay0_m_axi_rready;
+
   assign radio0_radio_rx_data = radio_rx_data_radio0;
   assign radio0_radio_rx_stb = radio_rx_stb_radio0;
   assign radio_rx_running_radio0 = radio0_radio_rx_running;
diff --git a/fpga/usrp3/top/x300/x310_rfnoc_image_core.yml b/fpga/usrp3/top/x300/x310_rfnoc_image_core.yml
index 5d6a98c7d..84b5f0234 100644
--- a/fpga/usrp3/top/x300/x310_rfnoc_image_core.yml
+++ b/fpga/usrp3/top/x300/x310_rfnoc_image_core.yml
@@ -28,6 +28,14 @@ stream_endpoints:
     ctrl: False                     # Endpoint passes control traffic
     data: True                      # Endpoint passes data traffic
     buff_size: 0                    # Ingress buffer size for data
+  ep4:                       # Stream endpoint name
+    ctrl: False                     # Endpoint passes control traffic
+    data: True                      # Endpoint passes data traffic
+    buff_size: 4096                 # Ingress buffer size for data
+  ep5:                       # Stream endpoint name
+    ctrl: False                     # Endpoint passes control traffic
+    data: True                      # Endpoint passes data traffic
+    buff_size: 4096                 # Ingress buffer size for data
 
 # A list of all NoC blocks in design
 # ----------------------------------
@@ -52,16 +60,11 @@ noc_blocks:
       NUM_PORTS: 2
   radio1:
     block_desc: 'radio_2x64.yml'
-  # These parameters are for reference, in case a DRAM FIFO is required
-  #fifo0:
-    #block_desc: 'axi_ram_fifo_2x64.yml'
-    #parameters:
-      ## These parameters match the interface on the x300/X310
-      #MEM_DATA_W: 64
-      #MEM_ADDR_W: 30
-      #FIFO_ADDR_BASE: "{30'h02000000, 30'h00000000}"
-      #FIFO_ADDR_MASK: "{30'h01FFFFFF, 30'h01FFFFFF}"
-      #MEM_CLK_RATE: "300e6"
+  replay0:
+    block_desc: 'replay.yml'
+    parameters:
+      NUM_PORTS: 2
+      MEM_ADDR_W: 30
 
 # A list of all static connections in design
 # ------------------------------------------
@@ -89,9 +92,18 @@ connections:
   # radio1(1) to ep3 - RFB RX
   - { srcblk: radio1, srcport: out_1, dstblk: ddc1,   dstport: in_1 }
   - { srcblk: ddc1,   srcport: out_1, dstblk: ep3,    dstport: in0  }
+  # ep4 to replay0(0)
+  - { srcblk: ep4,     srcport: out0,  dstblk: replay0, dstport: in_0 }
+  # replay0(0) to ep4
+  - { srcblk: replay0, srcport: out_0, dstblk: ep4,     dstport: in0  }
+  # ep5 to replay0(1)
+  - { srcblk: ep5,     srcport: out0,  dstblk: replay0, dstport: in_1 }
+  # replay0(1) to ep5
+  - { srcblk: replay0, srcport: out_1, dstblk: ep5,     dstport: in0  }
   # BSP Connections
   - { srcblk: radio0, srcport: ctrl_port, dstblk: _device_, dstport: ctrlport_radio0 }
   - { srcblk: radio1, srcport: ctrl_port, dstblk: _device_, dstport: ctrlport_radio1 }
+  - { srcblk: replay0, srcport: axi_ram, dstblk: _device_, dstport: dram }
   - { srcblk: _device_, srcport: x300_radio0, dstblk: radio0, dstport: x300_radio }
   - { srcblk: _device_, srcport: x300_radio1, dstblk: radio1, dstport: x300_radio }
   - { srcblk: _device_, srcport: time_keeper, dstblk: radio0, dstport: time_keeper }
@@ -111,3 +123,4 @@ clk_domains:
     - { srcblk: _device_, srcport: radio, dstblk: radio1, dstport: radio }
     - { srcblk: _device_, srcport: ce,    dstblk: ddc1,   dstport: ce    }
     - { srcblk: _device_, srcport: ce,    dstblk: duc1,   dstport: ce    }
+    - { srcblk: _device_, srcport: dram,  dstblk: replay0, dstport: mem  }
diff --git a/fpga/usrp3/top/x300/x310_static_router.hex b/fpga/usrp3/top/x300/x310_static_router.hex
index 53635706f..eb493cee8 100644
--- a/fpga/usrp3/top/x300/x310_static_router.hex
+++ b/fpga/usrp3/top/x300/x310_static_router.hex
@@ -1,13 +1,17 @@
-0000000C
-00400140
-014001c0
-01c00180
-01800040
-01c10181
-01810080
-00c00200
-02000280
-02800240
-024000c0
-02810241
-02410100
+00000010
+004001c0
+01c00240
+02400200
+02000040
+02410201
+02010080
+00c00280
+02800300
+030002c0
+02c000c0
+030102c1
+02c10100
+01400340
+03400140
+01800341
+03410180