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authorPhilip Balister <philip@opensdr.com>2010-08-19 21:24:51 +0000
committerPhilip Balister <philip@opensdr.com>2010-08-19 21:24:51 +0000
commit10f6e1aeec082c6b5ef0485e232266921a3adbc7 (patch)
tree627e5f6391588b349bc14c47bfb10b1cf6c3f0ad /fpga
parent38722979512f0f6d57db9fd5e314b94cad1f188e (diff)
parentb84f2da152eb65afe89240941bd02d67b3582eae (diff)
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Merge branch 'master' of ettus.sourcerepo.com:ettus/uhdpriv into usrp_e
Conflicts: host/examples/CMakeLists.txt
Diffstat (limited to 'fpga')
-rw-r--r--fpga/usrp2/vrt/vita_rx_framer.v2
1 files changed, 1 insertions, 1 deletions
diff --git a/fpga/usrp2/vrt/vita_rx_framer.v b/fpga/usrp2/vrt/vita_rx_framer.v
index fd82263d0..235817941 100644
--- a/fpga/usrp2/vrt/vita_rx_framer.v
+++ b/fpga/usrp2/vrt/vita_rx_framer.v
@@ -128,7 +128,7 @@ module vita_rx_framer
VITA_ERR_SECS : pkt_fifo_line <= {2'b00,vita_time_fifo_o[63:32]};
VITA_ERR_TICS : pkt_fifo_line <= {2'b00,32'd0};
VITA_ERR_TICS2 : pkt_fifo_line <= {2'b00,vita_time_fifo_o[31:0]};
- VITA_ERR_PAYLOAD : pkt_fifo_line <= {2'b11,28'd0,flags_fifo_o};
+ VITA_ERR_PAYLOAD : pkt_fifo_line <= {2'b10,28'd0,flags_fifo_o};
//VITA_ERR_TRAILER : pkt_fifo_line <= {2'b11,vita_trailer};
default : pkt_fifo_line <= 34'h0_FFFF_FFFF;