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| author | Matt Ettus <matt@ettus.com> | 2010-05-12 16:10:08 -0700 |
|---|---|---|
| committer | Matt Ettus <matt@ettus.com> | 2010-05-12 16:10:08 -0700 |
| commit | 4eef4015672ffafb56d66feb57848772f42b54e3 (patch) | |
| tree | e89d11e9281462719114896332f548ea66fbfd13 /fpga | |
| parent | fd4bdced70e5089434ec736b5938456219bda068 (diff) | |
| download | uhd-4eef4015672ffafb56d66feb57848772f42b54e3.tar.gz uhd-4eef4015672ffafb56d66feb57848772f42b54e3.tar.bz2 uhd-4eef4015672ffafb56d66feb57848772f42b54e3.zip | |
move dsp settings regs to reclocked setting bus. Works, gets us to within 18ps of passing timing
Diffstat (limited to 'fpga')
0 files changed, 0 insertions, 0 deletions