Merge branch 'next'

23 files changed, 1050 insertions, 1545 deletions

diff --git a/fpga/usrp2/fifo/Makefile.srcs b/fpga/usrp2/fifo/Makefile.srcs
index 6cbd5cd3f..55ba0be2a 100644
--- a/fpga/usrp2/fifo/Makefile.srcs
+++ b/fpga/usrp2/fifo/Makefile.srcs
@@ -1,5 +1,5 @@
 #
-# Copyright 2010 Ettus Research LLC
+# Copyright 2010-2012 Ettus Research LLC
 #
 
 ##################################################
@@ -38,4 +38,5 @@ packet_generator.v \
 packet_verifier32.v \
 packet_verifier.v \
 fifo19_pad.v \
+packet_padder36.v \
 ))
diff --git a/fpga/usrp2/fifo/packet_padder36.v b/fpga/usrp2/fifo/packet_padder36.v
new file mode 100644
index 000000000..7197b5ea5
--- /dev/null
+++ b/fpga/usrp2/fifo/packet_padder36.v
@@ -0,0 +1,155 @@
+//
+// Copyright 2011-2012 Ettus Research LLC
+//
+// This program is free software: you can redistribute it and/or modify
+// it under the terms of the GNU General Public License as published by
+// the Free Software Foundation, either version 3 of the License, or
+// (at your option) any later version.
+//
+// This program is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+// GNU General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with this program.  If not, see <http://www.gnu.org/licenses/>.
+//
+
+// The packet padder 36 for use with RX VITA stream output.
+// Packet padder understands the concept of USB LUTs,
+// and will forward packets through the interface,
+// adding zero padding as needed to properly flush.
+// The padder will never write a packet across a LUT boundary.
+// When flushing, padder writes out zeros until the LUT boundary.
+// Requires that the input line0 be a VITA header, and SOF set.
+// Flush when the LUT is partially filled and timeout is reached,
+// or when the LUT is partially filled and the DSP is inactive.
+
+module packet_padder36
+#(
+    parameter BASE = 0,
+
+    //default is 16K LUT
+    parameter DEFAULT_LINES32 = 4096,
+
+    //default about 1ms at 64MHz clock
+    parameter DEFAULT_IDLE_CYC = 65536
+)
+(
+    input clk, input reset,
+
+    //setting bus
+    input set_stb, input [7:0] set_addr, input [31:0] set_data,
+
+    //input interface
+    input [35:0] data_i,
+    input src_rdy_i,
+    output dst_rdy_o,
+
+    //output interface
+    output [35:0] data_o,
+    output src_rdy_o,
+    input dst_rdy_i,
+
+    input always_flush
+);
+
+    wire lut_lines_changed;
+    wire [15:0] max_lut_lines32;
+    setting_reg #(.my_addr(BASE+0),.width(16),.at_reset(DEFAULT_LINES32)) sr_num_lines(
+        .clk(clk),.rst(reset),.strobe(set_stb),.addr(set_addr),.in(set_data),
+        .out(max_lut_lines32),.changed(lut_lines_changed));
+
+    wire idle_cyc_changed;
+    wire [17:0] idle_flush_cycles;
+    setting_reg #(.my_addr(BASE+1),.width(18),.at_reset(DEFAULT_IDLE_CYC)) sr_flush_cyc(
+        .clk(clk),.rst(reset),.strobe(set_stb),.addr(set_addr),.in(set_data),
+        .out(idle_flush_cycles),.changed(idle_cyc_changed));
+
+    //state machine definitions
+    localparam STATE_READ_HDR = 0;
+    localparam STATE_WRITE_HDR = 1;
+    localparam STATE_FORWARD = 2;
+    localparam STATE_WRITE_PAD = 3;
+    reg [1:0] state;
+
+    //keep track of the outgoing lines
+    reg [15:0] line_count;
+    wire line_count_done = line_count == 1;
+    wire lut_is_empty = line_count == max_lut_lines32;
+    always @(posedge clk) begin
+        if (reset || lut_lines_changed) begin
+            line_count <= max_lut_lines32;
+        end
+        else if (src_rdy_o && dst_rdy_i) begin
+            line_count <= (line_count_done)? max_lut_lines32 : line_count - 1;
+        end
+    end
+
+    //count the number of cycles since RX data so we can force a flush
+    reg [17:0] non_rx_cycles;
+    wire idle_timeout = (non_rx_cycles == idle_flush_cycles);
+    always @(posedge clk) begin
+        if(reset || state != STATE_READ_HDR || idle_cyc_changed) begin
+            non_rx_cycles <= 0;
+        end
+        else if (~idle_timeout) begin
+            non_rx_cycles <= non_rx_cycles + 1;
+        end
+    end
+
+    //flush when we have written data to a LUT and either idle or non active DSP
+    wire force_flush = ~lut_is_empty && (idle_timeout || always_flush);
+
+    //the padding state machine
+    reg [31:0] vita_hdr;
+    reg has_vita_hdr;
+    always @(posedge clk) begin
+        if (reset) begin
+            state <= STATE_READ_HDR;
+        end
+        else case(state)
+
+        STATE_READ_HDR: begin
+            if (src_rdy_i && dst_rdy_o && data_i[32]) begin
+                vita_hdr <= data_i[31:0];
+                has_vita_hdr <= 1;
+                state <= (data_i[15:0] > line_count)? state <= STATE_WRITE_PAD : STATE_WRITE_HDR;
+            end
+            else if (force_flush) begin
+                has_vita_hdr <= 0;
+                state <= STATE_WRITE_PAD;
+            end
+        end
+
+        STATE_WRITE_HDR: begin
+            if (src_rdy_o && dst_rdy_i) begin
+                state <= STATE_FORWARD;
+            end
+        end
+
+        STATE_FORWARD: begin
+            if (src_rdy_i && dst_rdy_o && data_i[33]) begin
+                state <= STATE_READ_HDR;
+            end
+        end
+
+        STATE_WRITE_PAD: begin
+            if (src_rdy_o && dst_rdy_i && line_count_done) begin
+                state <= (has_vita_hdr)? STATE_WRITE_HDR : STATE_READ_HDR;
+            end
+        end
+
+        endcase //state
+    end
+
+    //assign outgoing signals
+    assign dst_rdy_o = (state == STATE_READ_HDR)? 1 : ((state == STATE_FORWARD)? dst_rdy_i : 0);
+    assign src_rdy_o = (state == STATE_WRITE_HDR || state == STATE_WRITE_PAD)? 1 : ((state == STATE_FORWARD )? src_rdy_i : 0);
+    assign data_o = (state == STATE_WRITE_HDR)? {4'b0001, vita_hdr} : ((state == STATE_FORWARD)? data_i : 0);
+
+endmodule // packet_padder36
+
+
+
+
diff --git a/fpga/usrp2/gpif/Makefile.srcs b/fpga/usrp2/gpif/Makefile.srcs
index 524e3660d..7909fb5ff 100644
--- a/fpga/usrp2/gpif/Makefile.srcs
+++ b/fpga/usrp2/gpif/Makefile.srcs
@@ -8,4 +8,6 @@
 GPIF_SRCS = $(abspath $(addprefix $(BASE_DIR)/../gpif/, \
 packet_reframer.v \
 slave_fifo.v \
+fifo36_to_gpmc16.v \
+gpmc16_to_fifo36.v \
 ))
diff --git a/fpga/usrp2/gpif/fifo36_to_gpmc16.v b/fpga/usrp2/gpif/fifo36_to_gpmc16.v
new file mode 100644
index 000000000..508cd319c
--- /dev/null
+++ b/fpga/usrp2/gpif/fifo36_to_gpmc16.v
@@ -0,0 +1,54 @@
+//
+// Copyright 2012 Ettus Research LLC
+//
+// This program is free software: you can redistribute it and/or modify
+// it under the terms of the GNU General Public License as published by
+// the Free Software Foundation, either version 3 of the License, or
+// (at your option) any later version.
+//
+// This program is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+// GNU General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with this program.  If not, see <http://www.gnu.org/licenses/>.
+//
+
+module fifo36_to_gpmc16
+#(
+    parameter FIFO_SIZE = 9
+)
+(
+    //input fifo interface
+    input fifo_clk, input fifo_rst,
+    input [35:0] in_data,
+    input in_src_rdy,
+    output in_dst_rdy,
+
+    //output interface
+    input gpif_clk, input gpif_rst,
+    output [15:0] out_data,
+    output valid,
+    input enable,
+    output eof
+);
+
+    wire [35:0] data_int;
+    wire src_rdy_int, dst_rdy_int;
+
+    fifo_2clock_cascade #(.WIDTH(36), .SIZE(FIFO_SIZE)) fifo_2clk
+     (.wclk(fifo_clk), .datain(in_data), .src_rdy_i(in_src_rdy), .dst_rdy_o(in_dst_rdy), .space(),
+      .rclk(gpif_clk), .dataout(data_int), .src_rdy_o(src_rdy_int), .dst_rdy_i(dst_rdy_int), .occupied(),
+      .arst(fifo_rst | gpif_rst));
+
+    wire [18:0] data18_int;
+    fifo36_to_fifo19 #(.LE(1)) f36_to_f19
+     (.clk(gpif_clk), .reset(gpif_rst), .clear(1'b0),
+      .f36_datain(data_int), .f36_src_rdy_i(src_rdy_int), .f36_dst_rdy_o(dst_rdy_int),
+      .f19_dataout(data18_int), .f19_src_rdy_o(valid), .f19_dst_rdy_i(enable) );
+
+    assign out_data = data18_int[15:0];
+    assign eof = data18_int[17];
+
+endmodule //fifo_to_gpmc16
diff --git a/fpga/usrp2/gpif/gpmc16_to_fifo36.v b/fpga/usrp2/gpif/gpmc16_to_fifo36.v
new file mode 100644
index 000000000..933891715
--- /dev/null
+++ b/fpga/usrp2/gpif/gpmc16_to_fifo36.v
@@ -0,0 +1,64 @@
+//
+// Copyright 2012 Ettus Research LLC
+//
+// This program is free software: you can redistribute it and/or modify
+// it under the terms of the GNU General Public License as published by
+// the Free Software Foundation, either version 3 of the License, or
+// (at your option) any later version.
+//
+// This program is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+// GNU General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with this program.  If not, see <http://www.gnu.org/licenses/>.
+//
+
+module gpmc16_to_fifo36
+#(
+    parameter FIFO_SIZE = 9,
+
+    //not ready until minimum xfers of space available
+    parameter MIN_SPACE16 = 128
+)
+(
+    //input interface
+    input gpif_clk, input gpif_rst,
+    input [15:0] in_data,
+    input valid,
+    output reg ready,
+
+    //output fifo interface
+    input fifo_clk, input fifo_rst,
+    output [35:0] out_data,
+    output out_src_rdy,
+    input out_dst_rdy
+);
+
+    wire [35:0] data_int;
+    wire src_rdy_int, dst_rdy_int;
+    wire [18:0] refr_data;
+    wire refr_src_rdy, refr_dst_rdy;
+
+    wire [15:0] fifo_space;
+
+    always @(posedge gpif_clk)
+        ready <= (fifo_space >= MIN_SPACE16/2);
+
+   packet_reframer packet_reframer 
+     (.clk(gpif_clk), .reset(gpif_rst), .clear(1'b0),
+      .data_i(in_data), .src_rdy_i(valid), .dst_rdy_o(),
+      .data_o(refr_data), .src_rdy_o(refr_src_rdy), .dst_rdy_i(refr_dst_rdy));
+
+   fifo19_to_fifo36 #(.LE(1)) f19_to_f36
+     (.clk(gpif_clk), .reset(gpif_rst), .clear(1'b0),
+      .f19_datain(refr_data), .f19_src_rdy_i(refr_src_rdy), .f19_dst_rdy_o(refr_dst_rdy),
+      .f36_dataout(data_int), .f36_src_rdy_o(src_rdy_int), .f36_dst_rdy_i(dst_rdy_int));
+
+   fifo_2clock_cascade #(.WIDTH(36), .SIZE(FIFO_SIZE)) fifo_2clk
+     (.wclk(gpif_clk), .datain(data_int), .src_rdy_i(src_rdy_int), .dst_rdy_o(dst_rdy_int), .space(fifo_space),
+      .rclk(fifo_clk), .dataout(out_data), .src_rdy_o(out_src_rdy), .dst_rdy_i(out_dst_rdy), .occupied(),
+      .arst(fifo_rst | gpif_rst));
+
+endmodule //fifo_to_gpmc16
diff --git a/fpga/usrp2/gpif/slave_fifo.v b/fpga/usrp2/gpif/slave_fifo.v
index d1a0a027b..0f301f8a6 100644
--- a/fpga/usrp2/gpif/slave_fifo.v
+++ b/fpga/usrp2/gpif/slave_fifo.v
@@ -20,85 +20,70 @@
 //this is a FIFO master interface for the FX2 in "slave fifo" mode.
 
 module slave_fifo
-  #(parameter TXFIFOSIZE = 12, parameter RXFIFOSIZE = 12)
+  #(
+        //how many cycles max in a transfer state
+        parameter DATA_XFER_COUNT = 256,
+        parameter CTRL_XFER_COUNT = 32,
+
+        //sizes for fifo36 2 clock cascade fifos
+        parameter DATA_RX_FIFO_SIZE = 9,
+        parameter DATA_TX_FIFO_SIZE = 9,
+        parameter CTRL_RX_FIFO_SIZE = 9,
+        parameter CTRL_TX_FIFO_SIZE = 9
+   )
    (// GPIF signals
     input gpif_clk, input gpif_rst,
     inout [15:0] gpif_d,
     input [3:0] gpif_ctl,
-    output sloe, output slrd, output slwr, output pktend, output [1:0] fifoadr,
-    
-    // Wishbone signals
-    input wb_clk, input wb_rst,
-    output [15:0] wb_adr_o, output [15:0] wb_dat_mosi, input [15:0] wb_dat_miso,
-    output [1:0] wb_sel_o, output wb_cyc_o, output wb_stb_o, output wb_we_o, input wb_ack_i,
-    input [7:0] triggers,
-    
-    input dsp_rx_run,
-    
+    output reg sloe, output reg slrd, output reg slwr, output reg pktend, output reg [1:0] fifoadr,
+
     // FIFO interface
-    input fifo_clk, input fifo_rst, input clear_tx, input clear_rx,
-    output [35:0] tx_data_o, output tx_src_rdy_o, input tx_dst_rdy_i,
-    input [35:0] rx_data_i, input rx_src_rdy_i, output rx_dst_rdy_o,
-    input [35:0] tx_err_data_i, input tx_err_src_rdy_i, output tx_err_dst_rdy_o,
-    output tx_underrun, output rx_overrun,
-    
-    input [15:0] test_len, input [7:0] test_rate, input [3:0] test_ctrl,
-    output [31:0] debug0, output [31:0] debug1
+    input fifo_clk, input fifo_rst,
+    output [35:0] tx_data, output tx_src_rdy, input tx_dst_rdy,
+    input [35:0] rx_data, input rx_src_rdy, output rx_dst_rdy,
+    output [35:0] ctrl_data, output ctrl_src_rdy, input ctrl_dst_rdy,
+    input [35:0] resp_data, input resp_src_rdy, output resp_dst_rdy,
+
+    output [31:0] debug
     );
 
-    reg FX2_DE, FX2_CE, FX2_DF, FX2_CF;
+    wire FX2_DE_pre = ~gpif_ctl[0]; //EP2 FX2 FIFO empty (FLAGA)
+    wire FX2_CE_pre = ~gpif_ctl[1]; //EP4 FX2 FIFO empty (FLAGB)
+    wire FX2_DF_pre = ~gpif_ctl[2]; //EP6 FX2 FIFO full  (FLAGC)
+    wire FX2_CF_pre = ~gpif_ctl[3]; //EP8 FX2 FIFO full  (FLAGD)
 
-   // inputs to FPGA (all active low)
+    reg FX2_DE, FX2_CE, FX2_DF, FX2_CF;
     always @(posedge gpif_clk) begin
-        FX2_DE <= ~gpif_ctl[0]; //EP2 FX2 FIFO empty (FLAGA)
-        FX2_CE <= ~gpif_ctl[1]; //EP4 FX2 FIFO empty (FLAGB)
-        FX2_DF <= ~gpif_ctl[2]; //EP6 FX2 FIFO full  (FLAGC)
-        FX2_CF <= ~gpif_ctl[3]; //EP8 FX2 FIFO full  (FLAGD)
+        FX2_DE <= FX2_DE_pre; //EP2 FX2 FIFO empty (FLAGA)
+        FX2_CE <= FX2_CE_pre; //EP4 FX2 FIFO empty (FLAGB)
+        FX2_DF <= FX2_DF_pre; //EP6 FX2 FIFO full  (FLAGC)
+        FX2_CF <= FX2_CF_pre; //EP8 FX2 FIFO full  (FLAGD)
     end
 
-   wire [17:0] 	  gpif_d_out_ctrl, gpif_d_out_data, gpif_d_out;
+   wire [15:0] gpif_d_out_ctrl, gpif_d_out_data;
+   reg [15:0] gpif_d_out, gpif_d_in;
 
    // ////////////////////////////////////////////////////////////////////
    // GPIF bus master state machine
 
-   //transfer size for GPIF data. this can be anything really, it's specified only for
-   //fairness in bus sharing. 256 lines is 512 bytes over the wire, half the size of
-   //the double buffers in B100/B150. this should probably be a toplevel parameter or even
-   //a settings register value.
-   localparam data_transfer_size = 256;
-   localparam ctrl_transfer_size = 16; //probably unnecessary since ctrl xfers won't back up
-
-   // state machine i/o to four fifos
-   //tx
-   wire ctrl_tx_dst_rdy; //sm input, ctrl tx path has space
-   wire ctrl_tx_src_rdy; //sm output, ctrl tx path enable
-   wire data_tx_dst_rdy; //sm input, data tx path has space
-   wire data_tx_src_rdy; //sm output, data tx path enable
-
-   //rx
-   wire ctrl_rx_dst_rdy; //sm output, ctrl rx path enable
-   wire ctrl_rx_src_rdy; //sm input, ctrl rx path has space
-   wire data_rx_dst_rdy; //sm output, data rx path enable
-   wire data_rx_src_rdy; //sm input, data rx path has space
-
-   reg tx_data_enough_space;
+    wire rx_valid, resp_valid;
+    reg tx_valid, ctrl_valid;
+    wire tx_ready, ctrl_ready;
+    reg rx_enable, resp_enable;
 
    reg [9:0] transfer_count; //number of lines (a line is 16 bits) in active transfer
 
-   reg pktend_latch;
-
    reg [3:0] state; //state machine current state
    localparam STATE_IDLE    = 0;
-   localparam STATE_DATA_RX = 5;
+   localparam STATE_THINK   = 1;
+   localparam STATE_DATA_RX = 2;
    localparam STATE_DATA_TX = 3;
-   localparam STATE_CTRL_RX = 6;
-   localparam STATE_CTRL_TX = 9;
-   localparam STATE_DATA_TX_SLOE = 2;
-   localparam STATE_CTRL_TX_SLOE = 8;
-   localparam STATE_DATA_RX_ADR = 1;
-   localparam STATE_CTRL_RX_ADR = 4;
-   localparam STATE_PKTEND_ADR = 10;
-   localparam STATE_PKTEND = 7;
+   localparam STATE_CTRL_RX = 4;
+   localparam STATE_CTRL_TX = 5;
+   localparam STATE_DATA_TX_SLOE = 6;
+   localparam STATE_CTRL_TX_SLOE = 7;
+   localparam STATE_DATA_RX_ADR = 8;
+   localparam STATE_CTRL_RX_ADR = 9;
 
    //logs the last bus user for xfer fairness
    //we only care about data rx vs. tx since ctrl pkts are so short
@@ -106,384 +91,184 @@ module slave_fifo
    localparam BUS_HOG_RX = 0;
    localparam BUS_HOG_TX = 1;
 
-    //count the number of cycles since RX data so we can force a flush
-    reg [17:0] non_rx_cycles;
-    localparam rx_idle_flush_cycles = 65536; //about 1ms at 64MHz clock
-    always @(posedge gpif_clk) begin
-        if(gpif_rst || state == STATE_DATA_RX || state == STATE_PKTEND)
-            non_rx_cycles <= 0;
-        else if (non_rx_cycles != rx_idle_flush_cycles)
-            non_rx_cycles <= non_rx_cycles + 1;
-    end
-
-    //when should we flush aka pktend?
-    //pktend_latch tells us that its ok to flush -> we just had an RX xfer with EOF
-    //the RX DSP not running or a cycle counter gives us the flushing response dynamic
-    wire rx_data_flush = (~dsp_rx_run || non_rx_cycles == rx_idle_flush_cycles) && pktend_latch;
+    wire resp_eof;
+    reg [1:0] idle_count;
 
    // //////////////////////////////////////////////////////////////
    // FX2 slave FIFO bus master state machine
    //
-   always @(posedge gpif_clk)
-     if(gpif_rst) begin
-       state <= STATE_IDLE;
-       pktend_latch <= 0;
-     end
-     else
-        begin
-       case (state)
-         STATE_IDLE:
-            begin
-           transfer_count <= 0;
-           //handle transitions to other states
-           if(ctrl_tx_dst_rdy & ~FX2_CE) //if there's room in the ctrl fifo and the FX2 has ctrl data
-             state <= STATE_CTRL_TX_SLOE;
-           else if(ctrl_rx_src_rdy & ~FX2_CF) //if the ctrl fifo has data and the FX2 isn't full
-             state <= STATE_CTRL_RX_ADR;
-           else if(data_tx_dst_rdy & ~FX2_DE & last_data_bus_hog == BUS_HOG_RX & tx_data_enough_space) //if there's room in the data fifo and the FX2 has data
-             state <= STATE_DATA_TX_SLOE;
-           else if(data_rx_src_rdy & ~FX2_DF & last_data_bus_hog == BUS_HOG_TX) //if the data fifo has data and the FX2 isn't full
-             state <= STATE_DATA_RX_ADR;
-           else if(data_tx_dst_rdy & ~FX2_DE & tx_data_enough_space)
-             state <= STATE_DATA_TX_SLOE;
-           else if(data_rx_src_rdy & ~FX2_DF)
-             state <= STATE_DATA_RX_ADR;
-           else if(rx_data_flush & ~FX2_DF)
-             state <= STATE_PKTEND_ADR;
-            end
-
-         STATE_DATA_TX_SLOE: //just to assert SLOE one cycle before SLRD
-           state <= STATE_DATA_TX;
-         STATE_CTRL_TX_SLOE:
-           state <= STATE_CTRL_TX;
-
-         STATE_DATA_RX_ADR: //just to assert FIFOADR one cycle before SLWR
-           state <= STATE_DATA_RX;
-         STATE_CTRL_RX_ADR:
-           state <= STATE_CTRL_RX;
-
-         STATE_DATA_RX:
-            begin
-                if(data_rx_src_rdy && data_rx_dst_rdy) begin
-                    transfer_count <= transfer_count + 1;
-                    pktend_latch <= gpif_d_out_data[17]; //ok to do pkt end when we complete with EOF
-                end
-                else
-                    state <= STATE_IDLE;
-                last_data_bus_hog <= BUS_HOG_RX;
-            end
-            
-         STATE_PKTEND_ADR:
-            begin
-           state <= STATE_PKTEND;
-            end
-
-         STATE_PKTEND:
-            begin
-           state <= STATE_IDLE;
-           pktend_latch <= 0;
-            end
-            
-         STATE_DATA_TX:
-            begin
-                if(data_tx_dst_rdy && data_tx_src_rdy)
-                    transfer_count <= transfer_count + 1;
-                else
-                    state <= STATE_IDLE;
-                last_data_bus_hog <= BUS_HOG_TX;
-            end
-         STATE_CTRL_RX:
-            begin
-                if(ctrl_rx_src_rdy && ctrl_rx_dst_rdy)
-                    transfer_count <= transfer_count + 1;
-                else
-                    state <= STATE_IDLE;
-            end
-         STATE_CTRL_TX:
-            begin
-                if(ctrl_tx_dst_rdy && ctrl_tx_src_rdy)
-                    transfer_count <= transfer_count + 1;
-                else
-                    state <= STATE_IDLE;
-            end
-       endcase
+    always @(posedge gpif_clk)
+    if(gpif_rst) begin
+        state <= STATE_IDLE;
+        sloe <= 1;
+        slrd <= 1;
+        slwr <= 1;
+        pktend <= 1;
+        rx_enable <= 0;
+        tx_valid <= 0;
+        ctrl_valid <= 0;
+        resp_enable <= 0;
+        idle_count <= 0;
+    end
+    else case (state)
+    STATE_IDLE: begin
+        transfer_count <= 0;
+        sloe <= 1;
+        slrd <= 1;
+        slwr <= 1;
+        pktend <= 1;
+        rx_enable <= 0;
+        tx_valid <= 0;
+        ctrl_valid <= 0;
+        resp_enable <= 0;
+        if (idle_count == 2'b11) state <= STATE_THINK;
+        idle_count <= idle_count + 1;
+    end
+
+    STATE_THINK: begin
+
+        idle_count <= 0;
+
+        //handle transitions to other states
+        if(ctrl_ready & ~FX2_CE) begin //if there's room in the ctrl fifo and the FX2 has ctrl data
+            state <= STATE_CTRL_TX_SLOE;
+            fifoadr <= 2'b01;
+            sloe <= 0;
         end
+        else if(resp_valid & ~FX2_CF) begin //if the ctrl fifo has data and the FX2 isn't full
+            state <= STATE_CTRL_RX_ADR;
+            fifoadr <= 2'b11;
+        end
+        else if(tx_ready & ~FX2_DE & last_data_bus_hog == BUS_HOG_RX) begin //if there's room in the data fifo and the FX2 has data
+            state <= STATE_DATA_TX_SLOE;
+            last_data_bus_hog <= BUS_HOG_TX;
+            fifoadr <= 2'b00;
+            sloe <= 0;
+        end
+        else if(rx_valid & ~FX2_DF & last_data_bus_hog == BUS_HOG_TX) begin //if the data fifo has data and the FX2 isn't full
+            state <= STATE_DATA_RX_ADR;
+            last_data_bus_hog <= BUS_HOG_RX;
+            fifoadr <= 2'b10;
+        end
+        else if(tx_ready & ~FX2_DE) begin
+            state <= STATE_DATA_TX_SLOE;
+            last_data_bus_hog <= BUS_HOG_TX;
+            fifoadr <= 2'b00;
+            sloe <= 0;
+        end
+        else if(rx_valid & ~FX2_DF) begin
+            state <= STATE_DATA_RX_ADR;
+            last_data_bus_hog <= BUS_HOG_RX;
+            fifoadr <= 2'b10;
+        end
+    end
+
+    STATE_DATA_TX_SLOE: begin //just to assert SLOE one cycle before SLRD
+        state <= STATE_DATA_TX;
+        slrd <= 0;
+    end
 
-   // ///////////////////////////////////////////////////////////////////
-   // fifo signal assignments and enables
+    STATE_CTRL_TX_SLOE: begin
+        state <= STATE_CTRL_TX;
+        slrd <= 0;
+    end
 
-   //enable fifos
-   assign data_rx_dst_rdy = (state == STATE_DATA_RX) && ~FX2_DF && (transfer_count != data_transfer_size);
-   assign data_tx_src_rdy = (state == STATE_DATA_TX) && ~FX2_DE && (transfer_count != data_transfer_size);
-   assign ctrl_rx_dst_rdy = (state == STATE_CTRL_RX) && ~FX2_CF;
-   assign ctrl_tx_src_rdy = (state == STATE_CTRL_TX) && ~FX2_CE;
+    STATE_DATA_RX_ADR: begin //just to assert FIFOADR one cycle before SLWR
+        state <= STATE_DATA_RX;
+        rx_enable <= 1;
+    end
 
-   //framing for TX ctrl packets
-   wire sop_ctrl, eop_ctrl;
-   assign sop_ctrl = (transfer_count == 0);
-   assign eop_ctrl = (transfer_count == (ctrl_transfer_size-1));
+    STATE_CTRL_RX_ADR: begin
+        state <= STATE_CTRL_RX;
+        resp_enable <= 1;
+    end
+
+    STATE_DATA_RX: begin
+        if (FX2_DF_pre || ~rx_valid || transfer_count == DATA_XFER_COUNT-1) begin
+            state <= STATE_IDLE;
+            rx_enable <= 0;
+        end
+        gpif_d_out <= gpif_d_out_data;
+        slwr <= ~rx_valid;
+        transfer_count <= transfer_count + 1;
+    end
+
+    STATE_DATA_TX: begin
+        if (FX2_DE_pre || transfer_count == DATA_XFER_COUNT-1) begin
+            state <= STATE_IDLE;
+            slrd <= 1;
+        end
+        gpif_d_in <= gpif_d;
+        tx_valid <= 1;
+        transfer_count <= transfer_count + 1;
+    end
+
+    STATE_CTRL_RX: begin
+        if (FX2_CF_pre || ~resp_valid || resp_eof || transfer_count == CTRL_XFER_COUNT-1) begin
+            state <= STATE_IDLE;
+            resp_enable <= 0;
+        end
+        pktend <= ~resp_eof;
+        gpif_d_out <= gpif_d_out_ctrl;
+        slwr <= ~resp_valid;
+        transfer_count <= transfer_count + 1;
+    end
+
+    STATE_CTRL_TX: begin
+        if (FX2_CE_pre || transfer_count == CTRL_XFER_COUNT-1) begin
+            state <= STATE_IDLE;
+            slrd <= 1;
+        end
+        gpif_d_in <= gpif_d;
+        ctrl_valid <= 1;
+        transfer_count <= transfer_count + 1;
+    end
+    endcase
 
-   // ////////////////////////////////////////////////////////////////////
-   // set GPIF pins
-
-   //set fifoadr to the appropriate endpoint
-   // {0,0}: EP2, data TX from host
-   // {0,1}: EP4, ctrl TX from host
-   // {1,0}: EP6, data RX to host
-   // {1,1}: EP8, ctrl RX to host
-   assign fifoadr = {(state == STATE_DATA_RX) | (state == STATE_CTRL_RX) | (state == STATE_DATA_RX_ADR) | (state == STATE_CTRL_RX_ADR) | (state == STATE_PKTEND) | (state == STATE_PKTEND_ADR),
-                     (state == STATE_CTRL_RX) | (state == STATE_CTRL_RX_ADR) | (state == STATE_CTRL_TX) | (state == STATE_CTRL_TX_SLOE)};
-   //set sloe, slwr, slrd (all active low)
-   //SLOE gets asserted when we want data from the FX2; i.e., TX mode
-   assign sloe = ~{(state == STATE_DATA_TX) | (state == STATE_CTRL_TX) | (state == STATE_DATA_TX_SLOE) | (state == STATE_CTRL_TX_SLOE)};
-   //"read" and "write" here are from the master's point of view;
-   //so "read" means "transmit" and "write" means "receive"
-   assign slwr = ~{(data_rx_src_rdy && data_rx_dst_rdy) || (ctrl_rx_src_rdy && ctrl_rx_dst_rdy)};
-   assign slrd = ~{(data_tx_src_rdy && data_tx_dst_rdy) || (ctrl_tx_src_rdy && ctrl_tx_dst_rdy)};
-
-   wire pktend_ctrl, pktend_data;
-   assign pktend_ctrl = ((~ctrl_rx_src_rdy | gpif_d_out_ctrl[17]) & (state == STATE_CTRL_RX));
-   assign pktend_data = (state == STATE_PKTEND);
-   assign pktend = ~(pktend_ctrl | pktend_data);
-
-   //mux between ctrl/data RX data out based on endpoint selection
-   assign gpif_d_out = fifoadr[0] ? gpif_d_out_ctrl : gpif_d_out_data;
    // GPIF output data lines, tristate
-   assign gpif_d = sloe ? gpif_d_out : 16'bz;
+   assign gpif_d = (sloe)? gpif_d_out[15:0] : 16'bz;
    
    // ////////////////////////////////////////////////////////////////////
    // TX Data Path
 
-   wire [15:0] 	  txfifo_data;
-   wire 	  txfifo_src_rdy, txfifo_dst_rdy;
-   wire [35:0] 	  tx36_data;
-   wire 	  tx36_src_rdy, tx36_dst_rdy;
-   wire [15:0]    data_tx_2clk;
-   wire           tx_src_rdy_2clk, tx_dst_rdy_2clk;
-   
-   wire [15:0] wr_fifo_space;
-
-   always @(posedge gpif_clk)
-     tx_data_enough_space <= (wr_fifo_space >= data_transfer_size);
-
-   fifo_cascade #(.WIDTH(16), .SIZE(12)) wr_fifo
-     (.clk(gpif_clk), .reset(gpif_rst), .clear(clear_tx),
-      .datain(gpif_d), .src_rdy_i(data_tx_src_rdy), .dst_rdy_o(data_tx_dst_rdy), .space(wr_fifo_space),
-      .dataout(txfifo_data), .src_rdy_o(txfifo_src_rdy), .dst_rdy_i(txfifo_dst_rdy), .occupied());
-   
-   fifo_2clock_cascade #(.WIDTH(16), .SIZE(4)) wr_fifo_2clk
-     (.wclk(gpif_clk), .datain(txfifo_data), .src_rdy_i(txfifo_src_rdy), .dst_rdy_o(txfifo_dst_rdy), .space(),
-      .rclk(fifo_clk), .dataout(data_tx_2clk), .src_rdy_o(tx_src_rdy_2clk), .dst_rdy_i(tx_dst_rdy_2clk), .occupied(),
-      .arst(fifo_rst));
-
-   // join vita packets which are longer than one frame, add SOP/EOP/OCC
-   wire [18:0] 	  refr_data;
-   wire 	  refr_src_rdy, refr_dst_rdy;
-   //below 3 signals for debug only
-   wire refr_state;
-   wire refr_eof;
-   wire [15:0] refr_len;
-   
-   packet_reframer tx_packet_reframer 
-     (.clk(fifo_clk), .reset(fifo_rst), .clear(clear_tx),
-      .data_i(data_tx_2clk), .src_rdy_i(tx_src_rdy_2clk), .dst_rdy_o(tx_dst_rdy_2clk),
-      .data_o(refr_data), .src_rdy_o(refr_src_rdy), .dst_rdy_i(refr_dst_rdy),
-      .state(refr_state), .eof_out(refr_eof), .length(refr_len));
-
-   fifo19_to_fifo36 #(.LE(1)) f19_to_f36
-     (.clk(fifo_clk), .reset(fifo_rst), .clear(clear_tx),
-      .f19_datain(refr_data), .f19_src_rdy_i(refr_src_rdy), .f19_dst_rdy_o(refr_dst_rdy),
-      .f36_dataout(tx36_data), .f36_src_rdy_o(tx36_src_rdy), .f36_dst_rdy_i(tx36_dst_rdy));
-   
-   fifo_cascade #(.WIDTH(36), .SIZE(TXFIFOSIZE)) tx_fifo36
-     (.clk(fifo_clk), .reset(fifo_rst), .clear(clear_tx),
-      .datain(tx36_data), .src_rdy_i(tx36_src_rdy), .dst_rdy_o(tx36_dst_rdy),
-      .dataout(tx_data_o), .src_rdy_o(tx_src_rdy_o), .dst_rdy_i(tx_dst_rdy_i));
+    gpmc16_to_fifo36 #(.FIFO_SIZE(DATA_TX_FIFO_SIZE), .MIN_SPACE16(DATA_XFER_COUNT)) fifo36_to_gpmc16_tx(
+        .gpif_clk(gpif_clk), .gpif_rst(gpif_rst),
+        .in_data(gpif_d_in), .ready(tx_ready), .valid(tx_valid),
+        .fifo_clk(fifo_clk), .fifo_rst(fifo_rst),
+        .out_data(tx_data), .out_src_rdy(tx_src_rdy), .out_dst_rdy(tx_dst_rdy)
+    );
 
    // ////////////////////////////////////////////
    // RX Data Path
 
-   wire [35:0] 	  rx36_data;
-   wire 	  rx36_src_rdy, rx36_dst_rdy;
-   wire [18:0] 	  rx19_data;
-   wire 	  rx19_src_rdy, rx19_dst_rdy;
-   wire [15:0] rxfifospace;
-
-   //deep 36 bit wide input fifo buffers from DSP
-   fifo_cascade #(.WIDTH(36), .SIZE(9)) rx_fifo36
-     (.clk(fifo_clk), .reset(fifo_rst), .clear(clear_rx),
-      .datain(rx_data_i), .src_rdy_i(rx_src_rdy_i), .dst_rdy_o(rx_dst_rdy_o),
-      .dataout(rx36_data), .src_rdy_o(rx36_src_rdy), .dst_rdy_i(rx36_dst_rdy));
-
-   //convert to fifo19
-   fifo36_to_fifo19 #(.LE(1)) f36_to_f19
-     (.clk(fifo_clk), .reset(fifo_rst), .clear(clear_rx),
-      .f36_datain(rx36_data), .f36_src_rdy_i(rx36_src_rdy), .f36_dst_rdy_o(rx36_dst_rdy),
-      .f19_dataout(rx19_data), .f19_src_rdy_o(rx19_src_rdy), .f19_dst_rdy_i(rx19_dst_rdy) );
-
-   wire [18:0] 	data_rx_int;
-   wire 	rx_src_rdy_int, rx_dst_rdy_int;
-   //clock domain crossing fifo for RX data
-   fifo_2clock_cascade #(.WIDTH(19), .SIZE(4)) rd_fifo_2clk
-     (.wclk(fifo_clk), .datain(rx19_data), .src_rdy_i(rx19_src_rdy), .dst_rdy_o(rx19_dst_rdy), .space(),
-      .rclk(~gpif_clk), .dataout(data_rx_int), .src_rdy_o(rx_src_rdy_int), .dst_rdy_i(rx_dst_rdy_int), .occupied(),
-      .arst(fifo_rst));
-
-   //rd_fifo buffers writes to the 2clock fifo above
-   fifo_cascade #(.WIDTH(18), .SIZE(RXFIFOSIZE)) rd_fifo
-     (.clk(~gpif_clk), .reset(gpif_rst), .clear(clear_rx),
-      .datain(data_rx_int[17:0]), .src_rdy_i(rx_src_rdy_int), .dst_rdy_o(rx_dst_rdy_int), .space(rxfifospace),
-      .dataout(gpif_d_out_data), .src_rdy_o(data_rx_src_rdy), .dst_rdy_i(data_rx_dst_rdy), .occupied());
+    fifo36_to_gpmc16 #(.FIFO_SIZE(DATA_RX_FIFO_SIZE)) fifo36_to_gpmc16_rx(
+        .fifo_clk(fifo_clk), .fifo_rst(fifo_rst),
+        .in_data(rx_data), .in_src_rdy(rx_src_rdy), .in_dst_rdy(rx_dst_rdy),
+        .gpif_clk(gpif_clk), .gpif_rst(gpif_rst),
+        .out_data(gpif_d_out_data), .valid(rx_valid), .enable(rx_enable)
+    );
 
    // ////////////////////////////////////////////////////////////////////
-   // FIFO to Wishbone interface
+   // CTRL TX Data Path
 
-   wire [18:0] 	  resp_data, resp_int;
-   wire 	  resp_src_rdy, resp_dst_rdy;
-   wire 	  resp_src_rdy_int, resp_dst_rdy_int;
-   
-   wire [18:0] 	  tx_err19_data;
-   wire 	  tx_err19_src_rdy, tx_err19_dst_rdy;
-
-   wire [18:0] 	  ctrl_data;
-   wire 	  ctrl_src_rdy, ctrl_dst_rdy;
-
-   fifo_to_wb fifo_to_wb
-     (.clk(fifo_clk), .reset(fifo_rst), .clear(0),
-      .data_i(ctrl_data), .src_rdy_i(ctrl_src_rdy), .dst_rdy_o(ctrl_dst_rdy),
-      .data_o(resp_int), .src_rdy_o(resp_src_rdy_int), .dst_rdy_i(resp_dst_rdy_int),
-      .wb_adr_o(wb_adr_o), .wb_dat_mosi(wb_dat_mosi), .wb_dat_miso(wb_dat_miso), .wb_sel_o(wb_sel_o), 
-      .wb_cyc_o(wb_cyc_o), .wb_stb_o(wb_stb_o), .wb_we_o(wb_we_o), .wb_ack_i(wb_ack_i),
-      .triggers(triggers),
-      .debug0(), .debug1());
-      
-   // ////////////////////////////////////////////////////////////////////
-   // TX CTRL PATH (ctrl commands into Wishbone)
+    gpmc16_to_fifo36 #(.FIFO_SIZE(CTRL_TX_FIFO_SIZE), .MIN_SPACE16(CTRL_XFER_COUNT)) fifo36_to_gpmc16_ctrl(
+        .gpif_clk(gpif_clk), .gpif_rst(gpif_rst),
+        .in_data(gpif_d_in), .ready(ctrl_ready), .valid(ctrl_valid),
+        .fifo_clk(fifo_clk), .fifo_rst(fifo_rst),
+        .out_data(ctrl_data), .out_src_rdy(ctrl_src_rdy), .out_dst_rdy(ctrl_dst_rdy)
+    );
 
-   //how does this use fifo_clk instead of wb_clk
-   //answer: on b100 fifo clk IS wb clk
-   fifo_2clock_cascade #(.WIDTH(19), .SIZE(4)) ctrl_fifo_2clk
-     (.wclk(gpif_clk), .datain({1'b0,eop_ctrl,sop_ctrl,gpif_d}), 
-      .src_rdy_i(ctrl_tx_src_rdy), .dst_rdy_o(ctrl_tx_dst_rdy), .space(),
-      .rclk(fifo_clk), .dataout(ctrl_data), 
-      .src_rdy_o(ctrl_src_rdy), .dst_rdy_i(ctrl_dst_rdy), .occupied(),
-      .arst(fifo_rst));
+   // ////////////////////////////////////////////
+   // CTRL RX Data Path
+
+    fifo36_to_gpmc16 #(.FIFO_SIZE(CTRL_RX_FIFO_SIZE)) fifo36_to_gpmc16_resp(
+        .fifo_clk(fifo_clk), .fifo_rst(fifo_rst),
+        .in_data(resp_data), .in_src_rdy(resp_src_rdy), .in_dst_rdy(resp_dst_rdy),
+        .gpif_clk(gpif_clk), .gpif_rst(gpif_rst),
+        .out_data(gpif_d_out_ctrl), .valid(resp_valid), .enable(resp_enable),
+        .eof(resp_eof)
+    );
 
-   // ////////////////////////////////////////////////////////////////////
-   // RX CTRL PATH (async packets, ctrl response data)
-   
-   //tx_err_data_i is the 36wide tx async err data clocked on fifo_clk
-   fifo36_to_fifo19 #(.LE(1)) f36_to_f19_txerr
-     (.clk(fifo_clk), .reset(fifo_rst), .clear(clear_rx),
-      .f36_datain(tx_err_data_i), .f36_src_rdy_i(tx_err_src_rdy_i), .f36_dst_rdy_o(tx_err_dst_rdy_o),
-      .f19_dataout(tx_err19_data), .f19_src_rdy_o(tx_err19_src_rdy), .f19_dst_rdy_i(tx_err19_dst_rdy) );
-
-   //mux FIFO-to-WB along with async tx err pkts into one ctrl resp fifo
-   //how is this clocked on wb_clk?
-   fifo19_mux #(.prio(0)) mux_err_stream
-     (.clk(wb_clk), .reset(wb_rst), .clear(clear_rx),
-      .data0_i(resp_int), .src0_rdy_i(resp_src_rdy_int), .dst0_rdy_o(resp_dst_rdy_int),
-      .data1_i(tx_err19_data), .src1_rdy_i(tx_err19_src_rdy), .dst1_rdy_o(tx_err19_dst_rdy),
-      .data_o(resp_data), .src_rdy_o(resp_src_rdy), .dst_rdy_i(resp_dst_rdy));
-
-   //clock domain crossing cascade fifo for mux_err_stream to get from wb_clk to gpif_clk
-   //the output of this fifo is CTRL DATA PENDING FOR GPIF
-   fifo_2clock_cascade #(.WIDTH(18), .SIZE(4)) resp_fifo_2clk
-     (.wclk(wb_clk), .datain(resp_data[17:0]), .src_rdy_i(resp_src_rdy), .dst_rdy_o(resp_dst_rdy), .space(),
-      .rclk(~gpif_clk), .dataout(gpif_d_out_ctrl), 
-      .src_rdy_o(ctrl_rx_src_rdy), .dst_rdy_i(ctrl_rx_dst_rdy), .occupied(),
-      .arst(wb_rst));
-
-        
-   // ////////////////////////////////////////////////////////////////////
-   // Debug support, timed and loopback
-   // RX side muxes test data into the same stream
+    assign debug = 0;
 
-   ///////////////////////////////////////////////////////////////////////
-   // debug lines
-   wire [31:0] 	  debug_rd, debug_wr, debug_split0, debug_split1;
-   
-   wire [35:0] 	timedrx_data, loopbackrx_data, testrx_data;
-   wire [35:0] 	timedtx_data, loopbacktx_data, testtx_data;
-   wire 	timedrx_src_rdy, timedrx_dst_rdy, loopbackrx_src_rdy, loopbackrx_dst_rdy,
-		testrx_src_rdy, testrx_dst_rdy;
-   wire 	timedtx_src_rdy, timedtx_dst_rdy, loopbacktx_src_rdy, loopbacktx_dst_rdy,
-		testtx_src_rdy, testtx_dst_rdy;
-   wire 	timedrx_src_rdy_int, timedrx_dst_rdy_int, timedtx_src_rdy_int, timedtx_dst_rdy_int;
-
-   wire [31:0] 	total, crc_err, seq_err, len_err;
-   wire 	sel_testtx = test_ctrl[0];
-   wire 	sel_loopbacktx = test_ctrl[1];
-   wire 	pkt_src_enable = test_ctrl[2];
-   wire 	pkt_sink_enable = test_ctrl[3];
-/*   
-   fifo36_mux rx_test_mux_lvl_1
-     (.clk(fifo_clk), .reset(fifo_rst), .clear(clear_rx),
-      .data0_i(timedrx_data), .src0_rdy_i(timedrx_src_rdy), .dst0_rdy_o(timedrx_dst_rdy),
-      .data1_i(loopbackrx_data), .src1_rdy_i(loopbackrx_src_rdy), .dst1_rdy_o(loopbackrx_dst_rdy),
-      .data_o(testrx_data), .src_rdy_o(testrx_src_rdy), .dst_rdy_i(testrx_dst_rdy));
-   
-   fifo36_mux rx_test_mux_lvl_2
-     (.clk(fifo_clk), .reset(fifo_rst), .clear(clear_rx),
-      .data0_i(testrx_data), .src0_rdy_i(testrx_src_rdy), .dst0_rdy_o(testrx_dst_rdy),
-      .data1_i(rx_data_i), .src1_rdy_i(rx_src_rdy_i), .dst1_rdy_o(rx_dst_rdy_o),
-      .data_o(rx_data), .src_rdy_o(rx_src_rdy), .dst_rdy_i(rx_dst_rdy));
-   
-   fifo_short #(.WIDTH(36)) loopback_fifo
-     (.clk(fifo_clk), .reset(fifo_rst), .clear(clear_tx | clear_rx),
-      .datain(loopbacktx_data), .src_rdy_i(loopbacktx_src_rdy), .dst_rdy_o(loopbacktx_dst_rdy),
-      .dataout(loopbackrx_data), .src_rdy_o(loopbackrx_src_rdy), .dst_rdy_i(loopbackrx_dst_rdy));
-   
-   // Crossbar used as a demux for switching TX stream to main DSP or to test logic
-   crossbar36 tx_crossbar_lvl_1
-     (.clk(fifo_clk), .reset(fifo_rst), .clear(clear_tx),
-      .cross(sel_testtx),
-      .data0_i(tx_data), .src0_rdy_i(tx_src_rdy), .dst0_rdy_o(tx_dst_rdy),
-      .data1_i(tx_data), .src1_rdy_i(1'b0), .dst1_rdy_o(),  // No 2nd input
-      .data0_o(tx_data_o), .src0_rdy_o(tx_src_rdy_o), .dst0_rdy_i(tx_dst_rdy_i),
-      .data1_o(testtx_data), .src1_rdy_o(testtx_src_rdy), .dst1_rdy_i(testtx_dst_rdy) );
-   
-   crossbar36 tx_crossbar_lvl_2
-     (.clk(fifo_clk), .reset(fifo_rst), .clear(clear_tx),
-      .cross(sel_loopbacktx),
-      .data0_i(testtx_data), .src0_rdy_i(testtx_src_rdy), .dst0_rdy_o(testtx_dst_rdy),
-      .data1_i(testtx_data), .src1_rdy_i(1'b0), .dst1_rdy_o(),  // No 2nd input
-      .data0_o(timedtx_data), .src0_rdy_o(timedtx_src_rdy), .dst0_rdy_i(timedtx_dst_rdy),
-      .data1_o(loopbacktx_data), .src1_rdy_o(loopbacktx_src_rdy), .dst1_rdy_i(loopbacktx_dst_rdy) );
-   
-   // Fixed rate TX traffic consumer
-   fifo_pacer tx_pacer
-     (.clk(fifo_clk), .reset(fifo_rst), .rate(test_rate), .enable(pkt_sink_enable),
-      .src1_rdy_i(timedtx_src_rdy), .dst1_rdy_o(timedtx_dst_rdy),
-      .src2_rdy_o(timedtx_src_rdy_int), .dst2_rdy_i(timedtx_dst_rdy_int),
-      .underrun(tx_underrun), .overrun());
-
-   packet_verifier32 pktver32
-     (.clk(fifo_clk), .reset(fifo_rst), .clear(clear_tx),
-      .data_i(timedtx_data), .src_rdy_i(timedtx_src_rdy_int), .dst_rdy_o(timedtx_dst_rdy_int),
-      .total(total), .crc_err(crc_err), .seq_err(seq_err), .len_err(len_err));
-
-   // Fixed rate RX traffic generator
-   vita_pkt_gen pktgen
-     (.clk(fifo_clk), .reset(fifo_rst), .clear(clear_rx),
-      .len(test_len),
-      .data_o(timedrx_data), .src_rdy_o(timedrx_src_rdy_int), .dst_rdy_i(timedrx_dst_rdy_int));
-
-   fifo_pacer rx_pacer
-     (.clk(fifo_clk), .reset(fifo_rst), .rate(test_rate), .enable(pkt_src_enable),
-      .src1_rdy_i(timedrx_src_rdy_int), .dst1_rdy_o(timedrx_dst_rdy_int),
-      .src2_rdy_o(timedrx_src_rdy), .dst2_rdy_i(timedrx_dst_rdy),
-      .underrun(), .overrun(rx_overrun));
-*/
-   // ////////////////////////////////////////////
-   //    DEBUG
-   
-   assign debug0 = { pktend_latch, data_rx_src_rdy, gpif_ctl[3:0], sloe, slrd, slwr, pktend, fifoadr[1:0], state[3:0], gpif_d[15:0]};
-   //assign debug0 = { data_tx_src_rdy, data_tx_dst_rdy, tx_src_rdy_int, tx_dst_rdy_int, 
-   //                  tx19_src_rdy, tx19_dst_rdy, refr_src_rdy, refr_dst_rdy, 
-   //                  tx36_src_rdy, tx36_dst_rdy,
-   //                  gpif_ctl[3:0], fifoadr[1:0], 
-   //                  wr_fifo_space[15:0]};
-   assign debug1 = { 16'b0, transfer_count[7:0], ctrl_rx_src_rdy, ctrl_tx_dst_rdy, data_rx_src_rdy,
-                     data_tx_dst_rdy, ctrl_tx_src_rdy, ctrl_rx_dst_rdy, data_tx_src_rdy, data_rx_dst_rdy};
 endmodule // slave_fifo
diff --git a/fpga/usrp2/gpmc/Makefile.srcs b/fpga/usrp2/gpmc/Makefile.srcs
index 4c6a1b4a2..39b37db58 100644
--- a/fpga/usrp2/gpmc/Makefile.srcs
+++ b/fpga/usrp2/gpmc/Makefile.srcs
@@ -1,5 +1,5 @@
 #
-# Copyright 2010-2011 Ettus Research LLC
+# Copyright 2010-2012 Ettus Research LLC
 #
 
 ##################################################
@@ -10,5 +10,4 @@ cross_clock_reader.v \
 fifo_to_gpmc.v \
 gpmc.v \
 gpmc_to_fifo.v \
-gpmc_wb.v \
 ))
diff --git a/fpga/usrp2/gpmc/cross_clock_reader.v b/fpga/usrp2/gpmc/cross_clock_reader.v
index a8366badc..b4cdb79c5 100644
--- a/fpga/usrp2/gpmc/cross_clock_reader.v
+++ b/fpga/usrp2/gpmc/cross_clock_reader.v
@@ -27,18 +27,20 @@ module cross_clock_reader
     );
 
     reg [WIDTH-1:0] shadow0, shadow1;
+    reg [2:0] count;
 
     always @(posedge clk) begin
         if (rst) begin
             out <= DEFAULT;
             shadow0 <= DEFAULT;
             shadow1 <= DEFAULT;
+            count <= 0;
         end
-        else if (shadow0 == shadow1) begin
-            out <= shadow1;
-        end
+        else if (shadow0 == shadow1) count <= count + 1;
+        else count <= 0;
         shadow0 <= in;
         shadow1 <= shadow0;
+        if (count == 3'b111) out <= shadow1;
     end
 
 endmodule //cross_clock_reader
diff --git a/fpga/usrp2/gpmc/fifo_to_gpmc.v b/fpga/usrp2/gpmc/fifo_to_gpmc.v
index 42c71d2d6..26443a702 100644
--- a/fpga/usrp2/gpmc/fifo_to_gpmc.v
+++ b/fpga/usrp2/gpmc/fifo_to_gpmc.v
@@ -1,5 +1,5 @@
 //
-// Copyright 2011 Ettus Research LLC
+// Copyright 2011-2012 Ettus Research LLC
 //
 // This program is free software: you can redistribute it and/or modify
 // it under the terms of the GNU General Public License as published by
@@ -39,7 +39,7 @@
 ////////////////////////////////////////////////////////////////////////
 
 module fifo_to_gpmc
-  #(parameter PTR_WIDTH = 2, parameter ADDR_WIDTH = 10)
+  #(parameter PTR_WIDTH = 2, parameter ADDR_WIDTH = 10, parameter LAST_ADDR = 10'h3ff)
   (input clk, input reset, input clear, input arst,
    input [17:0] data_i, input src_rdy_i, output dst_rdy_o,
    output [15:0] EM_D, input [ADDR_WIDTH:1] EM_A, input EM_CLK, input EM_OE,
@@ -82,14 +82,15 @@ module fifo_to_gpmc
             end
 
             GPMC_STATE_EMPTY: begin
-                if (EM_A == 10'h3ff) begin
+                if (addr == LAST_ADDR) begin
                     gpmc_state <= GPMC_STATE_START;
                     gpmc_ptr <= next_gpmc_ptr;
+                    addr <= 0;
                 end
             end
 
             endcase //gpmc_state
-        end //EM_WE
+        end //EM_OE
     end //always
 
     //------------------------------------------------------------------
diff --git a/fpga/usrp2/gpmc/gpmc.v b/fpga/usrp2/gpmc/gpmc.v
index a5d4db466..2ba69d184 100644
--- a/fpga/usrp2/gpmc/gpmc.v
+++ b/fpga/usrp2/gpmc/gpmc.v
@@ -1,5 +1,5 @@
 //
-// Copyright 2011 Ettus Research LLC
+// Copyright 2011-2012 Ettus Research LLC
 //
 // This program is free software: you can redistribute it and/or modify
 // it under the terms of the GNU General Public License as published by
@@ -18,7 +18,7 @@
 //////////////////////////////////////////////////////////////////////////////////
 
 module gpmc
-  #(parameter TXFIFOSIZE = 11, 
+  #(parameter TXFIFOSIZE = 11,
     parameter RXFIFOSIZE = 11,
     parameter ADDR_WIDTH = 10,
     parameter BUSDEBUG = 1)
@@ -26,57 +26,51 @@ module gpmc
     input arst,
     input EM_CLK, inout [15:0] EM_D, input [ADDR_WIDTH:1] EM_A, input [1:0] EM_NBE,
     input EM_WAIT0, input EM_NCS4, input EM_NCS6, input EM_NWE, input EM_NOE,
-    
+
     // GPIOs for FIFO signalling
-    output rx_have_data, output tx_have_space,
-    
-    // Wishbone signals
-    input wb_clk, input wb_rst,
-    output [ADDR_WIDTH:0] wb_adr_o, output [15:0] wb_dat_mosi, input [15:0] wb_dat_miso,
-    output [1:0] wb_sel_o, output wb_cyc_o, output wb_stb_o, output wb_we_o, input wb_ack_i,
-    
+    output rx_have_data, output tx_have_space, output resp_have_data,
+
     // FIFO interface
-    input fifo_clk, input fifo_rst, input clear_tx, input clear_rx,
-    output [35:0] tx_data_o, output tx_src_rdy_o, input tx_dst_rdy_i,
-    input [35:0] rx_data_i, input rx_src_rdy_i, output rx_dst_rdy_o,
+    input fifo_clk, input fifo_rst,
+    output [35:0] tx_data, output tx_src_rdy, input tx_dst_rdy,
+    input [35:0] rx_data, input rx_src_rdy, output rx_dst_rdy,
+    output [35:0] ctrl_data, output ctrl_src_rdy, input ctrl_dst_rdy,
+    input [35:0] resp_data, input resp_src_rdy, output resp_dst_rdy,
 
-    output tx_underrun, output rx_overrun,
-    input [7:0] test_rate, input [3:0] test_ctrl,
     output [31:0] debug
     );
 
-   wire 	  EM_output_enable = (~EM_NOE & (~EM_NCS4 | ~EM_NCS6));
-   wire [15:0] 	  EM_D_fifo;
-   wire [15:0] 	  EM_D_wb;
+   wire EM_output_enable = (~EM_NOE & (~EM_NCS4 | ~EM_NCS6));
+   wire [15:0] 	  EM_D_data;
+   wire [15:0] 	  EM_D_ctrl;
 
-   assign EM_D = ~EM_output_enable ? 16'bz : ~EM_NCS4 ? EM_D_fifo : EM_D_wb;
+   assign EM_D = ~EM_output_enable ? 16'bz : ~EM_NCS4 ? EM_D_data : EM_D_ctrl;
 
    // CS4 is RAM_2PORT for DATA PATH (high-speed data)
    //    Writes go into one RAM, reads come from the other
-   // CS6 is for CONTROL PATH (wishbone)
+   // CS6 is for CONTROL PATH (slow)
 
    // ////////////////////////////////////////////
    // TX Data Path
 
    wire [17:0] 	  tx18_data;
    wire 	  tx18_src_rdy, tx18_dst_rdy;
-   wire [35:0] 	  tx_data, txb_data;
-   wire 	  tx_src_rdy, tx_dst_rdy;
+   wire [35:0] 	  txb_data;
    wire 	  txb_src_rdy, txb_dst_rdy;
 
    gpmc_to_fifo #(.ADDR_WIDTH(ADDR_WIDTH)) gpmc_to_fifo
      (.EM_D(EM_D), .EM_A(EM_A), .EM_CLK(EM_CLK), .EM_WE(~EM_NCS4 & ~EM_NWE),
-      .clk(fifo_clk), .reset(fifo_rst), .clear(clear_tx), .arst(fifo_rst | clear_tx | arst),
+      .clk(fifo_clk), .reset(fifo_rst), .clear(1'b0), .arst(fifo_rst | arst),
       .data_o(tx18_data), .src_rdy_o(tx18_src_rdy), .dst_rdy_i(tx18_dst_rdy),
       .have_space(tx_have_space));
 
    fifo19_to_fifo36 #(.LE(1)) f19_to_f36   // Little endian because ARM is LE
-     (.clk(fifo_clk), .reset(fifo_rst), .clear(clear_tx),
+     (.clk(fifo_clk), .reset(fifo_rst), .clear(1'b0),
       .f19_datain({1'b0,tx18_data}), .f19_src_rdy_i(tx18_src_rdy), .f19_dst_rdy_o(tx18_dst_rdy),
       .f36_dataout(txb_data), .f36_src_rdy_o(txb_src_rdy), .f36_dst_rdy_i(txb_dst_rdy));
 
    fifo_cascade #(.WIDTH(36), .SIZE(TXFIFOSIZE)) tx_buffering(
-        .clk(fifo_clk), .reset(fifo_rst), .clear(clear_tx),
+        .clk(fifo_clk), .reset(fifo_rst), .clear(1'b0),
         .datain(txb_data), .src_rdy_i(txb_src_rdy), .dst_rdy_o(txb_dst_rdy),
         .dataout(tx_data), .src_rdy_o(tx_src_rdy), .dst_rdy_i(tx_dst_rdy)
    );
@@ -86,74 +80,88 @@ module gpmc
    
    wire [17:0] 	  rx18_data;
    wire 	  rx18_src_rdy, rx18_dst_rdy;
-   wire [35:0] 	  rx_data, rxb_data;
-   wire 	  rx_src_rdy, rx_dst_rdy;
+   wire [35:0] 	  rxb_data;
    wire 	  rxb_src_rdy, rxb_dst_rdy;
    wire 	  dummy;
 
    fifo_cascade #(.WIDTH(36), .SIZE(RXFIFOSIZE)) rx_buffering(
-        .clk(fifo_clk), .reset(fifo_rst), .clear(clear_rx),
+        .clk(fifo_clk), .reset(fifo_rst), .clear(1'b0),
         .datain(rx_data), .src_rdy_i(rx_src_rdy), .dst_rdy_o(rx_dst_rdy),
         .dataout(rxb_data), .src_rdy_o(rxb_src_rdy), .dst_rdy_i(rxb_dst_rdy)
    );
 
    fifo36_to_fifo19 #(.LE(1)) f36_to_f19   // Little endian because ARM is LE
-     (.clk(fifo_clk), .reset(fifo_rst), .clear(clear_rx),
+     (.clk(fifo_clk), .reset(fifo_rst), .clear(1'b0),
       .f36_datain(rxb_data), .f36_src_rdy_i(rxb_src_rdy), .f36_dst_rdy_o(rxb_dst_rdy),
       .f19_dataout({dummy,rx18_data}), .f19_src_rdy_o(rx18_src_rdy), .f19_dst_rdy_i(rx18_dst_rdy) );
 
-   fifo_to_gpmc #(.ADDR_WIDTH(ADDR_WIDTH)) fifo_to_gpmc
-     (.clk(fifo_clk), .reset(fifo_rst), .clear(clear_rx), .arst(fifo_rst | clear_rx | arst),
+   fifo_to_gpmc #(.ADDR_WIDTH(ADDR_WIDTH), .LAST_ADDR(10'h3ff)) fifo_to_gpmc
+     (.clk(fifo_clk), .reset(fifo_rst), .clear(1'b0), .arst(fifo_rst | arst),
       .data_i(rx18_data), .src_rdy_i(rx18_src_rdy), .dst_rdy_o(rx18_dst_rdy),
-      .EM_D(EM_D_fifo), .EM_A(EM_A), .EM_CLK(EM_CLK), .EM_OE(~EM_NCS4 & ~EM_NOE),
+      .EM_D(EM_D_data), .EM_A(EM_A), .EM_CLK(EM_CLK), .EM_OE(~EM_NCS4 & ~EM_NOE),
       .data_available(rx_have_data));
 
    // ////////////////////////////////////////////
    // Control path on CS6
-   
-   gpmc_wb gpmc_wb
-     (.EM_CLK(EM_CLK), .EM_D_in(EM_D), .EM_D_out(EM_D_wb), .EM_A(EM_A), .EM_NBE(EM_NBE),
-      .EM_WE(~EM_NCS6 & ~EM_NWE), .EM_OE(~EM_NCS6 & ~EM_NOE),
-      .wb_clk(wb_clk), .wb_rst(wb_rst),
-      .wb_adr_o(wb_adr_o), .wb_dat_mosi(wb_dat_mosi), .wb_dat_miso(wb_dat_miso),
-      .wb_sel_o(wb_sel_o), .wb_cyc_o(wb_cyc_o), .wb_stb_o(wb_stb_o), .wb_we_o(wb_we_o),
-      .wb_ack_i(wb_ack_i) );
+
+   // ////////////////////////////////////////////////////////////////////
+   // CTRL TX Data Path
+
+   wire [17:0] 	  ctrl18_data;
+   wire 	  ctrl18_src_rdy, ctrl18_dst_rdy;
+   wire [35:0] 	  ctrlb_data;
+   wire 	  ctrlb_src_rdy, ctrlb_dst_rdy;
+
+   gpmc_to_fifo #(.PTR_WIDTH(5), .ADDR_WIDTH(5)) ctrl_gpmc_to_fifo
+     (.EM_D(EM_D), .EM_A(EM_A[5:1]), .EM_CLK(EM_CLK), .EM_WE(~EM_NCS6 & ~EM_NWE & (EM_A[ADDR_WIDTH:6] == 0)),
+      .clk(fifo_clk), .reset(fifo_rst), .clear(1'b0), .arst(fifo_rst | arst),
+      .data_o(ctrl18_data), .src_rdy_o(ctrl18_src_rdy), .dst_rdy_i(ctrl18_dst_rdy),
+      .have_space(/*always*/));
+
+   fifo19_to_fifo36 #(.LE(1)) ctrl_f19_to_f36   // Little endian because ARM is LE
+     (.clk(fifo_clk), .reset(fifo_rst), .clear(1'b0),
+      .f19_datain({1'b0,ctrl18_data}), .f19_src_rdy_i(ctrl18_src_rdy), .f19_dst_rdy_o(ctrl18_dst_rdy),
+      .f36_dataout(ctrlb_data), .f36_src_rdy_o(ctrlb_src_rdy), .f36_dst_rdy_i(ctrlb_dst_rdy));
+
+   fifo_cascade #(.WIDTH(36), .SIZE(9)) ctrl_buffering(
+        .clk(fifo_clk), .reset(fifo_rst), .clear(1'b0),
+        .datain(ctrlb_data), .src_rdy_i(ctrlb_src_rdy), .dst_rdy_o(ctrlb_dst_rdy),
+        .dataout(ctrl_data), .src_rdy_o(ctrl_src_rdy), .dst_rdy_i(ctrl_dst_rdy)
+   );
 
    // ////////////////////////////////////////////
-   // Test support, traffic generator, loopback, etc.
-
-   // RX side muxes test data into the same stream
-   wire [35:0] loopbackrx_data, testrx_data;
-   wire [35:0] loopbacktx_data, testtx_data;
-   wire        loopbackrx_src_rdy, loopbackrx_dst_rdy;
-   wire        loopbacktx_src_rdy, loopbacktx_dst_rdy;
-   wire        sel_testtx = test_ctrl[0];
-
-   fifo36_mux rx_test_mux_lvl_2
-     (.clk(fifo_clk), .reset(fifo_rst), .clear(clear_rx),
-      .data0_i(loopbackrx_data), .src0_rdy_i(loopbackrx_src_rdy), .dst0_rdy_o(loopbackrx_dst_rdy),
-      .data1_i(rx_data_i), .src1_rdy_i(rx_src_rdy_i), .dst1_rdy_o(rx_dst_rdy_o),
-      .data_o(rx_data), .src_rdy_o(rx_src_rdy), .dst_rdy_i(rx_dst_rdy));
-
-   fifo_short #(.WIDTH(36)) loopback_fifo
-     (.clk(fifo_clk), .reset(fifo_rst), .clear(clear_tx | clear_rx),
-      .datain(loopbacktx_data), .src_rdy_i(loopbacktx_src_rdy), .dst_rdy_o(loopbacktx_dst_rdy),
-      .dataout(loopbackrx_data), .src_rdy_o(loopbackrx_src_rdy), .dst_rdy_i(loopbackrx_dst_rdy));
-
-   // Crossbar used as a demux for switching TX stream to main DSP or to test logic
-   crossbar36 tx_crossbar_lvl_1
-     (.clk(fifo_clk), .reset(fifo_rst), .clear(clear_tx),
-      .cross(sel_testtx),
-      .data0_i(tx_data), .src0_rdy_i(tx_src_rdy), .dst0_rdy_o(tx_dst_rdy),
-      .data1_i(tx_data), .src1_rdy_i(1'b0), .dst1_rdy_o(),  // No 2nd input
-      .data0_o(tx_data_o), .src0_rdy_o(tx_src_rdy_o), .dst0_rdy_i(tx_dst_rdy_i),
-      .data1_o(loopbacktx_data), .src1_rdy_o(loopbacktx_src_rdy), .dst1_rdy_i(loopbacktx_dst_rdy) );
-
-   assign debug = {
-        EM_D, //16
+   // CTRL RX Data Path
+
+   wire [17:0] 	  resp18_data;
+   wire 	  resp18_src_rdy, resp18_dst_rdy;
+   wire [35:0] 	  respb_data;
+   wire 	  respb_src_rdy, respb_dst_rdy;
+   wire 	  resp_dummy;
+
+   fifo_cascade #(.WIDTH(36), .SIZE(9)) resp_buffering(
+        .clk(fifo_clk), .reset(fifo_rst), .clear(1'b0),
+        .datain(resp_data), .src_rdy_i(resp_src_rdy), .dst_rdy_o(resp_dst_rdy),
+        .dataout(respb_data), .src_rdy_o(respb_src_rdy), .dst_rdy_i(respb_dst_rdy)
+   );
+
+   fifo36_to_fifo19 #(.LE(1)) resp_f36_to_f19   // Little endian because ARM is LE
+     (.clk(fifo_clk), .reset(fifo_rst), .clear(1'b0),
+      .f36_datain(respb_data), .f36_src_rdy_i(respb_src_rdy), .f36_dst_rdy_o(respb_dst_rdy),
+      .f19_dataout({resp_dummy,resp18_data}), .f19_src_rdy_o(resp18_src_rdy), .f19_dst_rdy_i(resp18_dst_rdy) );
+
+   fifo_to_gpmc #(.ADDR_WIDTH(ADDR_WIDTH), .LAST_ADDR(10'h00f)) resp_fifo_to_gpmc
+     (.clk(fifo_clk), .reset(fifo_rst), .clear(1'b0), .arst(fifo_rst | arst),
+      .data_i(resp18_data), .src_rdy_i(resp18_src_rdy), .dst_rdy_o(resp18_dst_rdy),
+      .EM_D(EM_D_ctrl), .EM_A(EM_A), .EM_CLK(EM_CLK), .EM_OE(~EM_NCS6 & ~EM_NOE),
+      .data_available(resp_have_data));
+
+    assign debug = {
+        EM_D,
+        //resp18_data[15:0], //16
         EM_A, //10
-        EM_CLK, EM_NCS4, EM_NWE, EM_NOE, //4
-        EM_NCS6, wb_ack_i
-   };
+        //resp18_data[17:16], resp18_src_rdy, resp18_dst_rdy, //4
+        EM_NCS4, EM_NCS6, EM_NWE, EM_NOE, //4
+        EM_CLK, resp_have_data //2
+    };
 
 endmodule // gpmc
diff --git a/fpga/usrp2/gpmc/gpmc_to_fifo.v b/fpga/usrp2/gpmc/gpmc_to_fifo.v
index cfc5aaa8b..3932b81ac 100644
--- a/fpga/usrp2/gpmc/gpmc_to_fifo.v
+++ b/fpga/usrp2/gpmc/gpmc_to_fifo.v
@@ -1,5 +1,5 @@
 //
-// Copyright 2011 Ettus Research LLC
+// Copyright 2011-2012 Ettus Research LLC
 //
 // This program is free software: you can redistribute it and/or modify
 // it under the terms of the GNU General Public License as published by
@@ -22,7 +22,7 @@
 // The GPMC is asynchronously alerted when a BRAM page is available.
 //
 // EM_CLK:
-// A GPMC read transaction consists of one EM_CLK cycle (idle low).
+// A GPMC write transaction consists of one EM_CLK cycle (idle low).
 //
 // EM_WE:
 // Write enable is actually the combination of ~NWE & ~NCS.
@@ -36,7 +36,7 @@
 ////////////////////////////////////////////////////////////////////////
 
 module gpmc_to_fifo
-  #(parameter PTR_WIDTH = 2, parameter ADDR_WIDTH = 10)
+  #(parameter PTR_WIDTH = 2, parameter ADDR_WIDTH = 10, parameter XFER_OFFSET = 2)
   (input [15:0] EM_D, input [ADDR_WIDTH:1] EM_A, input EM_CLK, input EM_WE,
    input clk, input reset, input clear, input arst,
    output [17:0] data_o, output src_rdy_o, input dst_rdy_i,
@@ -45,17 +45,20 @@ module gpmc_to_fifo
     //states for the GPMC side of things
     wire [17:0] data_i;
     reg gpmc_state;
-    reg [ADDR_WIDTH:1] last_addr;
+    reg [15:0] vita_len;
+    reg [ADDR_WIDTH:1] addr;
+    wire [ADDR_WIDTH:1] last_addr = {vita_len[ADDR_WIDTH-2:0], 1'b0} - 1'b1 + XFER_OFFSET;
     reg [PTR_WIDTH:0] gpmc_ptr, next_gpmc_ptr;
     localparam GPMC_STATE_START = 0;
     localparam GPMC_STATE_FILL = 1;
 
     //states for the FIFO side of things
-    reg fifo_state;
+    reg [1:0] fifo_state;
     reg [ADDR_WIDTH-1:0] counter;
     reg [PTR_WIDTH:0] fifo_ptr;
     localparam FIFO_STATE_CLAIM = 0;
     localparam FIFO_STATE_EMPTY = 1;
+    localparam FIFO_STATE_PRE = 2;
 
     //------------------------------------------------------------------
     // State machine to control the data from GPMC to BRAM
@@ -65,14 +68,16 @@ module gpmc_to_fifo
             gpmc_state <= GPMC_STATE_START;
             gpmc_ptr <= 0;
             next_gpmc_ptr <= 0;
+            addr <= 0;
         end
         else if (EM_WE) begin
+            addr <= EM_A + 1;
             case(gpmc_state)
 
             GPMC_STATE_START: begin
-                if (EM_A == 2) begin
+                if (data_i[16]) begin
                     gpmc_state <= GPMC_STATE_FILL;
-                    last_addr <= {EM_D[ADDR_WIDTH-2:0], 1'b0} - 1'b1 + 2;
+                    vita_len <= EM_D;
                     next_gpmc_ptr <= gpmc_ptr + 1;
                 end
             end
@@ -81,6 +86,7 @@ module gpmc_to_fifo
                 if (data_i[17]) begin
                     gpmc_state <= GPMC_STATE_START;
                     gpmc_ptr <= next_gpmc_ptr;
+                    addr <= 0;
                 end
             end
 
@@ -105,6 +111,7 @@ module gpmc_to_fifo
     cross_clock_reader #(.WIDTH(PTR_WIDTH+1)) read_next_gpmc_ptr
         (.clk(clk), .rst(reset | clear), .in(next_gpmc_ptr), .out(safe_next_gpmc_ptr));
 
+    wire [PTR_WIDTH:0] fifo_ptr_next = fifo_ptr + 1;
     always @(posedge clk)
         if (reset | clear) have_space <= 0;
         else               have_space <= (fifo_ptr ^ (1 << PTR_WIDTH)) != safe_next_gpmc_ptr;
@@ -116,22 +123,28 @@ module gpmc_to_fifo
         if (reset | clear) begin
             fifo_state <= FIFO_STATE_CLAIM;
             fifo_ptr <= 0;
-            counter <= 2;
+            counter <= XFER_OFFSET;
         end
         else begin
             case(fifo_state)
 
             FIFO_STATE_CLAIM: begin
-                if (bram_available_to_empty) fifo_state <= FIFO_STATE_EMPTY;
-                counter <= 2;
+                if (bram_available_to_empty && data_o[16]) fifo_state <= FIFO_STATE_PRE;
+                counter <= XFER_OFFSET;
+            end
+
+            FIFO_STATE_PRE: begin
+                fifo_state <= FIFO_STATE_EMPTY;
+                counter <= counter + 1;
             end
 
             FIFO_STATE_EMPTY: begin
                 if (src_rdy_o && dst_rdy_i && data_o[17]) begin
                     fifo_state <= FIFO_STATE_CLAIM;
                     fifo_ptr <= fifo_ptr + 1;
+                    counter <= XFER_OFFSET;
                 end
-                if (src_rdy_o && dst_rdy_i) begin
+                else if (src_rdy_o && dst_rdy_i) begin
                     counter <= counter + 1;
                 end
             end
@@ -140,18 +153,20 @@ module gpmc_to_fifo
         end
     end //always
 
+    wire enable = (fifo_state != FIFO_STATE_EMPTY) || dst_rdy_i;
+
     assign src_rdy_o = fifo_state == FIFO_STATE_EMPTY;
 
     //assign data and frame bits to bram input
     assign data_i[15:0] = EM_D;
-    assign data_i[16] = (gpmc_state == GPMC_STATE_START);
-    assign data_i[17] = (EM_A == last_addr);
+    assign data_i[16] = (addr == XFER_OFFSET);
+    assign data_i[17] = (addr == last_addr);
 
     //instantiate dual ported bram for async read + write
     ram_2port #(.DWIDTH(18),.AWIDTH(PTR_WIDTH + ADDR_WIDTH)) async_fifo_bram
      (.clka(~EM_CLK),.ena(1'b1),.wea(EM_WE),
-      .addra({gpmc_ptr[PTR_WIDTH-1:0], EM_A}),.dia(data_i),.doa(),
-      .clkb(~clk),.enb(1'b1),.web(1'b0),
+      .addra({gpmc_ptr[PTR_WIDTH-1:0], addr}),.dia(data_i),.doa(),
+      .clkb(clk),.enb(enable),.web(1'b0),
       .addrb({fifo_ptr[PTR_WIDTH-1:0], counter}),.dib(18'h3ffff),.dob(data_o));
 
 endmodule // gpmc_to_fifo
diff --git a/fpga/usrp2/gpmc/gpmc_wb.v b/fpga/usrp2/gpmc/gpmc_wb.v
deleted file mode 100644
index 4d368ca94..000000000
--- a/fpga/usrp2/gpmc/gpmc_wb.v
+++ /dev/null
@@ -1,79 +0,0 @@
-//
-// Copyright 2011 Ettus Research LLC
-//
-// This program is free software: you can redistribute it and/or modify
-// it under the terms of the GNU General Public License as published by
-// the Free Software Foundation, either version 3 of the License, or
-// (at your option) any later version.
-//
-// This program is distributed in the hope that it will be useful,
-// but WITHOUT ANY WARRANTY; without even the implied warranty of
-// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-// GNU General Public License for more details.
-//
-// You should have received a copy of the GNU General Public License
-// along with this program.  If not, see <http://www.gnu.org/licenses/>.
-//
-
-
-
-module gpmc_wb
-  (input EM_CLK, input [15:0] EM_D_in, output [15:0] EM_D_out, input [10:1] EM_A, input [1:0] EM_NBE,
-   input EM_WE, input EM_OE,
-
-   input wb_clk, input wb_rst,
-   output reg [10:0] wb_adr_o, output reg [15:0] wb_dat_mosi, input [15:0] wb_dat_miso,
-   output reg [1:0] wb_sel_o, output wb_cyc_o, output reg wb_stb_o, output reg wb_we_o, input wb_ack_i);
-   
-   // ////////////////////////////////////////////
-   // Control Path, Wishbone bus bridge (wb master)
-   reg [1:0] we_del, oe_del;
-
-   // Synchronize the async control signals
-   always @(posedge wb_clk)
-     if (wb_rst) begin
-        we_del <= 2'b0;
-        oe_del <= 2'b0;
-     end
-     else begin
-        we_del <= { we_del[0], EM_WE };
-        oe_del <= { oe_del[0], EM_OE };
-     end
-
-    wire writing = we_del == 2'b01;
-    wire reading = oe_del == 2'b01;
-
-   always @(posedge wb_clk)
-     if(writing || reading)
-       wb_adr_o <= { EM_A, 1'b0 };
-
-   always @(posedge wb_clk)
-     if(writing)
-       begin
-          wb_dat_mosi <= EM_D_in;
-          wb_sel_o <= ~EM_NBE;
-       end
-
-   reg [15:0] EM_D_hold;
-   
-   always @(posedge wb_clk)
-     if(wb_ack_i)
-       EM_D_hold <= wb_dat_miso;
-
-   assign EM_D_out = wb_ack_i ? wb_dat_miso : EM_D_hold;
-   
-   assign wb_cyc_o = wb_stb_o;
-
-   always @(posedge wb_clk)
-     if(writing)
-       wb_we_o <= 1;
-     else if(wb_ack_i)  // Turn off we when done.  Could also use we_del[0], others...
-       wb_we_o <= 0;
-
-   always @(posedge wb_clk)
-     if(writing || reading)
-       wb_stb_o <= 1;
-     else if(wb_ack_i)
-       wb_stb_o <= 0;
-   
-endmodule // gpmc_wb
diff --git a/fpga/usrp2/top/B100/B100.v b/fpga/usrp2/top/B100/B100.v
index dcda974b4..cb4efa4fa 100644
--- a/fpga/usrp2/top/B100/B100.v
+++ b/fpga/usrp2/top/B100/B100.v
@@ -1,5 +1,5 @@
 //
-// Copyright 2011 Ettus Research LLC
+// Copyright 2011-2012 Ettus Research LLC
 //
 // This program is free software: you can redistribute it and/or modify
 // it under the terms of the GNU General Public License as published by
@@ -50,6 +50,8 @@ module B100
    // /////////////////////////////////////////////////////////////////////////
    // Clocking
    wire  clk_fpga, clk_fpga_in, reset;
+   wire gpif_clk = IFCLK;
+   wire gpif_rst;
    
    IBUFGDS #(.IOSTANDARD("LVDS_33"), .DIFF_TERM("TRUE")) 
    clk_fpga_pin (.O(clk_fpga_in),.I(CLK_FPGA_P),.IB(CLK_FPGA_N));
@@ -57,6 +59,7 @@ module B100
    BUFG clk_fpga_BUFG (.I(clk_fpga_in), .O(clk_fpga));
    
    reset_sync reset_sync(.clk(clk_fpga), .reset_in((~reset_n) | (~ext_reset)), .reset_out(reset));
+   reset_sync reset_sync_gpif(.clk(gpif_clk), .reset_in((~reset_n) | (~ext_reset)), .reset_out(gpif_rst));
    
    // /////////////////////////////////////////////////////////////////////////
    // SPI
@@ -105,6 +108,7 @@ module B100
    // /////////////////////////////////////////////////////////////////////////
    // RX ADC -- handles deinterleaving
 
+   wire rxsync_0, rxsync_1;
    reg [11:0] rx_i, rx_q;
    wire [11:0] rx_a, rx_b;
    
@@ -151,24 +155,60 @@ module B100
 	  rx_i <= rx_a;
 	  rx_q <= rx_b;
        end
-   
+
    // /////////////////////////////////////////////////////////////////////////
-   // Main U1E Core
-   u1plus_core u1p_c(.clk_fpga(clk_fpga), .rst_fpga(reset),
-		     .debug_led(debug_led), .debug(debug), .debug_clk(debug_clk),
-		     .debug_txd(), .debug_rxd(1'b1),
-		     
-		     .gpif_d(GPIF_D), .gpif_ctl(GPIF_CTL), .gpif_pktend(GPIF_PKTEND),
-		     .gpif_sloe(GPIF_SLOE), .gpif_slwr(GPIF_SLWR), .gpif_slrd(GPIF_SLRD),
-		     .gpif_fifoadr(GPIF_ADR), .gpif_clk(IFCLK),
-
-		     .db_sda(SDA_FPGA), .db_scl(SCL_FPGA),
-		     .sclk(sclk), .sen({SEN_CODEC,SEN_TX_DB,SEN_RX_DB}), .mosi(mosi), .miso(miso),
-		     .cgen_st_status(cgen_st_status), .cgen_st_ld(cgen_st_ld),.cgen_st_refmon(cgen_st_refmon), 
-		     .cgen_sync_b(cgen_sync_b), .cgen_ref_sel(cgen_ref_sel),
-		     .io_tx(io_tx), .io_rx(io_rx),
-		     .tx_i(tx_i), .tx_q(tx_q), 
-		     .rx_i(rx_i), .rx_q(rx_q),
-		     .pps_in(PPS_IN) );
+   // Main Core
+   wire [35:0] rx_data, tx_data, ctrl_data, resp_data;
+   wire rx_src_rdy, rx_dst_rdy, tx_src_rdy, tx_dst_rdy, resp_src_rdy, resp_dst_rdy, ctrl_src_rdy, ctrl_dst_rdy;
+   wire dsp_rx_run, dsp_tx_run;
+   wire [7:0] sen8;
+   assign {SEN_CODEC,SEN_TX_DB,SEN_RX_DB} = sen8[2:0];
+    wire [31:0] core_debug;
+
+   assign debug_led = {dsp_tx_run, dsp_rx_run, cgen_st_ld};
+   wire cgen_sync;
+   assign { cgen_sync_b, cgen_ref_sel } = {~cgen_sync, 1'b1};
+
+   u1plus_core #(
+        .NUM_RX_DSPS(1),
+        .DSP_RX_XTRA_FIFOSIZE(11),
+        .DSP_TX_XTRA_FIFOSIZE(12),
+        .USE_PACKET_PADDER(1)
+    ) core(
+         .clk(clk_fpga), .reset(reset),
+         .debug(core_debug), .debug_clk(debug_clk),
+
+         .rx_data(rx_data), .rx_src_rdy(rx_src_rdy), .rx_dst_rdy(rx_dst_rdy),
+         .tx_data(tx_data), .tx_src_rdy(tx_src_rdy), .tx_dst_rdy(tx_dst_rdy),
+         .ctrl_data(ctrl_data), .ctrl_src_rdy(ctrl_src_rdy), .ctrl_dst_rdy(ctrl_dst_rdy),
+         .resp_data(resp_data), .resp_src_rdy(resp_src_rdy), .resp_dst_rdy(resp_dst_rdy),
+
+         .dsp_rx_run(dsp_rx_run), .dsp_tx_run(dsp_tx_run),
+         .clock_sync(cgen_sync),
+
+         .db_sda(SDA_FPGA), .db_scl(SCL_FPGA),
+         .sclk(sclk), .sen(sen8), .mosi(mosi), .miso(miso),
+         .io_tx(io_tx), .io_rx(io_rx),
+         .tx_i(tx_i), .tx_q(tx_q),
+         .rx_i(rx_i), .rx_q(rx_q),
+         .pps_in(PPS_IN) );
+
+    // /////////////////////////////////////////////////////////////////////////
+    // Interface from host to/from GPIF
+    wire [31:0] gpif_debug;
+    slave_fifo slave_fifo (.gpif_clk(gpif_clk), .gpif_rst(gpif_rst), .gpif_d(GPIF_D),
+         .gpif_ctl(GPIF_CTL), .sloe(GPIF_SLOE), .slwr(GPIF_SLWR), .slrd(GPIF_SLRD),
+         .pktend(GPIF_PKTEND), .fifoadr(GPIF_ADR),
+
+         .fifo_clk(clk_fpga), .fifo_rst(reset),
+         .rx_data(rx_data), .rx_src_rdy(rx_src_rdy), .rx_dst_rdy(rx_dst_rdy),
+         .tx_data(tx_data), .tx_src_rdy(tx_src_rdy), .tx_dst_rdy(tx_dst_rdy),
+         .ctrl_data(ctrl_data), .ctrl_src_rdy(ctrl_src_rdy), .ctrl_dst_rdy(ctrl_dst_rdy),
+         .resp_data(resp_data), .resp_src_rdy(resp_src_rdy), .resp_dst_rdy(resp_dst_rdy),
+
+         .debug(gpif_debug));
+
+    //assign debug = gpif_debug;
+    assign debug = core_debug;
 
 endmodule // B100
diff --git a/fpga/usrp2/top/B100/core_compile b/fpga/usrp2/top/B100/core_compile
index b62cbaee0..2192bfa94 100755
--- a/fpga/usrp2/top/B100/core_compile
+++ b/fpga/usrp2/top/B100/core_compile
@@ -1 +1 @@
-iverilog -Wall -y. -y ../../control_lib/ -y ../../custom/ -y ../../fifo/ -y ../../gpif/ -y ../../models/ -y ../../sdr_lib/ -y ../../coregen/ -y ../../vrt/ -y ../../opencores/i2c/rtl/verilog/ -y ../../opencores/spi/rtl/verilog/ -y ../../timing/ -y ../../opencores/8b10b/ -I ../../opencores/spi/rtl/verilog/ -I ../../opencores/i2c/rtl/verilog/ -y ../../simple_gemac u1plus_core.v  2>&1   | grep -v timescale | grep -v coregen | grep -v models
+iverilog -Wall -y. -y ../../control_lib/ -y ../../custom/ -y ../../fifo/ -y ../../gpif/ -y ../../models/ -y ../../sdr_lib/ -y ../../coregen/ -y ../../vrt/ -y ../../opencores/i2c/rtl/verilog/ -y ../../opencores/spi/rtl/verilog/ -y ../../timing/ -y ../../opencores/8b10b/ -I ../../opencores/spi/rtl/verilog/ -I ../../opencores/i2c/rtl/verilog/ -y ../../simple_gemac B100.v  2>&1   | grep -v timescale | grep -v coregen | grep -v models
diff --git a/fpga/usrp2/top/B100/timing.ucf b/fpga/usrp2/top/B100/timing.ucf
index 96c47cf2c..c4404e1d0 100644
--- a/fpga/usrp2/top/B100/timing.ucf
+++ b/fpga/usrp2/top/B100/timing.ucf
@@ -5,10 +5,15 @@ NET "IFCLK" TNM_NET = "IFCLK";
 TIMESPEC "TS_IFCLK" = PERIOD "IFCLK" 20833 ps HIGH 50 %;
 
 #constrain FX2 IO
-NET "GPIF_D<*>" MAXDELAY = 5.5 ns;
-NET "GPIF_CTL<*>" MAXDELAY = 5.5 ns;
-NET "GPIF_ADR<*>" MAXDELAY = 5.5ns;
-NET "GPIF_SLWR" MAXDELAY = 5.5 ns;
-NET "GPIF_SLRD" MAXDELAY = 5.5 ns;
-NET "GPIF_SLOE" MAXDELAY = 5.5 ns;
-NET "GPIF_PKTEND" MAXDELAY = 5.5 ns;
+INST "GPIF_D<*>" TNM = gpif_net_in;
+INST "GPIF_CTL<*>" TNM = gpif_net_in;
+
+INST "GPIF_D<*>" TNM = gpif_net_out;
+INST "GPIF_ADR<*>" TNM = gpif_net_out;
+INST "GPIF_SLWR" TNM = gpif_net_out;
+INST "GPIF_SLOE" TNM = gpif_net_out;
+INST "GPIF_SLRD" TNM = gpif_net_out;
+INST "GPIF_PKTEND" TNM = gpif_net_out;
+
+TIMEGRP "gpif_net_in" OFFSET = IN 7 ns VALID 14 ns BEFORE "IFCLK" RISING;
+TIMEGRP "gpif_net_out" OFFSET = OUT 7 ns AFTER "IFCLK" RISING;
diff --git a/fpga/usrp2/top/B100/u1plus_core.v b/fpga/usrp2/top/B100/u1plus_core.v
index e5af189cc..9ffbaa202 100644
--- a/fpga/usrp2/top/B100/u1plus_core.v
+++ b/fpga/usrp2/top/B100/u1plus_core.v
@@ -18,435 +18,339 @@
 
 
 module u1plus_core
-  (input clk_fpga, input rst_fpga,
-   output [2:0] debug_led, output [31:0] debug, output [1:0] debug_clk,
-   output debug_txd, input debug_rxd,
-   
-   // GPIF
-   inout [15:0] gpif_d, input [3:0] gpif_ctl, output gpif_sloe,
-   output gpif_slwr, output gpif_slrd, output gpif_pktend, output [1:0] gpif_fifoadr,
-   input gpif_clk,
-   
+#(
+    parameter NUM_RX_DSPS = 2,
+    parameter CTRL_ACK_SID = 20,      //needed for reply
+
+    parameter DSP_TX_FIFOSIZE = 10,     //4K MTU
+    parameter DSP_RX_FIFOSIZE = 10,     //4K MTU
+
+    parameter DSP_RX_XTRA_FIFOSIZE = 11,
+    parameter DSP_TX_XTRA_FIFOSIZE = 11,
+
+    parameter USE_PACKET_PADDER = 0
+)
+  (input clk, input reset,
+   output [31:0] debug, output [1:0] debug_clk,
+
+   // Host Interface
+   input [35:0] tx_data, input tx_src_rdy, output tx_dst_rdy,
+   output [35:0] rx_data, output rx_src_rdy, input rx_dst_rdy,
+   input [35:0] ctrl_data, input ctrl_src_rdy, output ctrl_dst_rdy,
+   output [35:0] resp_data, output resp_src_rdy, input resp_dst_rdy,
+
+   output dsp_rx_run, output dsp_tx_run, output clock_sync,
+
    inout db_sda, inout db_scl,
-   output sclk, output [15:0] sen, output mosi, input miso,
+   output sclk, output [7:0] sen, output mosi, input miso,
 
-   input cgen_st_status, input cgen_st_ld, input cgen_st_refmon, output cgen_sync_b, output cgen_ref_sel,   
-   inout [15:0] io_tx, inout [15:0] io_rx, 
-   output [13:0] tx_i, output [13:0] tx_q, 
-   input [11:0] rx_i, input [11:0] rx_q, 
+   inout [15:0] io_tx, inout [15:0] io_rx,
+   output [13:0] tx_i, output [13:0] tx_q,
+   input [11:0] rx_i, input [11:0] rx_q,
    input pps_in
    );
 
-   localparam TXFIFOSIZE = 11;
-   localparam RXFIFOSIZE = 12;
-
-   // 64 total regs in address space
-   localparam SR_RX_CTRL0 = 0;       // 9 regs (+0 to +8)
-   localparam SR_RX_DSP0 = 10;       // 4 regs (+0 to +3)
-   localparam SR_RX_CTRL1 = 16;      // 9 regs (+0 to +8)
-   localparam SR_RX_DSP1 = 26;       // 4 regs (+0 to +3)
-   localparam SR_TX_CTRL = 32;       // 4 regs (+0 to +3)
-   localparam SR_TX_DSP = 38;        // 3 regs (+0 to +2)
-
-   localparam SR_TIME64 = 42;        // 6 regs (+0 to +5)
-   localparam SR_RX_FRONT = 48;      // 5 regs (+0 to +4)
-   localparam SR_TX_FRONT = 54;      // 5 regs (+0 to +4)
-
-   localparam SR_REG_TEST32 = 60;    // 1 reg
-   localparam SR_CLEAR_FIFO = 61;    // 1 reg
-   localparam SR_GLOBAL_RESET = 63;  // 1 reg
-   localparam SR_USER_REGS = 64;     // 2 regs
-
-   localparam SR_GPIO = 128;         // 5 regs
-   
-   wire 	wb_clk = clk_fpga;
-   wire 	wb_rst, global_reset;
-
-   wire 	pps_int;
-   wire [63:0] 	vita_time, vita_time_pps;
-   reg [15:0] 	reg_cgen_ctrl, reg_test;
-
-   wire [7:0]  set_addr, set_addr_user;
-   wire [31:0] set_data, set_data_user;
-   wire        set_stb, set_stb_user;
-
-   wire [31:0]  debug0;
-   wire [31:0]  debug1;
-
-   wire [31:0] 	debug_vt;
-   wire 	gpif_rst;
-   
-   reg [7:0] 	frames_per_packet;
-   
-   wire 	rx_overrun_dsp0, rx_overrun_dsp1, rx_overrun_gpif, tx_underrun_dsp, tx_underrun_gpif;
-   wire 	rx_overrun = rx_overrun_gpif | rx_overrun_dsp0 | rx_overrun_dsp1;
-   wire 	tx_underrun = tx_underrun_gpif | tx_underrun_dsp;
-   
-   setting_reg #(.my_addr(SR_GLOBAL_RESET), .width(1)) sr_reset
-     (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr),
-      .in(set_data),.out(),.changed(global_reset));
-
-   reset_sync reset_sync_wb(.clk(wb_clk), .reset_in(rst_fpga | global_reset), .reset_out(wb_rst));
-   reset_sync reset_sync_gp(.clk(gpif_clk), .reset_in(rst_fpga | global_reset), .reset_out(gpif_rst));
-   
-   // /////////////////////////////////////////////////////////////////////////////////////
-   // GPIF Slave to Wishbone Master
-   localparam dw = 16;
-   localparam aw = 11;
-   localparam sw = 2;
-   
-   wire [dw-1:0] m0_dat_mosi, m0_dat_miso;
-   wire [aw-1:0] m0_adr;
-   wire [sw-1:0] m0_sel;
-   wire 	 m0_cyc, m0_stb, m0_we, m0_ack, m0_err, m0_rty;
-
-   wire [31:0] 	 debug_gpif;
-
-   wire [35:0] 	 tx_data, rx_data, tx_err_data;
-   wire 	 tx_src_rdy, tx_dst_rdy, rx_src_rdy, rx_dst_rdy, 
-		 tx_err_src_rdy, tx_err_dst_rdy;
-
-   wire 	 clear_fifo;
-
-   setting_reg #(.my_addr(SR_CLEAR_FIFO), .width(1)) sr_clear_fifo
-     (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr),
-      .in(set_data),.out(),.changed(clear_fifo));
-
-   wire 	 run_rx0, run_rx1;
-
-   slave_fifo #(.TXFIFOSIZE(TXFIFOSIZE), .RXFIFOSIZE(RXFIFOSIZE))
-   slave_fifo (.gpif_clk(gpif_clk), .gpif_rst(gpif_rst), .gpif_d(gpif_d),
-	 .gpif_ctl(gpif_ctl), .sloe(gpif_sloe), .slwr(gpif_slwr), .slrd(gpif_slrd),
-     .pktend(gpif_pktend), .fifoadr(gpif_fifoadr),
-	 
-	 .wb_clk(wb_clk), .wb_rst(wb_rst),
-	 .wb_adr_o(m0_adr), .wb_dat_mosi(m0_dat_mosi), .wb_dat_miso(m0_dat_miso),
-	 .wb_sel_o(m0_sel), .wb_cyc_o(m0_cyc), .wb_stb_o(m0_stb), .wb_we_o(m0_we),
-	 .wb_ack_i(m0_ack), .triggers(8'd0),
-	 
-	 .dsp_rx_run(run_rx0 | run_rx1),
-	 
-	 .fifo_clk(wb_clk), .fifo_rst(wb_rst), .clear_tx(clear_fifo), .clear_rx(clear_fifo),
-	 .tx_data_o(tx_data), .tx_src_rdy_o(tx_src_rdy), .tx_dst_rdy_i(tx_dst_rdy),
-	 .rx_data_i(rx_data), .rx_src_rdy_i(rx_src_rdy), .rx_dst_rdy_o(rx_dst_rdy),
-	 .tx_err_data_i(tx_err_data), .tx_err_src_rdy_i(tx_err_src_rdy), .tx_err_dst_rdy_o(tx_err_dst_rdy),
-	 
-	 .tx_underrun(tx_underrun_gpif), .rx_overrun(rx_overrun_gpif),
-
-	 .test_len(0), .test_rate(0), .test_ctrl(0),
-	 .debug0(debug0), .debug1(debug1));
+    localparam SR_MISC         = 0;      // 5
+    localparam SR_USER_REGS    = 5;      // 2
+    localparam SR_PADDER       = 10;     // 2
+
+    localparam SR_TX_CTRL      = 32;     // 6
+    localparam SR_TX_DSP       = 40;     // 5
+    localparam SR_TX_FE        = 48;     // 5
+
+    localparam SR_RX_CTRL0     = 96;      // 9
+    localparam SR_RX_DSP0      = 106;     // 7
+    localparam SR_RX_FE        = 114;     // 5
+
+    localparam SR_RX_CTRL1     = 128;     // 9
+    localparam SR_RX_DSP1      = 138;     // 7
+
+    localparam SR_TIME64       = 192;     // 6
+    localparam SR_SPI          = 208;     // 3
+    localparam SR_I2C          = 216;     // 1
+    localparam SR_GPIO         = 224;     // 5
+
+    //compatibility number -> increment when the fpga has been sufficiently altered
+    localparam compat_num = {16'd11, 16'd0}; //major, minor
+
+    //assign run signals used for ATR logic
+    wire [NUM_RX_DSPS-1:0] run_rx_n;
+    wire run_tx;
+    wire run_rx = |(run_rx_n);
+    assign dsp_rx_run = run_rx;
+    assign dsp_tx_run = run_tx;
+
+    //shared time core signals
+    wire [63:0] vita_time, vita_time_pps;
+
+    //shared settings bus signals
+    wire set_stb, set_stb_user;
+    wire [31:0] set_data, set_data_user;
+    wire [7:0] set_addr, set_addr_user;
+
+    //shared SPI core signals
+    wire [31:0] spi_readback;
+    wire spi_ready;
+
+    //shared I2C core signals
+    wire [31:0] i2c_readback;
+    wire i2c_ready;
+
+    //shared GPIO core signals
+    wire [31:0] gpio_readback;
+
+    ///////////////////////////////////////////////////////////////////////////
+    // Misc Registers - persistent across resets
+    ///////////////////////////////////////////////////////////////////////////
+    wire [31:0] config_word0;
+    setting_reg #(.my_addr(SR_MISC+0), .width(32)) sr_misc_config0
+     (.clk(clk), .rst(1'b0/*reset*/), .strobe(set_stb), .addr(set_addr), .in(set_data), .out(config_word0));
+
+    wire [31:0] config_word1;
+    setting_reg #(.my_addr(SR_MISC+1), .width(32)) sr_misc_config1
+     (.clk(clk), .rst(1'b0/*reset*/), .strobe(set_stb), .addr(set_addr), .in(set_data), .out(config_word1));
+
+    wire clock_sync_inv, clock_sync_enb;
+    setting_reg #(.my_addr(SR_MISC+2), .width(2)) sr_misc_clock_sync
+     (.clk(clk), .rst(reset), .strobe(set_stb), .addr(set_addr), .in(set_data),
+     .out({clock_sync_inv, clock_sync_enb}));
+
+    ///////////////////////////////////////////////////////////////////////////
+    // Settings Bus and Readback
+    ///////////////////////////////////////////////////////////////////////////
+    user_settings #(.BASE(SR_USER_REGS)) user_settings
+     (.clk(clk),.rst(reset),
+      .set_stb(set_stb), .set_addr(set_addr),.set_data(set_data),
+      .set_addr_user(set_addr_user),.set_data_user(set_data_user), .set_stb_user(set_stb_user) );
+
+    wire [35:0] ctrl_out_data, ctrl_int_data;
+    wire ctrl_out_src_rdy, ctrl_out_dst_rdy;
+    wire ctrl_int_src_rdy, ctrl_int_dst_rdy;
+
+    fifo_cascade #(.WIDTH(36), .SIZE(9)) ctrl_fifo
+     (.clk(clk), .reset(reset), .clear(1'b0),
+      .datain(ctrl_data), .src_rdy_i(ctrl_src_rdy), .dst_rdy_o(ctrl_dst_rdy), .space(),
+      .dataout(ctrl_int_data), .src_rdy_o(ctrl_int_src_rdy), .dst_rdy_i(ctrl_int_dst_rdy), .occupied());
+
+    wire [31:0] num_rx_dsps_rb = NUM_RX_DSPS;
+
+    wire [31:0] sfc_debug;
+    settings_fifo_ctrl #(.PROT_HDR(0), .ACK_SID(CTRL_ACK_SID), .XPORT_HDR(0)) sfc
+    (
+        .clock(clk), .reset(reset), .clear(1'b0),
+        .vita_time(vita_time), .perfs_ready(spi_ready & i2c_ready),
+        .in_data(ctrl_int_data), .in_valid(ctrl_int_src_rdy), .in_ready(ctrl_int_dst_rdy),
+        .out_data(ctrl_out_data), .out_valid(ctrl_out_src_rdy), .out_ready(ctrl_out_dst_rdy),
+        .strobe(set_stb), .addr(set_addr), .data(set_data),
+        .word00(spi_readback),.word01(compat_num),.word02(i2c_readback),.word03(gpio_readback),
+        .word04(config_word0),.word05(config_word1),.word06(num_rx_dsps_rb),.word07(32'hffff_ffff),
+        .word08(32'hffff_ffff),.word09(32'hffff_ffff),.word10(vita_time[63:32]),
+        .word11(vita_time[31:0]),.word12(32'hffff_ffff),.word13(32'hffff_ffff),
+        .word14(vita_time_pps[63:32]),.word15(vita_time_pps[31:0]),
+        .debug(sfc_debug)
+    );
+
+    ///////////////////////////////////////////////////////////////////////////
+    // Time Core
+    ///////////////////////////////////////////////////////////////////////////
+    time_64bit #(.BASE(SR_TIME64)) time_64bit
+     (.clk(clk), .rst(reset), .set_stb(set_stb), .set_addr(set_addr), .set_data(set_data),
+      .pps(pps_in), .vita_time(vita_time), .vita_time_pps(vita_time_pps),
+      .exp_time_in(0));
+
+    assign clock_sync = (clock_sync_enb)? (pps_in ^ clock_sync_inv) : 1'b0;
+
+    ///////////////////////////////////////////////////////////////////////////
+    // SPI Core
+    ///////////////////////////////////////////////////////////////////////////
+    simple_spi_core #(.BASE(SR_SPI), .WIDTH(8), .CLK_IDLE(0), .SEN_IDLE(8'hff))
+    simple_spi_core (.clock(clk), .reset(reset),
+        .set_stb(set_stb), .set_addr(set_addr), .set_data(set_data),
+        .readback(spi_readback), .ready(spi_ready),
+        .sen(sen), .sclk(sclk), .mosi(mosi), .miso(miso));
+
+    ///////////////////////////////////////////////////////////////////////////
+    // I2C Core
+    ///////////////////////////////////////////////////////////////////////////
+    wire scl_pad_i, scl_pad_o, scl_pad_oen_o, sda_pad_i, sda_pad_o, sda_pad_oen_o;
+    simple_i2c_core #(.BASE(SR_I2C)) i2c_core
+     (.clock(clk),.reset(reset),
+      .set_stb(set_stb), .set_addr(set_addr), .set_data(set_data),
+      .readback(i2c_readback), .ready(i2c_ready),
+      .scl_pad_i(scl_pad_i),.scl_pad_o(scl_pad_o),.scl_padoen_o(scl_pad_oen_o),
+      .sda_pad_i(sda_pad_i),.sda_pad_o(sda_pad_o),.sda_padoen_o(sda_pad_oen_o) );
+
+    // I2C -- Don't use external transistors for open drain, the FPGA implements this
+    IOBUF scl_pin(.O(scl_pad_i), .IO(db_scl), .I(scl_pad_o), .T(scl_pad_oen_o));
+    IOBUF sda_pin(.O(sda_pad_i), .IO(db_sda), .I(sda_pad_o), .T(sda_pad_oen_o));
+
+    ///////////////////////////////////////////////////////////////////////////
+    // GPIO Core
+    ///////////////////////////////////////////////////////////////////////////
+    gpio_atr #(.BASE(SR_GPIO), .WIDTH(32))
+    gpio_atr(.clk(clk),.reset(reset),
+        .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data),
+        .rx(run_rx), .tx(run_tx), .gpio({io_tx, io_rx}), .gpio_readback(gpio_readback) );
 
    // /////////////////////////////////////////////////////////////////////////
    // RX ADC Frontend, does IQ Balance, DC Offset, muxing
 
    wire [23:0] 	 rx_fe_i, rx_fe_q;  // 24 bits is total overkill here, but it matches u2/u2p
 
-   rx_frontend #(.BASE(SR_RX_FRONT)) rx_frontend
-     (.clk(wb_clk),.rst(wb_rst),
+   rx_frontend #(.BASE(SR_RX_FE)) rx_frontend
+     (.clk(clk),.rst(reset),
       .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data),
       .adc_a({rx_i,4'b00}),.adc_ovf_a(0),
       .adc_b({rx_q,4'b00}),.adc_ovf_b(0),
-      .i_out(rx_fe_i), .q_out(rx_fe_q), .run(run_rx0 | run_rx1), .debug());
-   
-   // /////////////////////////////////////////////////////////////////////////
-   // DSP RX 0
-
-   wire [31:0] 	 sample_rx0;
-   wire 	 strobe_rx0, clear_rx0;
-   wire [35:0] 	 vita_rx_data0;
-   wire 	 vita_rx_src_rdy0, vita_rx_dst_rdy0;
-   
-   ddc_chain #(.BASE(SR_RX_DSP0), .DSPNO(0)) ddc_chain0
-     (.clk(wb_clk), .rst(wb_rst), .clr(clear_rx0),
-      .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data),
-      .set_stb_user(set_stb_user), .set_addr_user(set_addr_user), .set_data_user(set_data_user),
-      .rx_fe_i(rx_fe_i),.rx_fe_q(rx_fe_q),
-      .sample(sample_rx0), .run(run_rx0), .strobe(strobe_rx0),
-      .debug() );
+      .i_out(rx_fe_i), .q_out(rx_fe_q), .run(run_rx), .debug());
 
-   vita_rx_chain #(.BASE(SR_RX_CTRL0), .UNIT(0), .FIFOSIZE(10), .PROT_ENG_FLAGS(0), .DSP_NUMBER(0)) vita_rx_chain0
-     (.clk(wb_clk),.reset(wb_rst),
-      .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data),
-      .set_stb_user(set_stb_user), .set_addr_user(set_addr_user), .set_data_user(set_data_user),
-      .vita_time(vita_time), .overrun(rx_overrun_dsp0),
-      .sample(sample_rx0), .run(run_rx0), .strobe(strobe_rx0), .clear_o(clear_rx0),
-      .rx_data_o(vita_rx_data0), .rx_dst_rdy_i(vita_rx_dst_rdy0), .rx_src_rdy_o(vita_rx_src_rdy0),
-      .debug() );
-   
    // /////////////////////////////////////////////////////////////////////////
-   // DSP RX 1
-
-   wire [31:0] 	 sample_rx1;
-   wire 	 strobe_rx1, clear_rx1;
-   wire [35:0] 	 vita_rx_data1;
-   wire 	 vita_rx_src_rdy1, vita_rx_dst_rdy1;
-   
-   ddc_chain #(.BASE(SR_RX_DSP1), .DSPNO(1)) ddc_chain1
-     (.clk(wb_clk),.rst(wb_rst), .clr(clear_rx1),
-      .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data),
-      .set_stb_user(set_stb_user), .set_addr_user(set_addr_user), .set_data_user(set_data_user),
-      .rx_fe_i(rx_fe_i),.rx_fe_q(rx_fe_q),
-      .sample(sample_rx1), .run(run_rx1), .strobe(strobe_rx1),
-      .debug() );
-
-   vita_rx_chain #(.BASE(SR_RX_CTRL1), .UNIT(1), .FIFOSIZE(10), .PROT_ENG_FLAGS(0), .DSP_NUMBER(1)) vita_rx_chain1
-     (.clk(wb_clk),.reset(wb_rst),
-      .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data),
-      .set_stb_user(set_stb_user), .set_addr_user(set_addr_user), .set_data_user(set_data_user),
-      .vita_time(vita_time), .overrun(rx_overrun_dsp1),
-      .sample(sample_rx1), .run(run_rx1), .strobe(strobe_rx1), .clear_o(clear_rx1),
-      .rx_data_o(vita_rx_data1), .rx_dst_rdy_i(vita_rx_dst_rdy1), .rx_src_rdy_o(vita_rx_src_rdy1),
-      .debug() );
+   // DSP RX *
+
+    wire [35:0] rx_int2_data [NUM_RX_DSPS-1:0];
+    wire rx_int2_src_rdy [NUM_RX_DSPS-1:0];
+    wire rx_int2_dst_rdy [NUM_RX_DSPS-1:0];
+
+    genvar dspno;
+    generate
+    for(dspno = 0; dspno < NUM_RX_DSPS; dspno = dspno + 1) begin:gen_rx_dsps
+
+        wire [31:0] sample_rx;
+        wire strobe_rx, clear_rx;
+        wire [35:0] vita_rx_data;
+        wire vita_rx_src_rdy, vita_rx_dst_rdy;
+        wire [35:0] int_rx_data;
+        wire int_rx_src_rdy, int_rx_dst_rdy;
+
+       ddc_chain #(.BASE(SR_RX_DSP0+dspno*32), .DSPNO(dspno)) ddc_chain
+         (.clk(clk), .rst(reset), .clr(clear_rx),
+          .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data),
+          .set_stb_user(set_stb_user), .set_addr_user(set_addr_user), .set_data_user(set_data_user),
+          .rx_fe_i(rx_fe_i),.rx_fe_q(rx_fe_q),
+          .sample(sample_rx), .run(run_rx_n[dspno]), .strobe(strobe_rx),
+          .debug() );
+
+        vita_rx_chain #(.BASE(SR_RX_CTRL0+dspno*32), .UNIT(dspno), .FIFOSIZE(DSP_RX_FIFOSIZE), .PROT_ENG_FLAGS(0), .DSP_NUMBER(dspno)) vita_rx_chain
+         (.clk(clk),.reset(reset),
+          .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data),
+          .set_stb_user(set_stb_user), .set_addr_user(set_addr_user), .set_data_user(set_data_user),
+          .vita_time(vita_time), .overrun(),
+          .sample(sample_rx), .run(run_rx_n[dspno]), .strobe(strobe_rx), .clear_o(clear_rx),
+          .rx_data_o(vita_rx_data), .rx_dst_rdy_i(vita_rx_dst_rdy), .rx_src_rdy_o(vita_rx_src_rdy),
+          .debug() );
+
+        fifo_cascade #(.WIDTH(36), .SIZE(DSP_RX_FIFOSIZE+1)) rx_data_fifo
+         (.clk(clk), .reset(reset), .clear(1'b0),
+          .datain(vita_rx_data), .src_rdy_i(vita_rx_src_rdy), .dst_rdy_o(vita_rx_dst_rdy), .space(),
+          .dataout(int_rx_data), .src_rdy_o(int_rx_src_rdy), .dst_rdy_i(int_rx_dst_rdy), .occupied());
+
+        if (dspno == 0) begin
+            assign rx_int2_data[dspno] = int_rx_data;
+            assign rx_int2_src_rdy[dspno] = int_rx_src_rdy;
+            assign int_rx_dst_rdy = rx_int2_dst_rdy[dspno];
+        end
+        else begin
+            fifo36_mux #(.prio(0)) // No priority, fair sharing
+            combine_rx_dsps (
+                .clk(clk), .reset(reset), .clear(1'b0/*noclear*/),
+                .data0_i(rx_int2_data[dspno-1]), .src0_rdy_i(rx_int2_src_rdy[dspno-1]), .dst0_rdy_o(rx_int2_dst_rdy[dspno-1]),
+                .data1_i(int_rx_data), .src1_rdy_i(int_rx_src_rdy), .dst1_rdy_o(int_rx_dst_rdy),
+                .data_o(rx_int2_data[dspno]), .src_rdy_o(rx_int2_src_rdy[dspno]), .dst_rdy_i(rx_int2_dst_rdy[dspno])
+            );
+        end
+
+    end
+    endgenerate
 
    // /////////////////////////////////////////////////////////////////////////
    // RX Stream muxing
 
-   fifo36_mux #(.prio(0)) mux_data_streams
-     (.clk(wb_clk), .reset(wb_rst), .clear(clear_fifo),
-      .data0_i(vita_rx_data0), .src0_rdy_i(vita_rx_src_rdy0), .dst0_rdy_o(vita_rx_dst_rdy0),
-      .data1_i(vita_rx_data1), .src1_rdy_i(vita_rx_src_rdy1), .dst1_rdy_o(vita_rx_dst_rdy1),
-      .data_o(rx_data), .src_rdy_o(rx_src_rdy), .dst_rdy_i(rx_dst_rdy));
+    wire [35:0] rx_int3_data;
+    wire rx_int3_src_rdy, rx_int3_dst_rdy;
+
+    fifo_cascade #(.WIDTH(36), .SIZE(DSP_RX_XTRA_FIFOSIZE)) rx_data_fifo_combined
+         (.clk(clk), .reset(reset), .clear(1'b0),
+          .datain(rx_int2_data[NUM_RX_DSPS-1]), .src_rdy_i(rx_int2_src_rdy[NUM_RX_DSPS-1]), .dst_rdy_o(rx_int2_dst_rdy[NUM_RX_DSPS-1]), .space(),
+          .dataout(rx_int3_data), .src_rdy_o(rx_int3_src_rdy), .dst_rdy_i(rx_int3_dst_rdy), .occupied());
+
+    generate
+    if (USE_PACKET_PADDER) begin
+    packet_padder36 #(.BASE(SR_PADDER)) packet_padder_rx_data36(
+        .clk(clk), .reset(reset),
+        .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data),
+        .data_i(rx_int3_data), .src_rdy_i(rx_int3_src_rdy), .dst_rdy_o(rx_int3_dst_rdy),
+        .data_o(rx_data), .src_rdy_o(rx_src_rdy), .dst_rdy_i(rx_dst_rdy),
+        .always_flush(~dsp_rx_run));
+    end
+    else begin
+        assign rx_data = rx_int3_data;
+        assign rx_src_rdy = rx_int3_src_rdy;
+        assign rx_int3_dst_rdy = rx_dst_rdy;
+    end
+    endgenerate
+
+    ///////////////////////////////////////////////////////////////////////////
+    // MUX for TX async and resp data
+    ///////////////////////////////////////////////////////////////////////////
+    wire [35:0] tx_err_data, resp_data_int;
+    wire tx_err_src_rdy, resp_src_rdy_int;
+    wire tx_err_dst_rdy, resp_dst_rdy_int;
+
+    fifo36_mux #(.prio(0)) // No priority, fair sharing
+    combine_async_and_resp (
+        .clk(clk), .reset(reset), .clear(1'b0/*noclear*/),
+        .data0_i(ctrl_out_data), .src0_rdy_i(ctrl_out_src_rdy), .dst0_rdy_o(ctrl_out_dst_rdy),
+        .data1_i(tx_err_data), .src1_rdy_i(tx_err_src_rdy), .dst1_rdy_o(tx_err_dst_rdy),
+        .data_o(resp_data_int), .src_rdy_o(resp_src_rdy_int), .dst_rdy_i(resp_dst_rdy_int)
+    );
+
+    fifo_cascade #(.WIDTH(36), .SIZE(9)) resp_fifo
+     (.clk(clk), .reset(reset), .clear(1'b0),
+      .datain(resp_data_int), .src_rdy_i(resp_src_rdy_int), .dst_rdy_o(resp_dst_rdy_int), .space(),
+      .dataout(resp_data), .src_rdy_o(resp_src_rdy), .dst_rdy_i(resp_dst_rdy), .occupied());
 
    // ///////////////////////////////////////////////////////////////////////////////////
    // DSP TX
 
-   wire 	 run_tx;
    wire [23:0] 	 tx_fe_i, tx_fe_q;
    wire [31:0]   sample_tx;
    wire strobe_tx, clear_tx;
 
-   vita_tx_chain #(.BASE(SR_TX_CTRL), .FIFOSIZE(10), .POST_ENGINE_FIFOSIZE(11),
+   vita_tx_chain #(.BASE(SR_TX_CTRL),
+		   .FIFOSIZE(DSP_TX_FIFOSIZE),
+		   .POST_ENGINE_FIFOSIZE(DSP_TX_XTRA_FIFOSIZE),
 		   .REPORT_ERROR(1), .DO_FLOW_CONTROL(0),
 		   .PROT_ENG_FLAGS(0), .USE_TRANS_HEADER(0),
-		   .DSP_NUMBER(0)) 
+		   .DSP_NUMBER(0))
    vita_tx_chain
-     (.clk(wb_clk), .reset(wb_rst),
+     (.clk(clk), .reset(reset),
       .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data),
       .set_stb_user(set_stb_user), .set_addr_user(set_addr_user), .set_data_user(set_data_user),
       .vita_time(vita_time),
       .tx_data_i(tx_data), .tx_src_rdy_i(tx_src_rdy), .tx_dst_rdy_o(tx_dst_rdy),
       .err_data_o(tx_err_data), .err_src_rdy_o(tx_err_src_rdy), .err_dst_rdy_i(tx_err_dst_rdy),
       .sample(sample_tx), .strobe(strobe_tx),
-      .underrun(tx_underrun_dsp), .run(run_tx), .clear_o(clear_tx),
-      .debug(debug_vt));
+      .underrun(), .run(run_tx), .clear_o(clear_tx),
+      .debug());
 
    duc_chain #(.BASE(SR_TX_DSP), .DSPNO(0)) duc_chain
-     (.clk(wb_clk), .rst(wb_rst), .clr(clear_tx),
+     (.clk(clk), .rst(reset), .clr(clear_tx),
       .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data),
       .set_stb_user(set_stb_user), .set_addr_user(set_addr_user), .set_data_user(set_data_user),
       .tx_fe_i(tx_fe_i),.tx_fe_q(tx_fe_q),
       .sample(sample_tx), .run(run_tx), .strobe(strobe_tx),
       .debug() );
 
-   tx_frontend #(.BASE(SR_TX_FRONT), .WIDTH_OUT(14)) tx_frontend
-     (.clk(wb_clk), .rst(wb_rst),
+   tx_frontend #(.BASE(SR_TX_FE), .WIDTH_OUT(14)) tx_frontend
+     (.clk(clk), .rst(reset),
       .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data),
       .tx_i(tx_fe_i), .tx_q(tx_fe_q), .run(1'b1),
       .dac_a(tx_i), .dac_b(tx_q));
 
    // /////////////////////////////////////////////////////////////////////////////////////
-   // Wishbone Intercon, single master
-   wire [dw-1:0] s0_dat_mosi, s1_dat_mosi, s0_dat_miso, s1_dat_miso, s2_dat_mosi, s3_dat_mosi, s2_dat_miso, s3_dat_miso,
-		 s4_dat_mosi, s5_dat_mosi, s4_dat_miso, s5_dat_miso, s6_dat_mosi, s7_dat_mosi, s6_dat_miso, s7_dat_miso,
-		 s8_dat_mosi, s9_dat_mosi, s8_dat_miso, s9_dat_miso, sa_dat_mosi, sb_dat_mosi, sa_dat_miso, sb_dat_miso,
-		 sc_dat_mosi, sd_dat_mosi, sc_dat_miso, sd_dat_miso, se_dat_mosi, sf_dat_mosi, se_dat_miso, sf_dat_miso;
-   wire [aw-1:0] s0_adr,s1_adr,s2_adr,s3_adr,s4_adr,s5_adr,s6_adr,s7_adr;
-   wire [aw-1:0] s8_adr,s9_adr,sa_adr,sb_adr,sc_adr, sd_adr, se_adr, sf_adr;
-   wire [sw-1:0] s0_sel,s1_sel,s2_sel,s3_sel,s4_sel,s5_sel,s6_sel,s7_sel;
-   wire [sw-1:0] s8_sel,s9_sel,sa_sel,sb_sel,sc_sel, sd_sel, se_sel, sf_sel;
-   wire 	 s0_ack,s1_ack,s2_ack,s3_ack,s4_ack,s5_ack,s6_ack,s7_ack;
-   wire 	 s8_ack,s9_ack,sa_ack,sb_ack,sc_ack, sd_ack, se_ack, sf_ack;
-   wire 	 s0_stb,s1_stb,s2_stb,s3_stb,s4_stb,s5_stb,s6_stb,s7_stb;
-   wire 	 s8_stb,s9_stb,sa_stb,sb_stb,sc_stb, sd_stb, se_stb, sf_stb;
-   wire 	 s0_cyc,s1_cyc,s2_cyc,s3_cyc,s4_cyc,s5_cyc,s6_cyc,s7_cyc;
-   wire 	 s8_cyc,s9_cyc,sa_cyc,sb_cyc,sc_cyc, sd_cyc, se_cyc, sf_cyc;
-   wire 	 s0_we,s1_we,s2_we,s3_we,s4_we,s5_we,s6_we,s7_we;
-   wire 	 s8_we,s9_we,sa_we,sb_we,sc_we,sd_we, se_we, sf_we;
-   
-   wb_1master #(.dw(dw), .aw(aw), .sw(sw), .decode_w(4),
-		.s0_addr(4'h0), .s0_mask(4'hF), // Misc Regs
-		.s1_addr(4'h1), .s1_mask(4'hF), // Unused
-		.s2_addr(4'h2), .s2_mask(4'hF),	// SPI
-		.s3_addr(4'h3), .s3_mask(4'hF), // I2C
-		.s4_addr(4'h4), .s4_mask(4'hF),	// Unused
-		.s5_addr(4'h5), .s5_mask(4'hF), // Unused on B1x0, Async Msg on E1x0
-		.s6_addr(4'h6), .s6_mask(4'hF),	// Unused
-		.s7_addr(4'h7), .s7_mask(4'hF), // Readback MUX
-		.s8_addr(4'h8), .s8_mask(4'h8), // Setting Regs -- slave 8 is 8 slaves wide
-		// slaves 9-f alias to slave 1, all are unused
-		.s9_addr(4'h1), .s9_mask(4'hF),
-		.sa_addr(4'h1), .sa_mask(4'hF),	.sb_addr(4'h1), .sb_mask(4'hF),
-		.sc_addr(4'h1), .sc_mask(4'hF),	.sd_addr(4'h1), .sd_mask(4'hF),
-		.se_addr(4'h1), .se_mask(4'hF),	.sf_addr(4'h1), .sf_mask(4'hF))
-   wb_1master
-     (.clk_i(wb_clk),.rst_i(wb_rst),       
-      .m0_dat_o(m0_dat_miso),.m0_ack_o(m0_ack),.m0_err_o(m0_err),.m0_rty_o(m0_rty),.m0_dat_i(m0_dat_mosi),
-      .m0_adr_i(m0_adr),.m0_sel_i(m0_sel),.m0_we_i(m0_we),.m0_cyc_i(m0_cyc),.m0_stb_i(m0_stb),
-      .s0_dat_o(s0_dat_mosi),.s0_adr_o(s0_adr),.s0_sel_o(s0_sel),.s0_we_o(s0_we),.s0_cyc_o(s0_cyc),.s0_stb_o(s0_stb),
-      .s0_dat_i(s0_dat_miso),.s0_ack_i(s0_ack),.s0_err_i(0),.s0_rty_i(0),
-      .s1_dat_o(s1_dat_mosi),.s1_adr_o(s1_adr),.s1_sel_o(s1_sel),.s1_we_o(s1_we),.s1_cyc_o(s1_cyc),.s1_stb_o(s1_stb),
-      .s1_dat_i(s1_dat_miso),.s1_ack_i(s1_ack),.s1_err_i(0),.s1_rty_i(0),
-      .s2_dat_o(s2_dat_mosi),.s2_adr_o(s2_adr),.s2_sel_o(s2_sel),.s2_we_o(s2_we),.s2_cyc_o(s2_cyc),.s2_stb_o(s2_stb),
-      .s2_dat_i(s2_dat_miso),.s2_ack_i(s2_ack),.s2_err_i(0),.s2_rty_i(0),
-      .s3_dat_o(s3_dat_mosi),.s3_adr_o(s3_adr),.s3_sel_o(s3_sel),.s3_we_o(s3_we),.s3_cyc_o(s3_cyc),.s3_stb_o(s3_stb),
-      .s3_dat_i(s3_dat_miso),.s3_ack_i(s3_ack),.s3_err_i(0),.s3_rty_i(0),
-      .s4_dat_o(s4_dat_mosi),.s4_adr_o(s4_adr),.s4_sel_o(s4_sel),.s4_we_o(s4_we),.s4_cyc_o(s4_cyc),.s4_stb_o(s4_stb),
-      .s4_dat_i(s4_dat_miso),.s4_ack_i(s4_ack),.s4_err_i(0),.s4_rty_i(0),
-      .s5_dat_o(s5_dat_mosi),.s5_adr_o(s5_adr),.s5_sel_o(s5_sel),.s5_we_o(s5_we),.s5_cyc_o(s5_cyc),.s5_stb_o(s5_stb),
-      .s5_dat_i(s5_dat_miso),.s5_ack_i(s5_ack),.s5_err_i(0),.s5_rty_i(0),
-      .s6_dat_o(s6_dat_mosi),.s6_adr_o(s6_adr),.s6_sel_o(s6_sel),.s6_we_o(s6_we),.s6_cyc_o(s6_cyc),.s6_stb_o(s6_stb),
-      .s6_dat_i(s6_dat_miso),.s6_ack_i(s6_ack),.s6_err_i(0),.s6_rty_i(0),
-      .s7_dat_o(s7_dat_mosi),.s7_adr_o(s7_adr),.s7_sel_o(s7_sel),.s7_we_o(s7_we),.s7_cyc_o(s7_cyc),.s7_stb_o(s7_stb),
-      .s7_dat_i(s7_dat_miso),.s7_ack_i(s7_ack),.s7_err_i(0),.s7_rty_i(0),
-      .s8_dat_o(s8_dat_mosi),.s8_adr_o(s8_adr),.s8_sel_o(s8_sel),.s8_we_o(s8_we),.s8_cyc_o(s8_cyc),.s8_stb_o(s8_stb),
-      .s8_dat_i(s8_dat_miso),.s8_ack_i(s8_ack),.s8_err_i(0),.s8_rty_i(0),
-      .s9_dat_o(s9_dat_mosi),.s9_adr_o(s9_adr),.s9_sel_o(s9_sel),.s9_we_o(s9_we),.s9_cyc_o(s9_cyc),.s9_stb_o(s9_stb),
-      .s9_dat_i(s9_dat_miso),.s9_ack_i(s9_ack),.s9_err_i(0),.s9_rty_i(0),
-      .sa_dat_o(sa_dat_mosi),.sa_adr_o(sa_adr),.sa_sel_o(sa_sel),.sa_we_o(sa_we),.sa_cyc_o(sa_cyc),.sa_stb_o(sa_stb),
-      .sa_dat_i(sa_dat_miso),.sa_ack_i(sa_ack),.sa_err_i(0),.sa_rty_i(0),
-      .sb_dat_o(sb_dat_mosi),.sb_adr_o(sb_adr),.sb_sel_o(sb_sel),.sb_we_o(sb_we),.sb_cyc_o(sb_cyc),.sb_stb_o(sb_stb),
-      .sb_dat_i(sb_dat_miso),.sb_ack_i(sb_ack),.sb_err_i(0),.sb_rty_i(0),
-      .sc_dat_o(sc_dat_mosi),.sc_adr_o(sc_adr),.sc_sel_o(sc_sel),.sc_we_o(sc_we),.sc_cyc_o(sc_cyc),.sc_stb_o(sc_stb),
-      .sc_dat_i(sc_dat_miso),.sc_ack_i(sc_ack),.sc_err_i(0),.sc_rty_i(0),
-      .sd_dat_o(sd_dat_mosi),.sd_adr_o(sd_adr),.sd_sel_o(sd_sel),.sd_we_o(sd_we),.sd_cyc_o(sd_cyc),.sd_stb_o(sd_stb),
-      .sd_dat_i(sd_dat_miso),.sd_ack_i(sd_ack),.sd_err_i(0),.sd_rty_i(0),
-      .se_dat_o(se_dat_mosi),.se_adr_o(se_adr),.se_sel_o(se_sel),.se_we_o(se_we),.se_cyc_o(se_cyc),.se_stb_o(se_stb),
-      .se_dat_i(se_dat_miso),.se_ack_i(se_ack),.se_err_i(0),.se_rty_i(0),
-      .sf_dat_o(sf_dat_mosi),.sf_adr_o(sf_adr),.sf_sel_o(sf_sel),.sf_we_o(sf_we),.sf_cyc_o(sf_cyc),.sf_stb_o(sf_stb),
-      .sf_dat_i(sf_dat_miso),.sf_ack_i(sf_ack),.sf_err_i(0),.sf_rty_i(0) );
-
-   assign s1_ack = 0;   assign s4_ack = 0;   assign s5_ack = 0;   assign s6_ack = 0;
-   assign s9_ack = 0;   assign sa_ack = 0;   assign sb_ack = 0;
-   assign sc_ack = 0;   assign sd_ack = 0;   assign se_ack = 0;   assign sf_ack = 0;
-
-   // /////////////////////////////////////////////////////////////////////////////////////
-   // Slave 0, Misc LEDs, Switches, controls
-   
-   localparam REG_CGEN_CTRL = 7'd4;    // out
-   localparam REG_CGEN_ST = 7'd6;      // in
-   localparam REG_TEST = 7'd8;         // out
-   localparam REG_RX_FRAMELEN = 7'd10; // in
-   localparam REG_TX_FRAMELEN = 7'd12; // out
-   
-   always @(posedge wb_clk)
-     if(wb_rst)
-       begin
-	  reg_cgen_ctrl <= 2'b11;
-	  reg_test <= 0;
-	  frames_per_packet <= 0;
-       end
-     else
-       if(s0_cyc & s0_stb & s0_we) 
-	 case(s0_adr[6:0])
-	   REG_CGEN_CTRL :
-	     reg_cgen_ctrl <= s0_dat_mosi;
-	   REG_TEST :
-	     reg_test <= s0_dat_mosi;
-	   REG_RX_FRAMELEN :
-	     frames_per_packet <= s0_dat_mosi[7:0];
-	 endcase // case (s0_adr[6:0])
-
-   assign debug_led = {run_tx, (run_rx0 | run_rx1), cgen_st_ld};
-   assign { cgen_sync_b, cgen_ref_sel } = reg_cgen_ctrl;
-   
-   assign s0_dat_miso = (s0_adr[6:0] == REG_CGEN_CTRL) ? reg_cgen_ctrl :
-			(s0_adr[6:0] == REG_CGEN_ST) ? {13'b0,cgen_st_status,cgen_st_ld,cgen_st_refmon} :
-			(s0_adr[6:0] == REG_TEST) ? reg_test :
-			16'hBEEF;
-   
-   assign s0_ack = s0_stb & s0_cyc;
-
-   // /////////////////////////////////////////////////////////////////////////////////////
-   // Slave 2, SPI
-
-   spi_top16 shared_spi
-     (.wb_clk_i(wb_clk),.wb_rst_i(wb_rst),.wb_adr_i(s2_adr[4:0]),.wb_dat_i(s2_dat_mosi),
-      .wb_dat_o(s2_dat_miso),.wb_sel_i(s2_sel),.wb_we_i(s2_we),.wb_stb_i(s2_stb),
-      .wb_cyc_i(s2_cyc),.wb_ack_o(s2_ack),.wb_err_o(),.wb_int_o(),
-      .ss_pad_o(sen), .sclk_pad_o(sclk), .mosi_pad_o(mosi), .miso_pad_i(miso) );
-   
-   // /////////////////////////////////////////////////////////////////////////
-   // Slave 3, I2C
-
-   wire 	scl_pad_i, scl_pad_o, scl_pad_oen_o, sda_pad_i, sda_pad_o, sda_pad_oen_o;
-   i2c_master_top #(.ARST_LVL(1)) i2c 
-     (.wb_clk_i(wb_clk),.wb_rst_i(wb_rst),.arst_i(1'b0), 
-      .wb_adr_i(s3_adr[3:1]),.wb_dat_i(s3_dat_mosi[7:0]),.wb_dat_o(s3_dat_miso[7:0]),
-      .wb_we_i(s3_we),.wb_stb_i(s3_stb),.wb_cyc_i(s3_cyc),
-      .wb_ack_o(s3_ack),.wb_inta_o(),
-      .scl_pad_i(scl_pad_i),.scl_pad_o(scl_pad_o),.scl_padoen_o(scl_pad_oen_o),
-      .sda_pad_i(sda_pad_i),.sda_pad_o(sda_pad_o),.sda_padoen_o(sda_pad_oen_o) );
-
-   assign 	 s3_dat_miso[15:8] = 8'd0;
-
-   // I2C -- Don't use external transistors for open drain, the FPGA implements this
-   IOBUF scl_pin(.O(scl_pad_i), .IO(db_scl), .I(scl_pad_o), .T(scl_pad_oen_o));
-   IOBUF sda_pin(.O(sda_pad_i), .IO(db_sda), .I(sda_pad_o), .T(sda_pad_oen_o));
-
-   // /////////////////////////////////////////////////////////////////////////
-   // GPIOs
-
-   wire [31:0] gpio_readback;
-   
-   gpio_atr #(.BASE(SR_GPIO), .WIDTH(32)) 
-   gpio_atr(.clk(wb_clk),.reset(wb_rst),
-	    .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data),
-	    .rx(run_rx0 | run_rx1), .tx(run_tx),
-	    .gpio({io_tx,io_rx}), .gpio_readback(gpio_readback) );
-
-   // /////////////////////////////////////////////////////////////////////////
-   // Settings Bus -- Slave #8 + 9
-
-   // only have 64 regs, 32 bits each with current setup...
-   settings_bus_16LE #(.AWIDTH(11),.RWIDTH(8)) settings_bus_16LE
-     (.wb_clk(wb_clk),.wb_rst(wb_rst),.wb_adr_i(s8_adr),.wb_dat_i(s8_dat_mosi),
-      .wb_stb_i(s8_stb),.wb_we_i(s8_we),.wb_ack_o(s8_ack),
-      .strobe(set_stb),.addr(set_addr),.data(set_data) );
-
-   user_settings #(.BASE(SR_USER_REGS)) user_settings
-     (.clk(wb_clk),.rst(wb_rst),.set_stb(set_stb),
-      .set_addr(set_addr),.set_data(set_data),
-      .set_addr_user(set_addr_user),.set_data_user(set_data_user),
-      .set_stb_user(set_stb_user) );
-
-   // /////////////////////////////////////////////////////////////////////////
-   // Readback mux 32 -- Slave #7
-
-   //compatibility number -> increment when the fpga has been sufficiently altered
-   localparam compat_num = {16'd10, 16'd0}; //major, minor
-
-   wire [31:0] reg_test32;
-
-   setting_reg #(.my_addr(SR_REG_TEST32)) sr_reg_test32
-     (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr),
-      .in(set_data),.out(reg_test32),.changed());
-
-   wb_readback_mux_16LE readback_mux_32
-     (.wb_clk_i(wb_clk), .wb_rst_i(wb_rst), .wb_stb_i(s7_stb),
-      .wb_adr_i({5'b0,s7_adr}), .wb_dat_o(s7_dat_miso), .wb_ack_o(s7_ack),
-
-      .word00(vita_time[63:32]),        .word01(vita_time[31:0]),
-      .word02(vita_time_pps[63:32]),    .word03(vita_time_pps[31:0]),
-      .word04(reg_test32),              .word05(32'b0),
-      .word06(compat_num),              .word07(gpio_readback),
-      .word08(32'b0),                   .word09(32'b0),
-      .word10(32'b0),                   .word11(32'b0),
-      .word12(32'b0),                   .word13(32'b0),
-      .word14(32'b0),                   .word15(32'b0)
-      );
-
-   // /////////////////////////////////////////////////////////////////////////
-   // VITA Timing
-
-   time_64bit #(.BASE(SR_TIME64)) time_64bit
-     (.clk(wb_clk), .rst(wb_rst), .set_stb(set_stb), .set_addr(set_addr), .set_data(set_data),
-      .pps(pps_in), .vita_time(vita_time), .vita_time_pps(vita_time_pps), .pps_int(pps_int),
-      .exp_time_in(0));
-   
-   // /////////////////////////////////////////////////////////////////////////////////////
    // Debug circuitry
 
-   assign debug_clk = 2'b00; // { gpif_clk, clk_fpga };
-   assign debug = 0;
-   
+   assign debug_clk = 2'b11;
+   assign debug = 32'hffffffff;
+
 endmodule // u1plus_core
diff --git a/fpga/usrp2/top/E1x0/u1e.ucf b/fpga/usrp2/top/E1x0/E1x0.ucf
index 278fc289a..278fc289a 100644
--- a/fpga/usrp2/top/E1x0/u1e.ucf
+++ b/fpga/usrp2/top/E1x0/E1x0.ucf
diff --git a/fpga/usrp2/top/E1x0/u1e.v b/fpga/usrp2/top/E1x0/E1x0.v
index 903ef7a6f..e7b0a4e00 100644
--- a/fpga/usrp2/top/E1x0/u1e.v
+++ b/fpga/usrp2/top/E1x0/E1x0.v
@@ -1,5 +1,5 @@
 //
-// Copyright 2011 Ettus Research LLC
+// Copyright 2011-2012 Ettus Research LLC
 //
 // This program is free software: you can redistribute it and/or modify
 // it under the terms of the GNU General Public License as published by
@@ -18,7 +18,7 @@
 `timescale 1ns / 1ps
 //////////////////////////////////////////////////////////////////////////////////
 
-module u1e
+module E1x0
   (input CLK_FPGA_P, input CLK_FPGA_N,  // Diff
    output [3:0] debug_led, output [31:0] debug, output [1:0] debug_clk,
    input debug_pb, output FPGA_TXD, input FPGA_RXD,
@@ -52,13 +52,23 @@ module u1e
    input PPS_IN
    );
 
+    assign FPGA_TXD = 0; //dont care
+
    // /////////////////////////////////////////////////////////////////////////
    // Clocking
-   wire  clk_fpga;
+   wire clk_fpga;
+   wire reset;
+
+   reg async_reset;
+   always @(negedge EM_CLK) begin
+        async_reset <= ~EM_NCS6 && ~EM_NWE && (EM_A[9:2] == 8'hff) && EM_D[0];
+   end
 
    IBUFGDS #(.IOSTANDARD("LVDS_33"), .DIFF_TERM("TRUE")) 
    clk_fpga_pin (.O(clk_fpga),.I(CLK_FPGA_P),.IB(CLK_FPGA_N));
 
+   reset_sync reset_sync(.clk(clk_fpga), .reset_in(async_reset), .reset_out(reset));
+
    // /////////////////////////////////////////////////////////////////////////
    // UART level conversion
    assign fpga_txd1 = overo_txd1;
@@ -73,12 +83,12 @@ module u1e
    assign miso = (~db_sen_tx & db_miso_tx) | (~db_sen_rx & db_miso_rx) |
                  (~sen_codec & miso_codec) | (~cgen_sen_b & cgen_miso);
 
-   //assign the aux spi to the cgen (bypasses wishbone)
+   //assign the aux spi to the cgen (bypasses control fifo)
    assign cgen_sclk = overo_gpio65;
    assign cgen_sen_b = overo_gpio128;
    assign cgen_mosi = overo_gpio145;
-   wire proc_int; //re-purpose gpio for interrupt when we are not using aux spi
-   assign overo_gpio147 = (cgen_sen_b == 1'b0)? cgen_miso : proc_int;
+   wire has_resp; //re-purpose gpio for interrupt when we are not using aux spi
+   assign overo_gpio147 = (cgen_sen_b == 1'b0)? cgen_miso : has_resp;
 
    wire _cgen_sen_b;
    //assign cgen_sen_b = _cgen_sen_b; //replaced by aux spi
@@ -121,29 +131,66 @@ module u1e
 		.D1(1'b1),   // 1-bit data input (associated with C1)
 		.R(1'b0),       // 1-bit reset input
 		.S(1'b0));      // 1-bit set input
-   
+
    // /////////////////////////////////////////////////////////////////////////
-   // Main U1E Core
-   u1e_core u1e_core(.clk_fpga(clk_fpga), .rst_fpga(~debug_pb),
-		     .debug_led(debug_led), .debug(debug), .debug_clk(debug_clk),
-		     .debug_txd(FPGA_TXD), .debug_rxd(FPGA_RXD),
-		     .EM_CLK(EM_CLK), .EM_D(EM_D), .EM_A(EM_A), .EM_NBE(EM_NBE),
-		     .EM_WAIT0(EM_WAIT0), .EM_NCS4(EM_NCS4), .EM_NCS5(EM_NCS5), 
-		     .EM_NCS6(EM_NCS6), .EM_NWE(EM_NWE), .EM_NOE(EM_NOE),
-		     .db_sda(db_sda), .db_scl(db_scl),
-		     .sclk(sclk), .sen({_cgen_sen_b,sen_codec,db_sen_tx,db_sen_rx}), .mosi(mosi), .miso(miso),
-		     .cgen_st_status(cgen_st_status), .cgen_st_ld(cgen_st_ld),.cgen_st_refmon(cgen_st_refmon), 
-		     .cgen_sync_b(cgen_sync_b), .cgen_ref_sel(cgen_ref_sel),
-		     .tx_have_space(overo_gpio144),
-		     .rx_have_data(overo_gpio146),
-		     .io_tx(io_tx), .io_rx(io_rx),
-		     .tx_i(tx_i), .tx_q(tx_q), 
-		     .rx_i(DA), .rx_q(DB),
-		     .pps_in(PPS_IN), .proc_int(proc_int) );
+   // Main Core
+   wire [35:0] rx_data, tx_data, ctrl_data, resp_data;
+   wire rx_src_rdy, rx_dst_rdy, tx_src_rdy, tx_dst_rdy, resp_src_rdy, resp_dst_rdy, ctrl_src_rdy, ctrl_dst_rdy;
+   wire dsp_rx_run, dsp_tx_run;
+   wire [7:0] sen8;
+   assign {_cgen_sen_b,sen_codec,db_sen_tx,db_sen_rx} = sen8[3:0];
+   wire [31:0] core_debug;
+
+   assign debug_led = ~{PPS_IN, dsp_tx_run, dsp_rx_run, cgen_st_ld};
+   wire cgen_sync;
+   assign { cgen_sync_b, cgen_ref_sel } = {~cgen_sync, 1'b1};
+
+   u1plus_core #(
+        .NUM_RX_DSPS(2),
+        .DSP_RX_XTRA_FIFOSIZE(10),
+        .DSP_TX_XTRA_FIFOSIZE(10),
+        .USE_PACKET_PADDER(0)
+    ) core(
+         .clk(clk_fpga), .reset(reset),
+         .debug(core_debug), .debug_clk(debug_clk),
+
+         .rx_data(rx_data), .rx_src_rdy(rx_src_rdy), .rx_dst_rdy(rx_dst_rdy),
+         .tx_data(tx_data), .tx_src_rdy(tx_src_rdy), .tx_dst_rdy(tx_dst_rdy),
+         .ctrl_data(ctrl_data), .ctrl_src_rdy(ctrl_src_rdy), .ctrl_dst_rdy(ctrl_dst_rdy),
+         .resp_data(resp_data), .resp_src_rdy(resp_src_rdy), .resp_dst_rdy(resp_dst_rdy),
+
+         .dsp_rx_run(dsp_rx_run), .dsp_tx_run(dsp_tx_run),
+         .clock_sync(cgen_sync),
+
+         .db_sda(db_sda), .db_scl(db_scl),
+         .sclk(sclk), .sen(sen8), .mosi(mosi), .miso(miso),
+         .io_tx(io_tx), .io_rx(io_rx),
+         .tx_i(tx_i), .tx_q(tx_q),
+         .rx_i(DA), .rx_q(DB),
+         .pps_in(PPS_IN) );
 
    // /////////////////////////////////////////////////////////////////////////
-   // Local Debug
-   // assign debug_clk = {clk_fpga, clk_2x };
-   // assign debug = { TXSYNC, TXBLANK, TX };
-   
-endmodule // u1e
+   // Interface between GPMC/host
+    wire [31:0] gpmc_debug;
+
+   gpmc #(.TXFIFOSIZE(13), .RXFIFOSIZE(13))
+   gpmc (.arst(async_reset),
+         .EM_CLK(EM_CLK), .EM_D(EM_D), .EM_A(EM_A), .EM_NBE(EM_NBE),
+         .EM_WAIT0(EM_WAIT0), .EM_NCS4(EM_NCS4), .EM_NCS6(EM_NCS6), .EM_NWE(EM_NWE),
+         .EM_NOE(EM_NOE),
+
+         .rx_have_data(overo_gpio146), .tx_have_space(overo_gpio144),
+         .resp_have_data(has_resp),
+
+         .fifo_clk(clk_fpga), .fifo_rst(reset),
+         .rx_data(rx_data), .rx_src_rdy(rx_src_rdy), .rx_dst_rdy(rx_dst_rdy),
+         .tx_data(tx_data), .tx_src_rdy(tx_src_rdy), .tx_dst_rdy(tx_dst_rdy),
+         .ctrl_data(ctrl_data), .ctrl_src_rdy(ctrl_src_rdy), .ctrl_dst_rdy(ctrl_dst_rdy),
+         .resp_data(resp_data), .resp_src_rdy(resp_src_rdy), .resp_dst_rdy(resp_dst_rdy),
+
+         .debug(gpmc_debug));
+
+    //assign debug = gpmc_debug;
+    assign debug = core_debug;
+
+endmodule // E1x0
diff --git a/fpga/usrp2/top/E1x0/Makefile.E100 b/fpga/usrp2/top/E1x0/Makefile.E100
index 3ba7e1031..92334d987 100644
--- a/fpga/usrp2/top/E1x0/Makefile.E100
+++ b/fpga/usrp2/top/E1x0/Makefile.E100
@@ -5,7 +5,7 @@
 ##################################################
 # Project Setup
 ##################################################
-TOP_MODULE = u1e
+TOP_MODULE = E1x0
 BUILD_DIR = $(abspath build$(ISE)-E100)
 
 # set me in a custom makefile
@@ -48,9 +48,9 @@ simulator "ISE Simulator (VHDL/Verilog)" \
 # Sources
 ##################################################
 TOP_SRCS = \
-u1e_core.v \
-u1e.v \
-u1e.ucf \
+../B100/u1plus_core.v \
+E1x0.v \
+E1x0.ucf \
 timing.ucf
 
 SOURCES = $(abspath $(TOP_SRCS)) $(FIFO_SRCS) \
diff --git a/fpga/usrp2/top/E1x0/Makefile.E110 b/fpga/usrp2/top/E1x0/Makefile.E110
index 89e51b523..e5be8d2fa 100644
--- a/fpga/usrp2/top/E1x0/Makefile.E110
+++ b/fpga/usrp2/top/E1x0/Makefile.E110
@@ -5,7 +5,7 @@
 ##################################################
 # Project Setup
 ##################################################
-TOP_MODULE = u1e
+TOP_MODULE = E1x0
 BUILD_DIR = $(abspath build$(ISE)-E110)
 
 # set me in a custom makefile
@@ -48,9 +48,9 @@ simulator "ISE Simulator (VHDL/Verilog)" \
 # Sources
 ##################################################
 TOP_SRCS = \
-u1e_core.v \
-u1e.v \
-u1e.ucf \
+../B100/u1plus_core.v \
+E1x0.v \
+E1x0.ucf \
 timing.ucf
 
 SOURCES = $(abspath $(TOP_SRCS)) $(FIFO_SRCS) \
diff --git a/fpga/usrp2/top/E1x0/core_compile b/fpga/usrp2/top/E1x0/core_compile
index 14e138fa3..ab992f29d 100755
--- a/fpga/usrp2/top/E1x0/core_compile
+++ b/fpga/usrp2/top/E1x0/core_compile
@@ -1,3 +1,3 @@
-iverilog -Wall -y. -y ../../control_lib/ -y ../../custom/ -y ../../fifo/ -y ../../gpmc/ -y ../../models/ -y ../../sdr_lib/ -y ../../coregen/ -y ../../vrt/ -y ../../opencores/i2c/rtl/verilog/ -y ../../opencores/spi/rtl/verilog/ -y ../../timing/ -y ../../opencores/8b10b/ -I ../../opencores/spi/rtl/verilog/ -I ../../opencores/i2c/rtl/verilog/ -y ../../simple_gemac -y $XILINX/verilog/src/unisims u1e_core.v  2>&1  | grep -v timescale | grep -v coregen | grep -v models
+iverilog -Wall -y. -y ../../control_lib/ -y ../../custom/ -y ../../fifo/ -y ../../gpmc/ -y ../../models/ -y ../../sdr_lib/ -y ../../coregen/ -y ../../vrt/ -y ../../opencores/i2c/rtl/verilog/ -y ../../opencores/spi/rtl/verilog/ -y ../../timing/ -y ../../opencores/8b10b/ -I ../../opencores/spi/rtl/verilog/ -I ../../opencores/i2c/rtl/verilog/ -y ../B100 -y $XILINX/verilog/src/unisims E1x0.v  2>&1  | grep -v timescale | grep -v coregen | grep -v models
 
 
diff --git a/fpga/usrp2/top/E1x0/timing.ucf b/fpga/usrp2/top/E1x0/timing.ucf
index 47c250c2f..7d3d9e090 100644
--- a/fpga/usrp2/top/E1x0/timing.ucf
+++ b/fpga/usrp2/top/E1x0/timing.ucf
@@ -3,25 +3,21 @@ NET "CLK_FPGA_P" TNM_NET = "CLK_FPGA_P";
 TIMESPEC "TS_clk_fpga_p" = PERIOD "CLK_FPGA_P" 15625 ps HIGH 50 %;
 
 NET "EM_CLK" TNM_NET = "EM_CLK";
-TIMESPEC "TS_em_clk" = PERIOD "EM_CLK" 12048 ps HIGH 50 %;
+TIMESPEC "TS_em_clk" = PERIOD "EM_CLK" 18867 ps HIGH 50 %;
 
 #constrain GPMC IO
-NET "EM_D<*>" MAXDELAY = 5.5 ns;
-NET "EM_A<*>" MAXDELAY = 5.5 ns;
-NET "EM_NBE<*>" MAXDELAY = 5.5 ns;
-NET "EM_NCS4" MAXDELAY = 5.5 ns;
-NET "EM_NCS6" MAXDELAY = 5.5 ns;
-NET "EM_NWE" MAXDELAY = 5.5 ns;
-NET "EM_NOE" MAXDELAY = 5.5 ns;
+INST "EM_D<*>" TNM = gpmc_net_out;
+INST "EM_D<*>" TNM = gpmc_net;
+INST "EM_A<*>" TNM = gpmc_net;
+INST "EM_NCS4" TNM = gpmc_net;
+INST "EM_NCS6" TNM = gpmc_net;
+INST "EM_NWE" TNM = gpmc_net;
+INST "EM_NOE" TNM = gpmc_net;
+
+TIMEGRP "gpmc_net" OFFSET = IN 6 ns VALID 12 ns BEFORE "EM_CLK" FALLING;
+TIMEGRP "gpmc_net_out" OFFSET = OUT 14 ns AFTER "EM_CLK" RISING; //2 clock cyc per read
 
 #constrain interrupt lines
 NET "overo_gpio144" MAXDELAY = 5.5 ns; #have space
 NET "overo_gpio146" MAXDELAY = 5.5 ns; #have data
 NET "overo_gpio147" MAXDELAY = 5.5 ns; #have msg/aux spi miso
-
-#NET "adc_a<*>" TNM_NET = ADC_DATA_GRP;
-#NET "adc_b<*>" TNM_NET = ADC_DATA_GRP;
-#TIMEGRP "ADC_DATA_GRP" OFFSET = IN 1 ns VALID 5 ns BEFORE "clk_fpga_p" RISING;
-
-#NET "adc_a<*>" OFFSET = IN 1 ns VALID 5 ns BEFORE "clk_fpga_p" RISING;
-#NET "adc_b<*>" OFFSET = IN 1 ns VALID 5 ns BEFORE "clk_fpga_p" RISING;
diff --git a/fpga/usrp2/top/E1x0/u1e_core.v b/fpga/usrp2/top/E1x0/u1e_core.v
deleted file mode 100644
index fef988e62..000000000
--- a/fpga/usrp2/top/E1x0/u1e_core.v
+++ /dev/null
@@ -1,494 +0,0 @@
-//
-// Copyright 2011-2012 Ettus Research LLC
-//
-// This program is free software: you can redistribute it and/or modify
-// it under the terms of the GNU General Public License as published by
-// the Free Software Foundation, either version 3 of the License, or
-// (at your option) any later version.
-//
-// This program is distributed in the hope that it will be useful,
-// but WITHOUT ANY WARRANTY; without even the implied warranty of
-// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-// GNU General Public License for more details.
-//
-// You should have received a copy of the GNU General Public License
-// along with this program.  If not, see <http://www.gnu.org/licenses/>.
-//
-
-
-
-module u1e_core
-  (input clk_fpga, input rst_fpga,
-   output [3:0] debug_led, output [31:0] debug, output [1:0] debug_clk,
-   output debug_txd, input debug_rxd,
-   
-   // GPMC
-   input EM_CLK, inout [15:0] EM_D, input [10:1] EM_A, input [1:0] EM_NBE,
-   input EM_WAIT0, input EM_NCS4, input EM_NCS5, input EM_NCS6,
-   input EM_NWE, input EM_NOE,
-   
-   inout db_sda, inout db_scl,
-   output sclk, output [15:0] sen, output mosi, input miso,
-
-   input cgen_st_status, input cgen_st_ld, input cgen_st_refmon, output cgen_sync_b, output cgen_ref_sel,   
-   output tx_have_space, output rx_have_data,
-   inout [15:0] io_tx, inout [15:0] io_rx, 
-   output [13:0] tx_i, output [13:0] tx_q, 
-   input [11:0] rx_i, input [11:0] rx_q, 
-   
-   input pps_in, output reg proc_int
-   );
-
-   localparam TXFIFOSIZE = 13;
-   localparam RXFIFOSIZE = 13;
-
-   // 64 total regs in address space
-   localparam SR_RX_CTRL0 = 0;       // 9 regs (+0 to +8)
-   localparam SR_RX_DSP0 = 10;       // 4 regs (+0 to +3)
-   localparam SR_RX_CTRL1 = 16;      // 9 regs (+0 to +8)
-   localparam SR_RX_DSP1 = 26;       // 4 regs (+0 to +3)
-   localparam SR_ERR_CTRL = 30;      // 1 reg
-   localparam SR_TX_CTRL = 32;       // 4 regs (+0 to +3)
-   localparam SR_TX_DSP = 38;        // 3 regs (+0 to +2)
-
-   localparam SR_TIME64 = 42;        // 6 regs (+0 to +5)
-   localparam SR_RX_FRONT = 48;      // 5 regs (+0 to +4)
-   localparam SR_TX_FRONT = 54;      // 5 regs (+0 to +4)
-
-   localparam SR_REG_TEST32 = 60;    // 1 reg
-   localparam SR_CLEAR_FIFO = 61;    // 1 reg
-   localparam SR_GLOBAL_RESET = 63;  // 1 reg
-   localparam SR_USER_REGS = 64;     // 2 regs
-
-   localparam SR_GPIO = 128;         // 5 regs
-   
-   wire 	wb_clk = clk_fpga;
-   wire 	wb_rst, global_reset;
-
-   wire 	pps_int;
-   wire [63:0] 	vita_time, vita_time_pps;
-   reg [15:0] 	reg_cgen_ctrl, reg_test, xfer_rate;
-   wire [7:0] 	test_rate;
-   wire [3:0] 	test_ctrl;
-
-   wire [7:0]  set_addr, set_addr_user;
-   wire [31:0] set_data, set_data_user;
-   wire        set_stb, set_stb_user;
-
-   wire [31:0] 	debug_vt;
-   wire 	rx_overrun_dsp0, rx_overrun_dsp1, rx_overrun_gpmc, tx_underrun_dsp, tx_underrun_gpmc;
-   wire 	rx_overrun = rx_overrun_gpmc | rx_overrun_dsp0 | rx_overrun_dsp1;
-   wire 	tx_underrun = tx_underrun_gpmc | tx_underrun_dsp;
-   
-   setting_reg #(.my_addr(SR_GLOBAL_RESET), .width(1)) sr_reset
-     (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr),
-      .in(set_data),.out(),.changed(global_reset));
-
-   reset_sync reset_sync(.clk(wb_clk), .reset_in(rst_fpga | global_reset), .reset_out(wb_rst));
-   
-   // /////////////////////////////////////////////////////////////////////////////////////
-   // GPMC Slave to Wishbone Master
-   localparam dw = 16;
-   localparam aw = 11;
-   localparam sw = 2;
-   
-   wire [dw-1:0] m0_dat_mosi, m0_dat_miso;
-   wire [aw-1:0] m0_adr;
-   wire [sw-1:0] m0_sel;
-   wire 	 m0_cyc, m0_stb, m0_we, m0_ack, m0_err, m0_rty;
-
-   wire [31:0] 	 debug_gpmc;
-
-   wire [35:0] 	 tx_data, rx_data, tx_err_data;
-   wire 	 tx_src_rdy, tx_dst_rdy, rx_src_rdy, rx_dst_rdy, 
-		 tx_err_src_rdy, tx_err_dst_rdy;
-
-   wire 	 clear_fifo;
-
-   setting_reg #(.my_addr(SR_CLEAR_FIFO), .width(1)) sr_clear_fifo
-     (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr),
-      .in(set_data),.out(),.changed(clear_fifo));
-
-   wire 	 run_rx0, run_rx1;
-
-   gpmc #(.TXFIFOSIZE(TXFIFOSIZE), .RXFIFOSIZE(RXFIFOSIZE))
-   gpmc (.arst(wb_rst),
-	 .EM_CLK(EM_CLK), .EM_D(EM_D), .EM_A(EM_A), .EM_NBE(EM_NBE),
-	 .EM_WAIT0(EM_WAIT0), .EM_NCS4(EM_NCS4), .EM_NCS6(EM_NCS6), .EM_NWE(EM_NWE), 
-	 .EM_NOE(EM_NOE),
-	 
-	 .rx_have_data(rx_have_data), .tx_have_space(tx_have_space),
-	 
-	 .wb_clk(wb_clk), .wb_rst(wb_rst),
-	 .wb_adr_o(m0_adr), .wb_dat_mosi(m0_dat_mosi), .wb_dat_miso(m0_dat_miso),
-	 .wb_sel_o(m0_sel), .wb_cyc_o(m0_cyc), .wb_stb_o(m0_stb), .wb_we_o(m0_we),
-	 .wb_ack_i(m0_ack),
-	 
-	 .fifo_clk(wb_clk), .fifo_rst(wb_rst), .clear_tx(clear_fifo), .clear_rx(clear_fifo),
-	 .tx_data_o(tx_data), .tx_src_rdy_o(tx_src_rdy), .tx_dst_rdy_i(tx_dst_rdy),
-	 .rx_data_i(rx_data), .rx_src_rdy_i(rx_src_rdy), .rx_dst_rdy_o(rx_dst_rdy),
-
-	 .tx_underrun(tx_underrun_gpmc), .rx_overrun(rx_overrun_gpmc),
-
-	 .test_rate(test_rate), .test_ctrl(test_ctrl),
-	 .debug(debug_gpmc));
-
-   wire 	 rx_src_rdy_int, rx_dst_rdy_int, tx_src_rdy_int, tx_dst_rdy_int;
-   
-   wire [31:0] 	 debug_rx_dsp, vrc_debug, vrf_debug, vr_debug;
-   
-   // /////////////////////////////////////////////////////////////////////////
-   // RX ADC Frontend, does IQ Balance, DC Offset, muxing
-
-   wire [23:0] 	 rx_fe_i, rx_fe_q;  // 24 bits is total overkill here, but it matches u2/u2p
-
-   rx_frontend #(.BASE(SR_RX_FRONT)) rx_frontend
-     (.clk(wb_clk),.rst(wb_rst),
-      .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data),
-      .adc_a({rx_i,4'b00}),.adc_ovf_a(0),
-      .adc_b({rx_q,4'b00}),.adc_ovf_b(0),
-      .i_out(rx_fe_i), .q_out(rx_fe_q), .run(run_rx0 | run_rx1), .debug());
-   
-   // /////////////////////////////////////////////////////////////////////////
-   // DSP RX 0
-
-   wire [31:0] 	 sample_rx0;
-   wire 	 strobe_rx0, clear_rx0;
-   wire [35:0] 	 vita_rx_data0;
-   wire 	 vita_rx_src_rdy0, vita_rx_dst_rdy0;
-   
-   ddc_chain #(.BASE(SR_RX_DSP0), .DSPNO(0)) ddc_chain0
-     (.clk(wb_clk), .rst(wb_rst), .clr(clear_rx0),
-      .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data),
-      .set_stb_user(set_stb_user), .set_addr_user(set_addr_user), .set_data_user(set_data_user),
-      .rx_fe_i(rx_fe_i),.rx_fe_q(rx_fe_q),
-      .sample(sample_rx0), .run(run_rx0), .strobe(strobe_rx0),
-      .debug() );
-
-   vita_rx_chain #(.BASE(SR_RX_CTRL0), .UNIT(0), .FIFOSIZE(10), .PROT_ENG_FLAGS(0), .DSP_NUMBER(0)) vita_rx_chain0
-     (.clk(wb_clk),.reset(wb_rst),
-      .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data),
-      .set_stb_user(set_stb_user), .set_addr_user(set_addr_user), .set_data_user(set_data_user),
-      .vita_time(vita_time), .overrun(rx_overrun_dsp0),
-      .sample(sample_rx0), .run(run_rx0), .strobe(strobe_rx0), .clear_o(clear_rx0),
-      .rx_data_o(vita_rx_data0), .rx_dst_rdy_i(vita_rx_dst_rdy0), .rx_src_rdy_o(vita_rx_src_rdy0),
-      .debug() );
-   
-   // /////////////////////////////////////////////////////////////////////////
-   // DSP RX 1
-
-   wire [31:0] 	 sample_rx1;
-   wire 	 strobe_rx1, clear_rx1;
-   wire [35:0] 	 vita_rx_data1;
-   wire 	 vita_rx_src_rdy1, vita_rx_dst_rdy1;
-   
-   ddc_chain #(.BASE(SR_RX_DSP1), .DSPNO(1)) ddc_chain1
-     (.clk(wb_clk),.rst(wb_rst), .clr(clear_rx1),
-      .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data),
-      .set_stb_user(set_stb_user), .set_addr_user(set_addr_user), .set_data_user(set_data_user),
-      .rx_fe_i(rx_fe_i),.rx_fe_q(rx_fe_q),
-      .sample(sample_rx1), .run(run_rx1), .strobe(strobe_rx1),
-      .debug() );
-
-   vita_rx_chain #(.BASE(SR_RX_CTRL1), .UNIT(1), .FIFOSIZE(10), .PROT_ENG_FLAGS(0), .DSP_NUMBER(1)) vita_rx_chain1
-     (.clk(wb_clk),.reset(wb_rst),
-      .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data),
-      .set_stb_user(set_stb_user), .set_addr_user(set_addr_user), .set_data_user(set_data_user),
-      .vita_time(vita_time), .overrun(rx_overrun_dsp1),
-      .sample(sample_rx1), .run(run_rx1), .strobe(strobe_rx1), .clear_o(clear_rx1),
-      .rx_data_o(vita_rx_data1), .rx_dst_rdy_i(vita_rx_dst_rdy1), .rx_src_rdy_o(vita_rx_src_rdy1),
-      .debug() );
-
-   // /////////////////////////////////////////////////////////////////////////
-   // RX Stream muxing
-
-   fifo36_mux #(.prio(0)) mux_data_streams
-     (.clk(wb_clk), .reset(wb_rst), .clear(clear_fifo),
-      .data0_i(vita_rx_data0), .src0_rdy_i(vita_rx_src_rdy0), .dst0_rdy_o(vita_rx_dst_rdy0),
-      .data1_i(vita_rx_data1), .src1_rdy_i(vita_rx_src_rdy1), .dst1_rdy_o(vita_rx_dst_rdy1),
-      .data_o(rx_data), .src_rdy_o(rx_src_rdy), .dst_rdy_i(rx_dst_rdy));
-
-   // ///////////////////////////////////////////////////////////////////////////////////
-   // DSP TX
-
-   wire 	 run_tx;
-   wire [23:0] 	 tx_fe_i, tx_fe_q;
-   wire [31:0]   sample_tx;
-   wire strobe_tx, clear_tx;
-
-   vita_tx_chain #(.BASE(SR_TX_CTRL), .FIFOSIZE(10), .POST_ENGINE_FIFOSIZE(11),
-		   .REPORT_ERROR(1), .DO_FLOW_CONTROL(0),
-		   .PROT_ENG_FLAGS(0), .USE_TRANS_HEADER(0),
-		   .DSP_NUMBER(0)) 
-   vita_tx_chain
-     (.clk(wb_clk), .reset(wb_rst),
-      .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data),
-      .set_stb_user(set_stb_user), .set_addr_user(set_addr_user), .set_data_user(set_data_user),
-      .vita_time(vita_time),
-      .tx_data_i(tx_data), .tx_src_rdy_i(tx_src_rdy), .tx_dst_rdy_o(tx_dst_rdy),
-      .err_data_o(tx_err_data), .err_src_rdy_o(tx_err_src_rdy), .err_dst_rdy_i(tx_err_dst_rdy),
-      .sample(sample_tx), .strobe(strobe_tx),
-      .underrun(tx_underrun_dsp), .run(run_tx), .clear_o(clear_tx),
-      .debug(debug_vt));
-
-   duc_chain #(.BASE(SR_TX_DSP), .DSPNO(0)) duc_chain
-     (.clk(wb_clk), .rst(wb_rst), .clr(clear_tx),
-      .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data),
-      .set_stb_user(set_stb_user), .set_addr_user(set_addr_user), .set_data_user(set_data_user),
-      .tx_fe_i(tx_fe_i),.tx_fe_q(tx_fe_q),
-      .sample(sample_tx), .run(run_tx), .strobe(strobe_tx),
-      .debug() );
-
-   tx_frontend #(.BASE(SR_TX_FRONT), .WIDTH_OUT(14)) tx_frontend
-     (.clk(wb_clk), .rst(wb_rst),
-      .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data),
-      .tx_i(tx_fe_i), .tx_q(tx_fe_q), .run(1'b1),
-      .dac_a(tx_i), .dac_b(tx_q));
-
-   // /////////////////////////////////////////////////////////////////////////////////////
-   // Wishbone Intercon, single master
-   wire [dw-1:0] s0_dat_mosi, s1_dat_mosi, s0_dat_miso, s1_dat_miso, s2_dat_mosi, s3_dat_mosi, s2_dat_miso, s3_dat_miso,
-		 s4_dat_mosi, s5_dat_mosi, s4_dat_miso, s5_dat_miso, s6_dat_mosi, s7_dat_mosi, s6_dat_miso, s7_dat_miso,
-		 s8_dat_mosi, s9_dat_mosi, s8_dat_miso, s9_dat_miso, sa_dat_mosi, sb_dat_mosi, sa_dat_miso, sb_dat_miso,
-		 sc_dat_mosi, sd_dat_mosi, sc_dat_miso, sd_dat_miso, se_dat_mosi, sf_dat_mosi, se_dat_miso, sf_dat_miso;
-   wire [aw-1:0] s0_adr,s1_adr,s2_adr,s3_adr,s4_adr,s5_adr,s6_adr,s7_adr;
-   wire [aw-1:0] s8_adr,s9_adr,sa_adr,sb_adr,sc_adr, sd_adr, se_adr, sf_adr;
-   wire [sw-1:0] s0_sel,s1_sel,s2_sel,s3_sel,s4_sel,s5_sel,s6_sel,s7_sel;
-   wire [sw-1:0] s8_sel,s9_sel,sa_sel,sb_sel,sc_sel, sd_sel, se_sel, sf_sel;
-   wire 	 s0_ack,s1_ack,s2_ack,s3_ack,s4_ack,s5_ack,s6_ack,s7_ack;
-   wire 	 s8_ack,s9_ack,sa_ack,sb_ack,sc_ack, sd_ack, se_ack, sf_ack;
-   wire 	 s0_stb,s1_stb,s2_stb,s3_stb,s4_stb,s5_stb,s6_stb,s7_stb;
-   wire 	 s8_stb,s9_stb,sa_stb,sb_stb,sc_stb, sd_stb, se_stb, sf_stb;
-   wire 	 s0_cyc,s1_cyc,s2_cyc,s3_cyc,s4_cyc,s5_cyc,s6_cyc,s7_cyc;
-   wire 	 s8_cyc,s9_cyc,sa_cyc,sb_cyc,sc_cyc, sd_cyc, se_cyc, sf_cyc;
-   wire 	 s0_we,s1_we,s2_we,s3_we,s4_we,s5_we,s6_we,s7_we;
-   wire 	 s8_we,s9_we,sa_we,sb_we,sc_we,sd_we, se_we, sf_we;
-   
-   wb_1master #(.dw(dw), .aw(aw), .sw(sw), .decode_w(4),
-		.s0_addr(4'h0), .s0_mask(4'hF), // Misc Regs
-		.s1_addr(4'h1), .s1_mask(4'hF), // Unused
-		.s2_addr(4'h2), .s2_mask(4'hF),	// SPI
-		.s3_addr(4'h3), .s3_mask(4'hF), // I2C
-		.s4_addr(4'h4), .s4_mask(4'hF),	// Unused
-		.s5_addr(4'h5), .s5_mask(4'hF), // Unused on B1x0, Async Msg on E1x0
-		.s6_addr(4'h6), .s6_mask(4'hF),	// Unused
-		.s7_addr(4'h7), .s7_mask(4'hF), // Readback MUX
-		.s8_addr(4'h8), .s8_mask(4'h8), // Setting Regs -- slave 8 is 8 slaves wide
-		// slaves 9-f alias to slave 1, all are unused
-		.s9_addr(4'h1), .s9_mask(4'hF),
-		.sa_addr(4'h1), .sa_mask(4'hF),	.sb_addr(4'h1), .sb_mask(4'hF),
-		.sc_addr(4'h1), .sc_mask(4'hF),	.sd_addr(4'h1), .sd_mask(4'hF),
-		.se_addr(4'h1), .se_mask(4'hF),	.sf_addr(4'h1), .sf_mask(4'hF))
-   wb_1master
-     (.clk_i(wb_clk),.rst_i(wb_rst),       
-      .m0_dat_o(m0_dat_miso),.m0_ack_o(m0_ack),.m0_err_o(m0_err),.m0_rty_o(m0_rty),.m0_dat_i(m0_dat_mosi),
-      .m0_adr_i(m0_adr),.m0_sel_i(m0_sel),.m0_we_i(m0_we),.m0_cyc_i(m0_cyc),.m0_stb_i(m0_stb),
-      .s0_dat_o(s0_dat_mosi),.s0_adr_o(s0_adr),.s0_sel_o(s0_sel),.s0_we_o(s0_we),.s0_cyc_o(s0_cyc),.s0_stb_o(s0_stb),
-      .s0_dat_i(s0_dat_miso),.s0_ack_i(s0_ack),.s0_err_i(0),.s0_rty_i(0),
-      .s1_dat_o(s1_dat_mosi),.s1_adr_o(s1_adr),.s1_sel_o(s1_sel),.s1_we_o(s1_we),.s1_cyc_o(s1_cyc),.s1_stb_o(s1_stb),
-      .s1_dat_i(s1_dat_miso),.s1_ack_i(s1_ack),.s1_err_i(0),.s1_rty_i(0),
-      .s2_dat_o(s2_dat_mosi),.s2_adr_o(s2_adr),.s2_sel_o(s2_sel),.s2_we_o(s2_we),.s2_cyc_o(s2_cyc),.s2_stb_o(s2_stb),
-      .s2_dat_i(s2_dat_miso),.s2_ack_i(s2_ack),.s2_err_i(0),.s2_rty_i(0),
-      .s3_dat_o(s3_dat_mosi),.s3_adr_o(s3_adr),.s3_sel_o(s3_sel),.s3_we_o(s3_we),.s3_cyc_o(s3_cyc),.s3_stb_o(s3_stb),
-      .s3_dat_i(s3_dat_miso),.s3_ack_i(s3_ack),.s3_err_i(0),.s3_rty_i(0),
-      .s4_dat_o(s4_dat_mosi),.s4_adr_o(s4_adr),.s4_sel_o(s4_sel),.s4_we_o(s4_we),.s4_cyc_o(s4_cyc),.s4_stb_o(s4_stb),
-      .s4_dat_i(s4_dat_miso),.s4_ack_i(s4_ack),.s4_err_i(0),.s4_rty_i(0),
-      .s5_dat_o(s5_dat_mosi),.s5_adr_o(s5_adr),.s5_sel_o(s5_sel),.s5_we_o(s5_we),.s5_cyc_o(s5_cyc),.s5_stb_o(s5_stb),
-      .s5_dat_i(s5_dat_miso),.s5_ack_i(s5_ack),.s5_err_i(0),.s5_rty_i(0),
-      .s6_dat_o(s6_dat_mosi),.s6_adr_o(s6_adr),.s6_sel_o(s6_sel),.s6_we_o(s6_we),.s6_cyc_o(s6_cyc),.s6_stb_o(s6_stb),
-      .s6_dat_i(s6_dat_miso),.s6_ack_i(s6_ack),.s6_err_i(0),.s6_rty_i(0),
-      .s7_dat_o(s7_dat_mosi),.s7_adr_o(s7_adr),.s7_sel_o(s7_sel),.s7_we_o(s7_we),.s7_cyc_o(s7_cyc),.s7_stb_o(s7_stb),
-      .s7_dat_i(s7_dat_miso),.s7_ack_i(s7_ack),.s7_err_i(0),.s7_rty_i(0),
-      .s8_dat_o(s8_dat_mosi),.s8_adr_o(s8_adr),.s8_sel_o(s8_sel),.s8_we_o(s8_we),.s8_cyc_o(s8_cyc),.s8_stb_o(s8_stb),
-      .s8_dat_i(s8_dat_miso),.s8_ack_i(s8_ack),.s8_err_i(0),.s8_rty_i(0),
-      .s9_dat_o(s9_dat_mosi),.s9_adr_o(s9_adr),.s9_sel_o(s9_sel),.s9_we_o(s9_we),.s9_cyc_o(s9_cyc),.s9_stb_o(s9_stb),
-      .s9_dat_i(s9_dat_miso),.s9_ack_i(s9_ack),.s9_err_i(0),.s9_rty_i(0),
-      .sa_dat_o(sa_dat_mosi),.sa_adr_o(sa_adr),.sa_sel_o(sa_sel),.sa_we_o(sa_we),.sa_cyc_o(sa_cyc),.sa_stb_o(sa_stb),
-      .sa_dat_i(sa_dat_miso),.sa_ack_i(sa_ack),.sa_err_i(0),.sa_rty_i(0),
-      .sb_dat_o(sb_dat_mosi),.sb_adr_o(sb_adr),.sb_sel_o(sb_sel),.sb_we_o(sb_we),.sb_cyc_o(sb_cyc),.sb_stb_o(sb_stb),
-      .sb_dat_i(sb_dat_miso),.sb_ack_i(sb_ack),.sb_err_i(0),.sb_rty_i(0),
-      .sc_dat_o(sc_dat_mosi),.sc_adr_o(sc_adr),.sc_sel_o(sc_sel),.sc_we_o(sc_we),.sc_cyc_o(sc_cyc),.sc_stb_o(sc_stb),
-      .sc_dat_i(sc_dat_miso),.sc_ack_i(sc_ack),.sc_err_i(0),.sc_rty_i(0),
-      .sd_dat_o(sd_dat_mosi),.sd_adr_o(sd_adr),.sd_sel_o(sd_sel),.sd_we_o(sd_we),.sd_cyc_o(sd_cyc),.sd_stb_o(sd_stb),
-      .sd_dat_i(sd_dat_miso),.sd_ack_i(sd_ack),.sd_err_i(0),.sd_rty_i(0),
-      .se_dat_o(se_dat_mosi),.se_adr_o(se_adr),.se_sel_o(se_sel),.se_we_o(se_we),.se_cyc_o(se_cyc),.se_stb_o(se_stb),
-      .se_dat_i(se_dat_miso),.se_ack_i(se_ack),.se_err_i(0),.se_rty_i(0),
-      .sf_dat_o(sf_dat_mosi),.sf_adr_o(sf_adr),.sf_sel_o(sf_sel),.sf_we_o(sf_we),.sf_cyc_o(sf_cyc),.sf_stb_o(sf_stb),
-      .sf_dat_i(sf_dat_miso),.sf_ack_i(sf_ack),.sf_err_i(0),.sf_rty_i(0) );
-
-   assign s1_ack = 0;   assign s4_ack = 0;   assign s6_ack = 0;
-   assign s9_ack = 0;   assign sa_ack = 0;   assign sb_ack = 0;
-   assign sc_ack = 0;   assign sd_ack = 0;   assign se_ack = 0;   assign sf_ack = 0;
-
-   // /////////////////////////////////////////////////////////////////////////////////////
-   // Slave 0, Misc LEDs, Switches, controls
-   
-   localparam REG_CGEN_CTRL = 7'd4;    // out
-   localparam REG_CGEN_ST = 7'd6;      // in
-   localparam REG_TEST = 7'd8;         // out
-   localparam REG_XFER_RATE = 7'd14;   // out
-   
-   always @(posedge wb_clk)
-     if(wb_rst)
-       begin
-	  reg_cgen_ctrl <= 2'b11;
-	  reg_test <= 0;
-	  xfer_rate <= 0;
-       end
-     else
-       if(s0_cyc & s0_stb & s0_we) 
-	 case(s0_adr[6:0])
-	   REG_CGEN_CTRL :
-	     reg_cgen_ctrl <= s0_dat_mosi;
-	   REG_TEST :
-	     reg_test <= s0_dat_mosi;
-	   REG_XFER_RATE :
-	     xfer_rate <= s0_dat_mosi;
-	 endcase // case (s0_adr[6:0])
-
-   assign test_ctrl = xfer_rate[11:8];
-   assign test_rate = xfer_rate[7:0];
-   
-   assign { debug_led[3:0] } = ~{1'b1, run_tx, run_rx0 | run_rx1, cgen_st_ld};
-   assign { cgen_sync_b, cgen_ref_sel } = reg_cgen_ctrl;
-   
-   assign s0_dat_miso = (s0_adr[6:0] == REG_CGEN_CTRL) ? reg_cgen_ctrl :
-			(s0_adr[6:0] == REG_CGEN_ST) ? {13'b0,cgen_st_status,cgen_st_ld,cgen_st_refmon} :
-			(s0_adr[6:0] == REG_TEST) ? reg_test :
-			16'hBEEF;
-   
-   assign s0_ack = s0_stb & s0_cyc;
-
-   // /////////////////////////////////////////////////////////////////////////////////////
-   // Slave 2, SPI
-
-   spi_top16 shared_spi
-     (.wb_clk_i(wb_clk),.wb_rst_i(wb_rst),.wb_adr_i(s2_adr[4:0]),.wb_dat_i(s2_dat_mosi),
-      .wb_dat_o(s2_dat_miso),.wb_sel_i(s2_sel),.wb_we_i(s2_we),.wb_stb_i(s2_stb),
-      .wb_cyc_i(s2_cyc),.wb_ack_o(s2_ack),.wb_err_o(),.wb_int_o(),
-      .ss_pad_o(sen), .sclk_pad_o(sclk), .mosi_pad_o(mosi), .miso_pad_i(miso) );
-   
-   // /////////////////////////////////////////////////////////////////////////
-   // Slave 3, I2C
-
-   wire 	scl_pad_i, scl_pad_o, scl_pad_oen_o, sda_pad_i, sda_pad_o, sda_pad_oen_o;
-   i2c_master_top #(.ARST_LVL(1)) i2c 
-     (.wb_clk_i(wb_clk),.wb_rst_i(wb_rst),.arst_i(1'b0), 
-      .wb_adr_i(s3_adr[3:1]),.wb_dat_i(s3_dat_mosi[7:0]),.wb_dat_o(s3_dat_miso[7:0]),
-      .wb_we_i(s3_we),.wb_stb_i(s3_stb),.wb_cyc_i(s3_cyc),
-      .wb_ack_o(s3_ack),.wb_inta_o(),
-      .scl_pad_i(scl_pad_i),.scl_pad_o(scl_pad_o),.scl_padoen_o(scl_pad_oen_o),
-      .sda_pad_i(sda_pad_i),.sda_pad_o(sda_pad_o),.sda_padoen_o(sda_pad_oen_o) );
-
-   assign 	 s3_dat_miso[15:8] = 8'd0;
-
-   // I2C -- Don't use external transistors for open drain, the FPGA implements this
-   IOBUF scl_pin(.O(scl_pad_i), .IO(db_scl), .I(scl_pad_o), .T(scl_pad_oen_o));
-   IOBUF sda_pin(.O(sda_pad_i), .IO(db_sda), .I(sda_pad_o), .T(sda_pad_oen_o));
-
-   // /////////////////////////////////////////////////////////////////////////
-   // GPIOs
-
-   wire [31:0] gpio_readback;
-   
-   gpio_atr #(.BASE(SR_GPIO), .WIDTH(32)) 
-   gpio_atr(.clk(wb_clk),.reset(wb_rst),
-	    .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data),
-	    .rx(run_rx0 | run_rx1), .tx(run_tx),
-	    .gpio({io_tx,io_rx}), .gpio_readback(gpio_readback) );
-
-   ////////////////////////////////////////////////////////////////////////////
-   // FIFO to WB slave for async messages - Slave #5
-
-   //signals between fifo and buffer module
-   wire [35:0] _tx_err_data;
-   wire _tx_err_src_rdy, _tx_err_dst_rdy;
-
-   fifo_cascade #(.WIDTH(36), .SIZE(9/*512 lines plenty for short pkts*/)) err_fifo(
-        .clk(wb_clk), .reset(wb_rst), .clear(wb_rst),
-        .datain(tx_err_data),   .src_rdy_i(tx_err_src_rdy),   .dst_rdy_o(tx_err_dst_rdy),
-        .dataout(_tx_err_data), .src_rdy_o(_tx_err_src_rdy),  .dst_rdy_i(_tx_err_dst_rdy)
-   );
-
-   wire [31:0] err_status, err_data32;
-   //the buffer is 32 bits, but the data is 16, so mux based on the addr bit
-   assign s5_dat_miso = (s5_adr[1] == 1'b0)? err_data32[15:0] : err_data32[31:16];
-
-   buffer_int2 #(.BASE(SR_ERR_CTRL), .BUF_SIZE(5)) fifo_to_wb(
-        .clk(wb_clk), .rst(wb_rst),
-        .set_stb(set_stb), .set_addr(set_addr), .set_data(set_data),
-        .status(err_status),
-        // Wishbone interface to RAM
-        .wb_clk_i(wb_clk), .wb_rst_i(wb_rst),
-        .wb_we_i(s5_we),   .wb_stb_i(s5_stb),
-        .wb_adr_i({5'b0,s5_adr}), .wb_dat_i({16'b0, s5_dat_mosi}),
-        .wb_dat_o(err_data32), .wb_ack_o(s5_ack),
-        // Write FIFO Interface
-        .wr_data_i(_tx_err_data), .wr_ready_i(_tx_err_src_rdy), .wr_ready_o(_tx_err_dst_rdy),
-        // Read FIFO Interface
-        .rd_data_o(), .rd_ready_o(), .rd_ready_i(1'b0)
-    );
-
-   ////////////////////////////////////////////////////////////////////////////
-   // Interrupts
-
-   always @(posedge wb_clk)
-     proc_int <= (|err_status[1:0]);
-
-   // /////////////////////////////////////////////////////////////////////////
-   // Settings Bus -- Slave #8 + 9
-
-   // only have 64 regs, 32 bits each with current setup...
-   settings_bus_16LE #(.AWIDTH(11),.RWIDTH(8)) settings_bus_16LE
-     (.wb_clk(wb_clk),.wb_rst(wb_rst),.wb_adr_i(s8_adr),.wb_dat_i(s8_dat_mosi),
-      .wb_stb_i(s8_stb),.wb_we_i(s8_we),.wb_ack_o(s8_ack),
-      .strobe(set_stb),.addr(set_addr),.data(set_data) );
-
-   user_settings #(.BASE(SR_USER_REGS)) user_settings
-     (.clk(wb_clk),.rst(wb_rst),.set_stb(set_stb),
-      .set_addr(set_addr),.set_data(set_data),
-      .set_addr_user(set_addr_user),.set_data_user(set_data_user),
-      .set_stb_user(set_stb_user) );
-
-   // /////////////////////////////////////////////////////////////////////////
-   // Readback mux 32 -- Slave #7
-
-   //compatibility number -> increment when the fpga has been sufficiently altered
-   localparam compat_num = {16'd10, 16'd2}; //major, minor
-
-   wire [31:0] reg_test32;
-
-   //this setting reg is persistent across resets, to check for fpga loaded
-   setting_reg #(.my_addr(SR_REG_TEST32)) sr_reg_test32
-     (.clk(wb_clk),.rst(/*wb_rst*/1'b0),.strobe(set_stb),.addr(set_addr),
-      .in(set_data),.out(reg_test32),.changed());
-
-   wb_readback_mux_16LE readback_mux_32
-     (.wb_clk_i(wb_clk), .wb_rst_i(wb_rst), .wb_stb_i(s7_stb),
-      .wb_adr_i({5'b0,s7_adr}), .wb_dat_o(s7_dat_miso), .wb_ack_o(s7_ack),
-
-      .word00(vita_time[63:32]),        .word01(vita_time[31:0]),
-      .word02(vita_time_pps[63:32]),    .word03(vita_time_pps[31:0]),
-      .word04(reg_test32),              .word05(err_status),
-      .word06(compat_num),              .word07(gpio_readback),
-      .word08(32'b0),                   .word09(32'b0),
-      .word10(32'b0),                   .word11(32'b0),
-      .word12(32'b0),                   .word13(32'b0),
-      .word14(32'b0),                   .word15(32'b0)
-      );
-
-   // /////////////////////////////////////////////////////////////////////////
-   // VITA Timing
-
-   time_64bit #(.BASE(SR_TIME64)) time_64bit
-     (.clk(wb_clk), .rst(wb_rst), .set_stb(set_stb), .set_addr(set_addr), .set_data(set_data),
-      .pps(pps_in), .vita_time(vita_time), .vita_time_pps(vita_time_pps), .pps_int(pps_int),
-      .exp_time_in(0));
-   
-   // /////////////////////////////////////////////////////////////////////////////////////
-   // Debug circuitry
-
-   assign debug_clk = 2'b00; //{ EM_CLK, clk_fpga };
-   assign debug = 0;
-   
-endmodule // u1e_core