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| author | Johnathan Corgan <jcorgan@corganenterprises.com> | 2010-03-29 15:35:06 -0700 |
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| committer | Johnathan Corgan <jcorgan@corganenterprises.com> | 2010-03-29 15:35:06 -0700 |
| commit | 50b1ca13e651152a731d3fdf7a5f532b65e04e13 (patch) | |
| tree | 6f70f0fd06a53cec4d65be384f437997caada5a4 /fpga | |
| parent | 5642e3be330b707254625de7ce33fa219edf0ab9 (diff) | |
| download | uhd-50b1ca13e651152a731d3fdf7a5f532b65e04e13.tar.gz uhd-50b1ca13e651152a731d3fdf7a5f532b65e04e13.tar.bz2 uhd-50b1ca13e651152a731d3fdf7a5f532b65e04e13.zip | |
Added timing constraint for Wishbone clock/dsp_clock skew
Diffstat (limited to 'fpga')
0 files changed, 0 insertions, 0 deletions