Merge branch 'uhd_master'

21 files changed, 886 insertions, 52 deletions

diff --git a/fpga/usrp1/common/fpga_regs_common.v b/fpga/usrp1/common/fpga_regs_common.v
new file mode 100644
index 000000000..8035d8565
--- /dev/null
+++ b/fpga/usrp1/common/fpga_regs_common.v
@@ -0,0 +1,117 @@
+//
+// This file is machine generated from ./fpga_regs_common.h
+// Do not edit by hand; your edits will be overwritten.
+//
+
+// This file defines registers common to all FPGA configurations.
+// Registers 0 to 31 are reserved for use in this file.
+
+
+// The FPGA needs to know the rate that samples are coming from and
+// going to the A/D's and D/A's.  div = 128e6 / sample_rate
+
+`define FR_TX_SAMPLE_RATE_DIV     7'd0
+`define FR_RX_SAMPLE_RATE_DIV     7'd1
+
+// 2 and 3 are defined in the ATR section
+
+`define FR_MASTER_CTRL            7'd4	// master enable and reset controls
+
+// i/o direction registers for pins that go to daughterboards.
+// Setting the bit makes it an output from the FPGA to the d'board.
+// top 16 is mask, low 16 is value
+
+`define FR_OE_0                   7'd5	// slot 0
+`define FR_OE_1                   7'd6
+`define FR_OE_2                   7'd7
+`define FR_OE_3                   7'd8
+
+// i/o registers for pins that go to daughterboards.
+// top 16 is a mask, low 16 is value
+
+`define FR_IO_0                   7'd9	// slot 0
+`define FR_IO_1                   7'd10
+`define FR_IO_2                   7'd11
+`define FR_IO_3                   7'd12
+
+`define FR_MODE                   7'd13
+
+
+// If the corresponding bit is set, internal FPGA debug circuitry
+// controls the i/o pins for the associated bank of daughterboard
+// i/o pins.  Typically used for debugging FPGA designs.
+
+`define FR_DEBUG_EN               7'd14
+
+
+// If the corresponding bit is set, enable the automatic DC
+// offset correction control loop.
+//
+// The 4 low bits are significant:
+//
+//   ADC0 = (1 << 0)
+//   ADC1 = (1 << 1)
+//   ADC2 = (1 << 2)
+//   ADC3 = (1 << 3)
+//
+// This control loop works if the attached daugherboard blocks DC.
+// Currently all daughterboards do block DC.  This includes:
+// basic rx, dbs_rx, tv_rx, flex_xxx_rx.
+
+`define FR_DC_OFFSET_CL_EN        7'd15			// DC Offset Control Loop Enable
+
+
+// offset corrections for ADC's and DAC's (2's complement)
+
+`define FR_ADC_OFFSET_0           7'd16
+`define FR_ADC_OFFSET_1           7'd17
+`define FR_ADC_OFFSET_2           7'd18
+`define FR_ADC_OFFSET_3           7'd19
+
+
+// ------------------------------------------------------------------------
+// Automatic Transmit/Receive switching
+//
+// If automatic transmit/receive (ATR) switching is enabled in the
+// FR_ATR_CTL register, the presence or absence of data in the FPGA
+// transmit fifo selects between two sets of values for each of the 4
+// banks of daughterboard i/o pins.
+//
+// Each daughterboard slot has 3 16-bit registers associated with it:
+//   FR_ATR_MASK_*, FR_ATR_TXVAL_* and FR_ATR_RXVAL_*
+//
+// FR_ATR_MASK_{0,1,2,3}: 
+//
+//   These registers determine which of the daugherboard i/o pins are
+//   affected by ATR switching.  If a bit in the mask is set, the
+//   corresponding i/o bit is controlled by ATR, else it's output
+//   value comes from the normal i/o pin output register:
+//   FR_IO_{0,1,2,3}.
+//
+// FR_ATR_TXVAL_{0,1,2,3}:
+// FR_ATR_RXVAL_{0,1,2,3}:
+//
+//   If the Tx fifo contains data, then the bits from TXVAL that are
+//   selected by MASK are output.  Otherwise, the bits from RXVAL that
+//   are selected by MASK are output.
+                      
+`define FR_ATR_MASK_0             7'd20	// slot 0
+`define FR_ATR_TXVAL_0            7'd21
+`define FR_ATR_RXVAL_0            7'd22
+
+`define FR_ATR_MASK_1             7'd23	// slot 1
+`define FR_ATR_TXVAL_1            7'd24
+`define FR_ATR_RXVAL_1            7'd25
+
+`define FR_ATR_MASK_2             7'd26	// slot 2
+`define FR_ATR_TXVAL_2            7'd27
+`define FR_ATR_RXVAL_2            7'd28
+
+`define FR_ATR_MASK_3             7'd29	// slot 3
+`define FR_ATR_TXVAL_3            7'd30
+`define FR_ATR_RXVAL_3            7'd31
+
+// Clock ticks to delay rising and falling edge of T/R signal
+`define FR_ATR_TX_DELAY           7'd2
+`define FR_ATR_RX_DELAY           7'd3
+
diff --git a/fpga/usrp1/common/fpga_regs_standard.v b/fpga/usrp1/common/fpga_regs_standard.v
new file mode 100644
index 000000000..d09aa6116
--- /dev/null
+++ b/fpga/usrp1/common/fpga_regs_standard.v
@@ -0,0 +1,256 @@
+//
+// This file is machine generated from ./fpga_regs_standard.h
+// Do not edit by hand; your edits will be overwritten.
+//
+
+// Register numbers 0 to 31 are reserved for use in fpga_regs_common.h.
+// Registers 64 to 79 are available for custom FPGA builds.
+
+
+// DDC / DUC
+
+`define FR_INTERP_RATE            7'd32	// [1,1024]
+`define FR_DECIM_RATE             7'd33	// [1,256]
+
+// DDC center freq
+
+`define FR_RX_FREQ_0              7'd34
+`define FR_RX_FREQ_1              7'd35
+`define FR_RX_FREQ_2              7'd36
+`define FR_RX_FREQ_3              7'd37
+
+// See below for DDC Starting Phase
+
+// ------------------------------------------------------------------------
+//  configure FPGA Rx mux
+//
+//    3                   2                   1                       
+//  1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
+// +-----------------------+-------+-------+-------+-------+-+-----+
+// |      must be zero     | Q3| I3| Q2| I2| Q1| I1| Q0| I0|Z| NCH |
+// +-----------------------+-------+-------+-------+-------+-+-----+
+//
+// There are a maximum of 4 digital downconverters in the the FPGA.
+// Each DDC has two 16-bit inputs, I and Q, and two 16-bit outputs, I & Q.
+//
+// DDC I inputs are specified by the two bit fields I3, I2, I1 & I0
+//
+//   0 = DDC input is from ADC 0
+//   1 = DDC input is from ADC 1
+//   2 = DDC input is from ADC 2
+//   3 = DDC input is from ADC 3
+//
+// If Z == 1, all DDC Q inputs are set to zero
+// If Z == 0, DDC Q inputs are specified by the two bit fields Q3, Q2, Q1 & Q0
+//
+// NCH specifies the number of complex channels that are sent across
+// the USB.  The legal values are 1, 2 or 4, corresponding to 2, 4 or
+// 8 16-bit values.
+
+`define FR_RX_MUX                 7'd38
+
+// ------------------------------------------------------------------------
+//  configure FPGA Tx Mux.
+//
+//    3                   2                   1                       
+//  1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
+// +-----------------------+-------+-------+-------+-------+-+-----+
+// |                       | DAC3  | DAC2  | DAC1  |  DAC0 |0| NCH |
+// +-----------------------------------------------+-------+-+-----+
+//
+// NCH specifies the number of complex channels that are sent across
+// the USB.  The legal values are 1 or 2, corresponding to 2 or 4
+// 16-bit values.
+//
+// There are two interpolators with complex inputs and outputs.
+// There are four DACs.  (We use the DUC in each AD9862.)
+//
+// Each 4-bit DACx field specifies the source for the DAC and
+// whether or not that DAC is enabled.  Each subfield is coded
+// like this: 
+//
+//    3 2 1 0
+//   +-+-----+
+//   |E|  N  |
+//   +-+-----+
+//
+// Where E is set if the DAC is enabled, and N specifies which
+// interpolator output is connected to this DAC.
+//
+//  N   which interp output
+// ---  -------------------
+//  0   chan 0 I
+//  1   chan 0 Q
+//  2   chan 1 I
+//  3   chan 1 Q
+
+`define FR_TX_MUX                 7'd39
+
+// ------------------------------------------------------------------------
+// REFCLK control
+//
+// Control whether a reference clock is sent to the daughterboards,
+// and what frequency.  The refclk is sent on d'board i/o pin 0.
+//
+//    3                   2                   1                       
+//  1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
+// +-----------------------------------------------+-+------------+
+// |             Reserved (Must be zero)           |E|   DIVISOR  |
+// +-----------------------------------------------+-+------------+
+
+//
+// Bit 7  -- 1 turns on refclk, 0 allows IO use
+// Bits 6:0 Divider value
+
+`define FR_TX_A_REFCLK            7'd40
+`define FR_RX_A_REFCLK            7'd41
+`define FR_TX_B_REFCLK            7'd42
+`define FR_RX_B_REFCLK            7'd43
+
+
+// ------------------------------------------------------------------------
+// DDC Starting Phase
+
+`define FR_RX_PHASE_0             7'd44
+`define FR_RX_PHASE_1             7'd45
+`define FR_RX_PHASE_2             7'd46
+`define FR_RX_PHASE_3             7'd47
+
+// ------------------------------------------------------------------------
+// Tx data format control register
+//
+//    3                   2                   1                       
+//  1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
+// +-------------------------------------------------------+-------+
+// |                    Reserved (Must be zero)            |  FMT  |
+// +-------------------------------------------------------+-------+
+//
+//  FMT values:
+
+`define FR_TX_FORMAT              7'd48
+
+// ------------------------------------------------------------------------
+// Rx data format control register
+//
+//    3                   2                   1                       
+//  1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
+// +-----------------------------------------+-+-+---------+-------+
+// |          Reserved (Must be zero)        |B|Q|  WIDTH  | SHIFT |
+// +-----------------------------------------+-+-+---------+-------+
+//
+//  FMT values:
+
+`define FR_RX_FORMAT              7'd49
+
+
+// The valid combinations currently are:
+//
+//   B  Q  WIDTH  SHIFT
+//   0  1    16     0
+//   0  1     8     8
+
+
+// Possible future values of WIDTH = {4, 2, 1}
+// 12 takes a bit more work, since we need to know packet alignment.
+
+// ------------------------------------------------------------------------
+// FIXME register numbers 50 to 63 are available
+
+// ------------------------------------------------------------------------
+// Registers 64 to 95 are reserved for user custom FPGA builds.
+// The standard USRP software will not touch these.
+
+`define FR_USER_0                 7'd64
+`define FR_USER_1                 7'd65
+`define FR_USER_2                 7'd66
+`define FR_USER_3                 7'd67
+`define FR_USER_4                 7'd68
+`define FR_USER_5                 7'd69
+`define FR_USER_6                 7'd70
+`define FR_USER_7                 7'd71
+`define FR_USER_8                 7'd72
+`define FR_USER_9                 7'd73
+`define FR_USER_10                7'd74
+`define FR_USER_11                7'd75
+`define FR_USER_12                7'd76
+`define FR_USER_13                7'd77
+`define FR_USER_14                7'd78
+`define FR_USER_15                7'd79
+`define FR_USER_16                7'd80
+`define FR_USER_17                7'd81
+`define FR_USER_18                7'd82
+`define FR_USER_19                7'd83
+`define FR_USER_20                7'd84
+`define FR_USER_21                7'd85
+`define FR_USER_22                7'd86
+`define FR_USER_23                7'd87
+`define FR_USER_24                7'd88
+`define FR_USER_25                7'd89
+`define FR_USER_26                7'd90
+`define FR_USER_27                7'd91
+`define FR_USER_28                7'd92
+`define FR_USER_29                7'd93
+`define FR_USER_30                7'd94
+`define FR_USER_31                7'd95
+
+//Registers needed for multi usrp master/slave configuration
+//
+//Rx Master/slave control register (FR_RX_MASTER_SLAVE = FR_USER_0)
+//
+`define FR_RX_MASTER_SLAVE        7'd64
+`define bitnoFR_RX_SYNC           0
+`define bitnoFR_RX_SYNC_MASTER    1
+`define bitnoFR_RX_SYNC_SLAVE     2
+
+
+//Caution The master settings will output values on the io lines.
+//They inheritely enable these lines as output. If you have a daughtercard which uses these lines also as output then you will burn your usrp and daughtercard.
+//If you set the slave bits then your usrp won't do anything if you don't connect a master.
+// Rx Master/slave control register
+//
+// The way this is supposed to be used is connecting a (short) 16pin flatcable from an rx daughterboard in RXA master io_rx[8..15] to slave io_rx[8..15] on RXA of slave usrp
+// This can be done with basic_rx boards or dbsrx boards
+//dbsrx: connect master-J25 to slave-J25
+//basic rx: connect J25 to slave-J25
+//CAUTION: pay attention to the lineup of your connector.
+//The red line (pin1) should be at the same side of the daughterboards on master and slave.
+//If you turnaround the cable on one end you will burn your usrp.
+
+//You cannot use a 16pin flatcable if you are using FLEX400 or FLEX2400 daughterboards, since these use a lot of the io pins.
+//You can still link them but you must use only a 2pin or 1pin cable
+//You can also use a 2-wire link. put a 2pin header on io[15],gnd of the master RXA daughterboard and connect it to io15,gnd of the slave RXA db.
+//You can use a cable like the ones found with the leds on the mainbord of a PC.
+//Make sure you don't twist the cable, otherwise you connect the sync output to ground.
+//To be save you could also just use a single wire from master io[15] to slave io[15], but this is not optimal for signal integrity.
+
+
+// Since rx_io[0] can normally be used as a refclk and is not exported on all daughterboards this line
+// still has the refclk function if you use the master/slave setup (it is not touched by the master/slave settings).
+// The master/slave circuitry will only use io pin 15 and does not touch any of the other io pins.
+`define bitnoFR_RX_SYNC_INPUT_IOPIN 15
+`define bmFR_RX_SYNC_INPUT_IOPIN  (1<<bitnoFR_RX_SYNC_INPUT_IOPIN)
+//TODO the output pin is still hardcoded in the verilog code, make it listen to the following define
+`define bitnoFR_RX_SYNC_OUTPUT_IOPIN 15
+`define bmFR_RX_SYNC_OUTPUT_IOPIN (1<<bitnoFR_RX_SYNC_OUTPUT_IOPIN)
+// =======================================================================
+// READBACK Registers
+// =======================================================================
+
+`define FR_RB_IO_RX_A_IO_TX_A     7'd1	// read back a-side i/o pins
+`define FR_RB_IO_RX_B_IO_TX_B     7'd2	// read back b-side i/o pins
+
+// ------------------------------------------------------------------------
+// FPGA Capability register
+//
+//    3                   2                   1                       
+//  1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
+// +-----------------------------------------------+-+-----+-+-----+
+// |                    Reserved (Must be zero)    |T|NDUC |R|NDDC |
+// +-----------------------------------------------+-+-----+-+-----+
+//
+// Bottom 4-bits are Rx capabilities
+// Next   4-bits are Tx capabilities
+
+`define FR_RB_CAPS                7'd3
+
+
diff --git a/fpga/usrp1/inband_lib/rx_buffer_inband.v b/fpga/usrp1/inband_lib/rx_buffer_inband.v
index cbd2d8958..40c7ec7bd 100755
--- a/fpga/usrp1/inband_lib/rx_buffer_inband.v
+++ b/fpga/usrp1/inband_lib/rx_buffer_inband.v
@@ -1,5 +1,5 @@
-//`include "../../firmware/include/fpga_regs_common.v"

-//`include "../../firmware/include/fpga_regs_standard.v"

+//`include "../common/fpga_regs_common.v"

+//`include "../common/fpga_regs_standard.v"

 module rx_buffer_inband

   ( input usbclk,

     input bus_reset,

diff --git a/fpga/usrp1/sdr_lib/adc_interface.v b/fpga/usrp1/sdr_lib/adc_interface.v
index f18ffc104..cb78f332a 100644
--- a/fpga/usrp1/sdr_lib/adc_interface.v
+++ b/fpga/usrp1/sdr_lib/adc_interface.v
@@ -1,7 +1,7 @@
 
 
-`include "../../firmware/include/fpga_regs_common.v"
-`include "../../firmware/include/fpga_regs_standard.v"
+`include "../common/fpga_regs_common.v"
+`include "../common/fpga_regs_standard.v"
 
 module adc_interface
   (input clock, input reset, input enable,
diff --git a/fpga/usrp1/sdr_lib/io_pins.v b/fpga/usrp1/sdr_lib/io_pins.v
index ad1b7b4a8..b8bf59555 100644
--- a/fpga/usrp1/sdr_lib/io_pins.v
+++ b/fpga/usrp1/sdr_lib/io_pins.v
@@ -19,8 +19,8 @@
 //  Foundation, Inc., 51 Franklin Street, Boston, MA  02110-1301  USA
 //
 
-`include "../../firmware/include/fpga_regs_common.v"
-`include "../../firmware/include/fpga_regs_standard.v"
+`include "../common/fpga_regs_common.v"
+`include "../common/fpga_regs_standard.v"
 
 module io_pins
   ( inout wire [15:0] io_0, inout wire [15:0] io_1, inout wire [15:0] io_2, inout wire [15:0] io_3,
diff --git a/fpga/usrp1/sdr_lib/master_control_multi.v b/fpga/usrp1/sdr_lib/master_control_multi.v
index cab96a79f..eee8ebfa3 100644
--- a/fpga/usrp1/sdr_lib/master_control_multi.v
+++ b/fpga/usrp1/sdr_lib/master_control_multi.v
@@ -19,8 +19,8 @@
 //  Foundation, Inc., 51 Franklin Street, Boston, MA  02110-1301  USA
 //
 `include "config.vh"
-`include "../../../firmware/include/fpga_regs_common.v"
-`include "../../../firmware/include/fpga_regs_standard.v"
+`include "../../common/fpga_regs_common.v"
+`include "../../common/fpga_regs_standard.v"
 // Clock, enable, and reset controls for whole system
 // Modified version to enable multi_usrp synchronisation
 
diff --git a/fpga/usrp1/sdr_lib/rx_buffer.v b/fpga/usrp1/sdr_lib/rx_buffer.v
index d17294b98..5541d2912 100644
--- a/fpga/usrp1/sdr_lib/rx_buffer.v
+++ b/fpga/usrp1/sdr_lib/rx_buffer.v
@@ -22,8 +22,8 @@
 // Interface to Cypress FX2 bus
 // A packet is 512 Bytes, the fifo has 4096 lines of 18 bits each
 
-`include "../../firmware/include/fpga_regs_common.v"
-`include "../../firmware/include/fpga_regs_standard.v"
+`include "../common/fpga_regs_common.v"
+`include "../common/fpga_regs_standard.v"
 
 module rx_buffer
   ( // Read/USB side
diff --git a/fpga/usrp1/toplevel/mrfm/mrfm.v b/fpga/usrp1/toplevel/mrfm/mrfm.v
index 7a0e38059..6b7442ef3 100644
--- a/fpga/usrp1/toplevel/mrfm/mrfm.v
+++ b/fpga/usrp1/toplevel/mrfm/mrfm.v
@@ -24,8 +24,8 @@
 // Uncomment the following to include optional circuitry
 
 `include "mrfm.vh"
-`include "../../../firmware/include/fpga_regs_common.v"
-`include "../../../firmware/include/fpga_regs_standard.v"
+`include "../../common/fpga_regs_common.v"
+`include "../../common/fpga_regs_standard.v"
 
 module mrfm
 (output MYSTERY_SIGNAL,
diff --git a/fpga/usrp1/toplevel/mrfm/mrfm_proc.v b/fpga/usrp1/toplevel/mrfm/mrfm_proc.v
index 80de9fc90..7da934a6e 100644
--- a/fpga/usrp1/toplevel/mrfm/mrfm_proc.v
+++ b/fpga/usrp1/toplevel/mrfm/mrfm_proc.v
@@ -1,7 +1,7 @@
 
 `include "mrfm.vh"
-`include "../../../firmware/include/fpga_regs_common.v"
-`include "../../../firmware/include/fpga_regs_standard.v"
+`include "../../common/fpga_regs_common.v"
+`include "../../common/fpga_regs_standard.v"
 
 module mrfm_proc (input clock, input reset, input enable,
 		  input [6:0] serial_addr, input [31:0] serial_data, input serial_strobe,
diff --git a/fpga/usrp1/toplevel/usrp_inband_usb/usrp_inband_usb.v b/fpga/usrp1/toplevel/usrp_inband_usb/usrp_inband_usb.v
index 79f0dfa4a..49ed7444d 100644
--- a/fpga/usrp1/toplevel/usrp_inband_usb/usrp_inband_usb.v
+++ b/fpga/usrp1/toplevel/usrp_inband_usb/usrp_inband_usb.v
@@ -23,8 +23,8 @@
 `define RX_IN_BAND
 
 `include "config.vh"
-`include "../../../firmware/include/fpga_regs_common.v"
-`include "../../../firmware/include/fpga_regs_standard.v"
+`include "../../common/fpga_regs_common.v"
+`include "../../common/fpga_regs_standard.v"
 
 module usrp_inband_usb
 (output MYSTERY_SIGNAL,
diff --git a/fpga/usrp1/toplevel/usrp_multi/usrp_multi.v b/fpga/usrp1/toplevel/usrp_multi/usrp_multi.v
index ce484fc1c..08ae0c2aa 100644
--- a/fpga/usrp1/toplevel/usrp_multi/usrp_multi.v
+++ b/fpga/usrp1/toplevel/usrp_multi/usrp_multi.v
@@ -29,8 +29,8 @@
 // Uncomment the following to include optional circuitry
 
 `include "config.vh"
-`include "../../../firmware/include/fpga_regs_common.v"
-`include "../../../firmware/include/fpga_regs_standard.v"
+`include "../../common/fpga_regs_common.v"
+`include "../../common/fpga_regs_standard.v"
 
 module usrp_multi
 (output MYSTERY_SIGNAL,
diff --git a/fpga/usrp1/toplevel/usrp_std/usrp_std.v b/fpga/usrp1/toplevel/usrp_std/usrp_std.v
index 83a89cb81..b2eaceb25 100644
--- a/fpga/usrp1/toplevel/usrp_std/usrp_std.v
+++ b/fpga/usrp1/toplevel/usrp_std/usrp_std.v
@@ -28,8 +28,8 @@
 // Uncomment the following to include optional circuitry
 
 `include "config.vh"
-`include "../../../../firmware/fx2/common/fpga_regs_common.v"
-`include "../../../../firmware/fx2/common/fpga_regs_standard.v"
+`include "../../common/fpga_regs_common.v"
+`include "../../common/fpga_regs_standard.v"
 
 module usrp_std
 (output MYSTERY_SIGNAL,
diff --git a/fpga/usrp2/top/B100/B100.ucf b/fpga/usrp2/top/B100/B100.ucf
new file mode 100644
index 000000000..69fd49971
--- /dev/null
+++ b/fpga/usrp2/top/B100/B100.ucf
@@ -0,0 +1,200 @@
+## Main Clock
+NET "CLK_FPGA_P"  LOC = "R7"  ;
+NET "CLK_FPGA_N"  LOC = "T7"  ;
+
+## I2C
+NET "SDA_FPGA"  LOC = "T13"  ;
+NET "SCL_FPGA"  LOC = "R13"  ;
+
+## CGEN
+NET "cgen_st_ld"  LOC = "M13"  ;
+NET "cgen_st_refmon"  LOC = "J14"  ;
+NET "cgen_st_status"  LOC = "P6"  ;
+NET "cgen_ref_sel"  LOC = "T2"  ;
+NET "cgen_sync_b"  LOC = "H15"  ;
+
+## FPGA Config
+#NET "fpga_cfg_din"  LOC = "T14"  ;
+#NET "fpga_cfg_cclk"  LOC = "R14"  ;
+#NET "fpga_cfg_init_b"  LOC = "T12"  ;
+
+## MISC
+#NET "mystery_bus<1>"  LOC = "C4"  ;
+#NET "mystery_bus<0>"  LOC = "E7"  ;
+NET "reset_n"  LOC = "D5"  ;
+NET "PPS_IN"  LOC = "M14"  ;
+NET "reset_codec"  LOC = "B14"  ;
+
+## GPIF
+NET "GPIF_D<15>"  LOC = "P7"  ;
+NET "GPIF_D<14>"  LOC = "N8"  ;
+NET "GPIF_D<13>"  LOC = "T5"  ;
+NET "GPIF_D<12>"  LOC = "T6"  ;
+NET "GPIF_D<11>"  LOC = "N6"  ;
+NET "GPIF_D<10>"  LOC = "P5"  ;
+NET "GPIF_D<9>"  LOC = "R3"  ;
+NET "GPIF_D<8>"  LOC = "T3"  ;
+NET "GPIF_D<7>"  LOC = "N12"  ;
+NET "GPIF_D<6>"  LOC = "P13"  ;
+NET "GPIF_D<5>"  LOC = "P11"  ;
+NET "GPIF_D<4>"  LOC = "R9"  ;
+NET "GPIF_D<3>"  LOC = "T9"  ;
+NET "GPIF_D<2>"  LOC = "N9"  ;
+NET "GPIF_D<1>"  LOC = "P9"  ;
+NET "GPIF_D<0>"  LOC = "P8"  ;
+
+NET "GPIF_CTL<3>"  LOC = "N5"  ;
+NET "GPIF_CTL<2>"  LOC = "M11"  ;
+NET "GPIF_CTL<1>"  LOC = "M9"  ;
+NET "GPIF_CTL<0>"  LOC = "M7"  ;
+
+NET "GPIF_RDY<3>"  LOC = "N11"  ;
+NET "GPIF_RDY<2>"  LOC = "T10"  ;
+NET "GPIF_RDY<1>"  LOC = "T4"  ;
+NET "GPIF_RDY<0>"  LOC = "R5"  ;
+
+NET "GPIF_CS"  LOC = "P12"  ;
+NET "GPIF_SLOE"  LOC = "R11"  ;
+NET "GPIF_PKTEND"  LOC = "P10"  ;
+NET "GPIF_ADR<0>"  LOC = "T11"  ;
+NET "GPIF_ADR<1>"  LOC = "H16"  ;
+
+NET "IFCLK"  LOC = "T8"  ;
+
+## LEDs
+NET "debug_led<2>"  LOC = "R2"  ;
+NET "debug_led<1>"  LOC = "N4"  ;
+NET "debug_led<0>"  LOC = "P4"  ;
+
+## Debug bus
+NET "debug_clk<0>"  LOC = "K15"  ;
+NET "debug_clk<1>"  LOC = "K14"  ;
+NET "debug<0>"  LOC = "K16"  ;
+NET "debug<1>"  LOC = "J16"  ;
+NET "debug<2>"  LOC = "C16"  ;
+NET "debug<3>"  LOC = "C15"  ;
+NET "debug<4>"  LOC = "E13"  ;
+NET "debug<5>"  LOC = "D14"  ;
+NET "debug<6>"  LOC = "D16"  ;
+NET "debug<7>"  LOC = "D15"  ;
+NET "debug<8>"  LOC = "E14"  ;
+NET "debug<9>"  LOC = "F13"  ;
+NET "debug<10>"  LOC = "G13"  ;
+NET "debug<11>"  LOC = "F14"  ;
+NET "debug<12>"  LOC = "E16"  ;
+NET "debug<13>"  LOC = "F15"  ;
+NET "debug<14>"  LOC = "H13"  ;
+NET "debug<15>"  LOC = "G14"  ;
+NET "debug<16>"  LOC = "G16"  ;
+NET "debug<17>"  LOC = "F16"  ;
+NET "debug<18>"  LOC = "J12"  ;
+NET "debug<19>"  LOC = "J13"  ;
+NET "debug<20>"  LOC = "L14"  ;
+NET "debug<21>"  LOC = "L16"  ;
+NET "debug<22>"  LOC = "M15"  ;
+NET "debug<23>"  LOC = "M16"  ;
+NET "debug<24>"  LOC = "L13"  ;
+NET "debug<25>"  LOC = "K13"  ;
+NET "debug<26>"  LOC = "P16"  ;
+NET "debug<27>"  LOC = "N16"  ;
+NET "debug<28>"  LOC = "R15"  ;
+NET "debug<29>"  LOC = "P15"  ;
+NET "debug<30>"  LOC = "N13"  ;
+NET "debug<31>"  LOC = "N14"  ;
+
+## ADC
+NET "adc<11>"  LOC = "B15"  ;
+NET "adc<10>"  LOC = "A8"  ;
+NET "adc<9>"  LOC = "B8"  ;
+NET "adc<8>"  LOC = "C8"  ;
+NET "adc<7>"  LOC = "D8"  ;
+NET "adc<6>"  LOC = "C9"  ;
+NET "adc<5>"  LOC = "A9"  ;
+NET "adc<4>"  LOC = "C10"  ;
+NET "adc<3>"  LOC = "D9"  ;
+NET "adc<2>"  LOC = "A3"  ;
+NET "adc<1>"  LOC = "B3"  ;
+NET "adc<0>"  LOC = "A4"  ;
+NET "RXSYNC"  LOC = "D10"  ;
+
+## DAC
+NET "TXBLANK"  LOC = "K1"  ;
+NET "TXSYNC"  LOC = "J2"  ;
+NET "dac<0>"  LOC = "J1"  ;
+NET "dac<1>"  LOC = "H3"  ;
+NET "dac<2>"  LOC = "J3"  ;
+NET "dac<3>"  LOC = "G2"  ;
+NET "dac<4>"  LOC = "H1"  ;
+NET "dac<5>"  LOC = "N3"  ;
+NET "dac<6>"  LOC = "M4"  ;
+NET "dac<7>"  LOC = "R1"  ;
+NET "dac<8>"  LOC = "P2"  ;
+NET "dac<9>"  LOC = "P1"  ;
+NET "dac<10>"  LOC = "M1"  ;
+NET "dac<11>"  LOC = "N1"  ;
+NET "dac<12>"  LOC = "M3"  ;
+NET "dac<13>"  LOC = "L4"  ;
+
+## TX DB
+NET "io_tx<0>"  LOC = "K4"  ;
+NET "io_tx<1>"  LOC = "L3"  ;
+NET "io_tx<2>"  LOC = "L2"  ;
+NET "io_tx<3>"  LOC = "F1"  ;
+NET "io_tx<4>"  LOC = "F3"  ;
+NET "io_tx<5>"  LOC = "G3"  ;
+NET "io_tx<6>"  LOC = "E3"  ;
+NET "io_tx<7>"  LOC = "E2"  ;
+NET "io_tx<8>"  LOC = "E4"  ;
+NET "io_tx<9>"  LOC = "F4"  ;
+NET "io_tx<10>"  LOC = "D1"  ;
+NET "io_tx<11>"  LOC = "E1"  ;
+NET "io_tx<12>"  LOC = "D4"  ;
+NET "io_tx<13>"  LOC = "D3"  ;
+NET "io_tx<14>"  LOC = "C2"  ;
+NET "io_tx<15>"  LOC = "C1"  ;
+
+## RX DB
+NET "io_rx<0>"  LOC = "D7"  ;
+NET "io_rx<1>"  LOC = "C6"  ;
+NET "io_rx<2>"  LOC = "A6"  ;
+NET "io_rx<3>"  LOC = "B6"  ;
+NET "io_rx<4>"  LOC = "E9"  ;
+NET "io_rx<5>"  LOC = "A7"  ;
+NET "io_rx<6>"  LOC = "C7"  ;
+NET "io_rx<7>"  LOC = "B10"  ;
+NET "io_rx<8>"  LOC = "A10"  ;
+NET "io_rx<9>"  LOC = "C11"  ;
+NET "io_rx<10>"  LOC = "A11"  ;
+NET "io_rx<11>"  LOC = "D11"  ;
+NET "io_rx<12>"  LOC = "B12"  ;
+NET "io_rx<13>"  LOC = "A12"  ;
+NET "io_rx<14>"  LOC = "A14"  ;
+NET "io_rx<15>"  LOC = "A13"  ;
+
+## SPI
+#NET "SEN_AUX"  LOC = "C12"  ;
+#NET "SCLK_AUX"  LOC = "D12"  ;
+#NET "MISO_AUX"  LOC = "J5"  ;
+NET "SCLK_CODEC"  LOC = "K3"  ;
+NET "SEN_CODEC"  LOC = "D13"  ;
+NET "MOSI_CODEC"  LOC = "C13"  ;
+NET "MISO_CODEC"  LOC = "G4"  ;
+
+NET "MISO_RX_DB"  LOC = "E6"  ;
+NET "SEN_RX_DB"  LOC = "B4"  ;
+NET "MOSI_RX_DB"  LOC = "A5"  ;
+NET "SCLK_RX_DB"  LOC = "C5"  ;
+
+NET "MISO_TX_DB"  LOC = "J4"  ;
+NET "SEN_TX_DB"  LOC = "N2"  ;
+NET "MOSI_TX_DB"  LOC = "L1"  ;
+NET "SCLK_TX_DB"  LOC = "G1"  ;
+
+## Dedicated pins
+#NET "TMS"  LOC = "B2"  ;
+#NET "TDO"  LOC = "B16"  ;
+#NET "TDI"  LOC = "B1"  ;
+#NET "TCK"  LOC = "A15"  ;
+
+#NET "fpga_cfg_prog_b"  LOC = "A2"  ;
+#NET "fpga_cfg_done"  LOC = "T15"  ;
diff --git a/fpga/usrp2/top/B100/B100.v b/fpga/usrp2/top/B100/B100.v
new file mode 100644
index 000000000..f2d75c54e
--- /dev/null
+++ b/fpga/usrp2/top/B100/B100.v
@@ -0,0 +1,172 @@
+//
+// Copyright 2011 Ettus Research LLC
+//
+// This program is free software: you can redistribute it and/or modify
+// it under the terms of the GNU General Public License as published by
+// the Free Software Foundation, either version 3 of the License, or
+// (at your option) any later version.
+//
+// This program is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+// GNU General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with this program.  If not, see <http://www.gnu.org/licenses/>.
+//
+
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+
+module B100
+  (input CLK_FPGA_P, input CLK_FPGA_N,  // Diff
+   output [2:0] debug_led, output [31:0] debug, output [1:0] debug_clk,
+
+   // GPIF
+   inout [15:0] GPIF_D, input [3:0] GPIF_CTL, output [3:0] GPIF_RDY,
+   input [1:0] GPIF_ADR, output GPIF_CS, output GPIF_SLOE, output GPIF_PKTEND,
+   input IFCLK,
+   
+   inout SDA_FPGA, inout SCL_FPGA, // I2C
+
+   output SCLK_TX_DB, output SEN_TX_DB, output MOSI_TX_DB, input MISO_TX_DB,   // DB TX SPI
+   output SCLK_RX_DB, output SEN_RX_DB, output MOSI_RX_DB, input MISO_RX_DB,   // DB TX SPI
+   output SCLK_CODEC, output SEN_CODEC, output MOSI_CODEC, input MISO_CODEC,   // AD9862 main SPI
+
+   input cgen_st_status, input cgen_st_ld, input cgen_st_refmon, output cgen_sync_b, output cgen_ref_sel,
+   
+   inout [15:0] io_tx, inout [15:0] io_rx,
+
+   output [13:0] dac, output TXSYNC, output TXBLANK,
+   input [11:0] adc, input RXSYNC,
+  
+   input PPS_IN,
+   input reset_n, output reset_codec
+   );
+
+   assign reset_codec = 1;  // Believed to be active low
+   
+   // /////////////////////////////////////////////////////////////////////////
+   // Clocking
+   wire  clk_fpga, clk_fpga_in, reset;
+   
+   IBUFGDS #(.IOSTANDARD("LVDS_33"), .DIFF_TERM("TRUE")) 
+   clk_fpga_pin (.O(clk_fpga_in),.I(CLK_FPGA_P),.IB(CLK_FPGA_N));
+
+   BUFG clk_fpga_BUFG (.I(clk_fpga_in), .O(clk_fpga));
+   
+   reset_sync reset_sync(.clk(clk_fpga), .reset_in(~reset_n), .reset_out(reset));
+   
+   // /////////////////////////////////////////////////////////////////////////
+   // SPI
+   wire  mosi, sclk, miso;
+   assign { SCLK_TX_DB, MOSI_TX_DB } = ~SEN_TX_DB ? {sclk,mosi} : 2'b0;
+   assign { SCLK_RX_DB, MOSI_RX_DB } = ~SEN_RX_DB ? {sclk,mosi} : 2'b0;
+   assign { SCLK_CODEC, MOSI_CODEC } = ~SEN_CODEC ? {sclk,mosi} : 2'b0;
+   assign miso = (~SEN_TX_DB & MISO_TX_DB) | (~SEN_RX_DB & MISO_RX_DB) |
+		 (~SEN_CODEC & MISO_CODEC);
+
+   // /////////////////////////////////////////////////////////////////////////
+   // TX DAC -- handle the interleaved data bus to DAC, with clock doubling DLL
+
+   assign TXBLANK = 0;
+   wire [13:0] tx_i, tx_q;
+
+   genvar i;
+   generate
+      for(i=0;i<14;i=i+1)
+	begin : gen_dacout
+	   ODDR2 #(.DDR_ALIGNMENT("NONE"), // Sets output alignment to "NONE", "C0" or "C1" 
+		   .INIT(1'b0),            // Sets initial state of the Q output to 1'b0 or 1'b1
+		   .SRTYPE("SYNC"))        // Specifies "SYNC" or "ASYNC" set/reset
+	   ODDR2_inst (.Q(dac[i]),      // 1-bit DDR output data
+		       .C0(clk_fpga),  // 1-bit clock input
+		       .C1(~clk_fpga), // 1-bit clock input
+		       .CE(1'b1),      // 1-bit clock enable input
+		       .D0(tx_i[i]),   // 1-bit data input (associated with C0)
+		       .D1(tx_q[i]),   // 1-bit data input (associated with C1)
+		       .R(1'b0),       // 1-bit reset input
+		       .S(1'b0));      // 1-bit set input
+	end // block: gen_dacout
+      endgenerate
+   ODDR2 #(.DDR_ALIGNMENT("NONE"), // Sets output alignment to "NONE", "C0" or "C1" 
+	   .INIT(1'b0),            // Sets initial state of the Q output to 1'b0 or 1'b1
+	   .SRTYPE("SYNC"))        // Specifies "SYNC" or "ASYNC" set/reset
+   ODDR2_txsnc (.Q(TXSYNC),      // 1-bit DDR output data
+		.C0(clk_fpga),  // 1-bit clock input
+		.C1(~clk_fpga), // 1-bit clock input
+		.CE(1'b1),      // 1-bit clock enable input
+		.D0(1'b0),   // 1-bit data input (associated with C0)
+		.D1(1'b1),   // 1-bit data input (associated with C1)
+		.R(1'b0),       // 1-bit reset input
+		.S(1'b0));      // 1-bit set input
+
+   // /////////////////////////////////////////////////////////////////////////
+   // RX ADC -- handles deinterleaving
+
+   reg [11:0] rx_i, rx_q;
+   wire [11:0] rx_a, rx_b;
+   
+   genvar      j;
+   generate
+      for(j=0;j<12;j=j+1)
+	begin : gen_adcin
+	   IDDR2 #(.DDR_ALIGNMENT("NONE"), // Sets output alignment to "NONE", "C0" or "C1"
+		   .INIT_Q0(1'b0),         // Sets initial state of the Q0 output to 1’b0 or 1’b1
+		   .INIT_Q1(1'b0),         // Sets initial state of the Q1 output to 1’b0 or 1’b1
+		   .SRTYPE("SYNC"))        // Specifies "SYNC" or "ASYNC" set/reset
+	   IDDR2_inst (.Q0(rx_a[j]),      // 1-bit output captured with C0 clock
+		       .Q1(rx_b[j]),      // 1-bit output captured with C1 clock
+		       .C0(clk_fpga),     // 1-bit clock input
+		       .C1(~clk_fpga),    // 1-bit clock input
+		       .CE(1'b1),         // 1-bit clock enable input
+		       .D(adc[j]),        // 1-bit DDR data input
+		       .R(1'b0),          // 1-bit reset input
+		       .S(1'b0));         // 1-bit set input
+	end // block: gen_adcin
+   endgenerate
+   
+   IDDR2 #(.DDR_ALIGNMENT("NONE"), // Sets output alignment to "NONE", "C0" or "C1"
+	   .INIT_Q0(1'b0),         // Sets initial state of the Q0 output to 1’b0 or 1’b1
+	   .INIT_Q1(1'b0),         // Sets initial state of the Q1 output to 1’b0 or 1’b1
+	   .SRTYPE("SYNC"))        // Specifies "SYNC" or "ASYNC" set/reset
+   IDDR2_sync (.Q0(rxsync_0),      // 1-bit output captured with C0 clock
+	       .Q1(rxsync_1),      // 1-bit output captured with C1 clock
+	       .C0(clk_fpga),     // 1-bit clock input
+	       .C1(~clk_fpga),    // 1-bit clock input
+	       .CE(1'b1),         // 1-bit clock enable input
+	       .D(RXSYNC),        // 1-bit DDR data input
+	       .R(1'b0),          // 1-bit reset input
+	       .S(1'b0));         // 1-bit set input
+
+   always @(posedge clk_fpga)
+     if(rxsync_0)
+       begin
+	  rx_i <= rx_b;
+	  rx_q <= rx_a;
+       end
+     else
+       begin
+	  rx_i <= rx_a;
+	  rx_q <= rx_b;
+       end
+   
+   // /////////////////////////////////////////////////////////////////////////
+   // Main U1E Core
+   u1plus_core u1p_c(.clk_fpga(clk_fpga), .rst_fpga(reset),
+		     .debug_led(debug_led), .debug(debug), .debug_clk(debug_clk),
+		     .debug_txd(), .debug_rxd(1'b1),
+		     .gpif_d(GPIF_D), .gpif_ctl(GPIF_CTL), .gpif_rdy(GPIF_RDY),
+		     .gpif_misc({GPIF_CS,GPIF_SLOE,GPIF_PKTEND}),
+		     .gpif_clk(IFCLK),
+
+		     .db_sda(SDA_FPGA), .db_scl(SCL_FPGA),
+		     .sclk(sclk), .sen({SEN_CODEC,SEN_TX_DB,SEN_RX_DB}), .mosi(mosi), .miso(miso),
+		     .cgen_st_status(cgen_st_status), .cgen_st_ld(cgen_st_ld),.cgen_st_refmon(cgen_st_refmon), 
+		     .cgen_sync_b(cgen_sync_b), .cgen_ref_sel(cgen_ref_sel),
+		     .io_tx(io_tx), .io_rx(io_rx),
+		     .tx_i(tx_i), .tx_q(tx_q), 
+		     .rx_i(rx_i), .rx_q(rx_q),
+		     .pps_in(PPS_IN) );
+
+endmodule // B100
diff --git a/fpga/usrp2/top/B100/Makefile.B100 b/fpga/usrp2/top/B100/Makefile.B100
new file mode 100644
index 000000000..90dd25942
--- /dev/null
+++ b/fpga/usrp2/top/B100/Makefile.B100
@@ -0,0 +1,98 @@
+#
+# Copyright 2008 Ettus Research LLC
+#
+
+##################################################
+# Project Setup
+##################################################
+TOP_MODULE := B100
+BUILD_DIR := build-B100/
+export PROJ_FILE := $(BUILD_DIR)$(TOP_MODULE).ise
+
+include ../Makefile.common
+include ../../fifo/Makefile.srcs
+include ../../control_lib/Makefile.srcs
+include ../../sdr_lib/Makefile.srcs
+include ../../serdes/Makefile.srcs
+include ../../simple_gemac/Makefile.srcs
+include ../../timing/Makefile.srcs
+include ../../opencores/Makefile.srcs
+include ../../vrt/Makefile.srcs
+include ../../udp/Makefile.srcs
+include ../../coregen/Makefile.srcs
+include ../../gpif/Makefile.srcs
+
+##################################################
+# Project Properties
+##################################################
+export PROJECT_PROPERTIES := \
+family "Spartan3A" \
+device XC3S1400A \
+package ft256 \
+speed -4 \
+top_level_module_type "HDL" \
+synthesis_tool "XST (VHDL/Verilog)" \
+simulator "ISE Simulator (VHDL/Verilog)" \
+"Preferred Language" "Verilog" \
+"Enable Message Filtering" FALSE \
+"Display Incremental Messages" FALSE 
+
+##################################################
+# Sources
+##################################################
+TOP_SRCS = \
+B100.v \
+u1plus_core.v \
+B100.ucf \
+timing.ucf
+
+SOURCES = $(abspath $(TOP_SRCS)) $(FIFO_SRCS) \
+$(CONTROL_LIB_SRCS) $(SDR_LIB_SRCS) $(SERDES_SRCS) \
+$(SIMPLE_GEMAC_SRCS) $(TIMING_SRCS) $(OPENCORES_SRCS) \
+$(VRT_SRCS) $(UDP_SRCS) $(COREGEN_SRCS) $(EXTRAM_SRCS) \
+$(GPIF_SRCS)
+
+##################################################
+# Process Properties
+##################################################
+SYNTHESIZE_PROPERTIES = \
+"Number of Clock Buffers" 8 \
+"Pack I/O Registers into IOBs" Yes \
+"Optimization Effort" High \
+"Optimize Instantiated Primitives" TRUE \
+"Register Balancing" Yes \
+"Use Clock Enable" Auto \
+"Use Synchronous Reset" Auto \
+"Use Synchronous Set" Auto
+
+TRANSLATE_PROPERTIES = \
+"Macro Search Path" "$(shell pwd)/../../coregen/"
+
+MAP_PROPERTIES = \
+"Generate Detailed MAP Report" TRUE \
+"Allow Logic Optimization Across Hierarchy" TRUE \
+"Map to Input Functions" 4 \
+"Optimization Strategy (Cover Mode)" Speed \
+"Pack I/O Registers/Latches into IOBs" "For Inputs and Outputs" \
+"Perform Timing-Driven Packing and Placement" TRUE \
+"Map Effort Level" High \
+"Extra Effort" Normal \
+"Combinatorial Logic Optimization" TRUE \
+"Register Duplication" TRUE
+
+PLACE_ROUTE_PROPERTIES = \
+"Place & Route Effort Level (Overall)" High 
+
+STATIC_TIMING_PROPERTIES = \
+"Number of Paths in Error/Verbose Report" 10 \
+"Report Type" "Error Report"
+
+GEN_PROG_FILE_PROPERTIES = \
+"Configuration Rate" 6 \
+"Create Binary Configuration File" TRUE \
+"Done (Output Events)" 5 \
+"Enable Bitstream Compression" TRUE \
+"Enable Outputs (Output Events)" 6 \
+"Unused IOB Pins" "Pull Up"
+
+SIM_MODEL_PROPERTIES = ""
diff --git a/fpga/usrp2/top/B100/Makefile b/fpga/usrp2/top/B100/Makefile.u1plus
index 7ab56f9bd..e08a11126 100644
--- a/fpga/usrp2/top/B100/Makefile
+++ b/fpga/usrp2/top/B100/Makefile.u1plus
@@ -5,8 +5,8 @@
 ##################################################
 # Project Setup
 ##################################################
-BUILD_DIR := build/
-export TOP_MODULE := u1plus
+TOP_MODULE := u1plus
+BUILD_DIR := build-u1plus/
 export PROJ_FILE := $(BUILD_DIR)$(TOP_MODULE).ise
 
 include ../Makefile.common
diff --git a/fpga/usrp2/top/B100/u1plus.ucf b/fpga/usrp2/top/B100/u1plus.ucf
index cd89878e3..3ecc4daf2 100644
--- a/fpga/usrp2/top/B100/u1plus.ucf
+++ b/fpga/usrp2/top/B100/u1plus.ucf
@@ -199,5 +199,5 @@ NET "SCLK_TX_DB"  LOC = "G1"  ;
 #NET "TDI"  LOC = "B1"  ;
 #NET "TCK"  LOC = "A15"  ;
 
-##NET "fpga_cfg_prog_b"  LOC = "A2"  ;
-##NET "fpga_cfg_done"  LOC = "T15"  ;
+#NET "fpga_cfg_prog_b"  LOC = "A2"  ;
+#NET "fpga_cfg_done"  LOC = "T15"  ;
diff --git a/fpga/usrp2/top/B100/u1plus_core.v b/fpga/usrp2/top/B100/u1plus_core.v
index b40083201..61c1df04c 100644
--- a/fpga/usrp2/top/B100/u1plus_core.v
+++ b/fpga/usrp2/top/B100/u1plus_core.v
@@ -205,7 +205,7 @@ module u1plus_core
       .data0_i(vita_rx_data0), .src0_rdy_i(vita_rx_src_rdy0), .dst0_rdy_o(vita_rx_dst_rdy0),
       .data1_i(vita_rx_data1), .src1_rdy_i(vita_rx_src_rdy1), .dst1_rdy_o(vita_rx_dst_rdy1),
       .data_o(rx_data), .src_rdy_o(rx_src_rdy), .dst_rdy_i(rx_dst_rdy));
-   
+
    // ///////////////////////////////////////////////////////////////////////////////////
    // DSP TX
 
@@ -297,7 +297,8 @@ module u1plus_core
       .sf_dat_o(sf_dat_mosi),.sf_adr_o(sf_adr),.sf_sel_o(sf_sel),.sf_we_o(sf_we),.sf_cyc_o(sf_cyc),.sf_stb_o(sf_stb),
       .sf_dat_i(sf_dat_miso),.sf_ack_i(sf_ack),.sf_err_i(0),.sf_rty_i(0) );
 
-   assign s5_ack = 0;   assign s9_ack = 0;   assign sa_ack = 0;   assign sb_ack = 0;
+   assign s5_ack = 0;   
+   assign s9_ack = 0;   assign sa_ack = 0;   assign sb_ack = 0;
    assign sc_ack = 0;   assign sd_ack = 0;   assign se_ack = 0;   assign sf_ack = 0;
 
    // /////////////////////////////////////////////////////////////////////////////////////
@@ -410,10 +411,10 @@ module u1plus_core
 
    // only have 64 regs, 32 bits each with current setup...
    settings_bus_16LE #(.AWIDTH(11),.RWIDTH(6)) settings_bus_16LE
-     (.wb_clk(wb_clk),.wb_rst(wb_rst),.wb_adr_i(s8_adr[10:0]),.wb_dat_i(s8_dat_mosi),
+     (.wb_clk(wb_clk),.wb_rst(wb_rst),.wb_adr_i(s8_adr),.wb_dat_i(s8_dat_mosi),
       .wb_stb_i(s8_stb),.wb_we_i(s8_we),.wb_ack_o(s8_ack),
       .strobe(set_stb),.addr(set_addr),.data(set_data) );
-   
+
    // /////////////////////////////////////////////////////////////////////////
    // ATR Controller -- Slave #6
 
@@ -457,7 +458,7 @@ module u1plus_core
    // /////////////////////////////////////////////////////////////////////////////////////
    // Debug circuitry
 
-   assign debug_clk = { gpif_clk, clk_fpga };
+   assign debug_clk = 2'b00; // { gpif_clk, clk_fpga };
    assign debug = 0;
    assign debug_gpio_0 = 0;
    assign debug_gpio_1 = 0;
diff --git a/fpga/usrp2/top/E1x0/u1e.ucf b/fpga/usrp2/top/E1x0/u1e.ucf
index 0c487a601..278fc289a 100644
--- a/fpga/usrp2/top/E1x0/u1e.ucf
+++ b/fpga/usrp2/top/E1x0/u1e.ucf
@@ -67,8 +67,10 @@ NET "overo_gpio170"  LOC = "E8"  ;  # MISC GPIO for debug
 NET "overo_gpio176"  LOC = "B4"  ;  # MISC GPIO for debug
 
 ## Overo UART
-#NET "overo_txd1"  LOC = "C6"  ;
-#NET "overo_rxd1"  LOC = "D6"  ;
+NET "overo_txd1"  LOC = "C6"  ;
+NET "overo_rxd1"  LOC = "D6"  ;
+NET "fpga_txd1"   LOC = "AB9" ;
+NET "fpga_rxd1"   LOC = "AB8" ;
 
 ## FTDI UART to USB converter
 NET "FPGA_TXD"  LOC = "G19"  ;
diff --git a/fpga/usrp2/top/E1x0/u1e.v b/fpga/usrp2/top/E1x0/u1e.v
index ff2e08394..903ef7a6f 100644
--- a/fpga/usrp2/top/E1x0/u1e.v
+++ b/fpga/usrp2/top/E1x0/u1e.v
@@ -22,6 +22,7 @@ module u1e
   (input CLK_FPGA_P, input CLK_FPGA_N,  // Diff
    output [3:0] debug_led, output [31:0] debug, output [1:0] debug_clk,
    input debug_pb, output FPGA_TXD, input FPGA_RXD,
+   output fpga_txd1, input fpga_rxd1, input overo_txd1, output overo_rxd1,
 
    // GPMC
    input EM_CLK, inout [15:0] EM_D, input [10:1] EM_A, input [1:0] EM_NBE,
@@ -59,6 +60,10 @@ module u1e
    clk_fpga_pin (.O(clk_fpga),.I(CLK_FPGA_P),.IB(CLK_FPGA_N));
 
    // /////////////////////////////////////////////////////////////////////////
+   // UART level conversion
+   assign fpga_txd1 = overo_txd1;
+   assign overo_rxd1 = fpga_rxd1;
+   
    // SPI
    wire  mosi, sclk, miso;
    assign { db_sclk_tx, db_mosi_tx } = ~db_sen_tx ? {sclk,mosi} : 2'b0;
diff --git a/fpga/usrp2/top/E1x0/u1e_core.v b/fpga/usrp2/top/E1x0/u1e_core.v
index 20dd98a36..e1bb50890 100644
--- a/fpga/usrp2/top/E1x0/u1e_core.v
+++ b/fpga/usrp2/top/E1x0/u1e_core.v
@@ -489,26 +489,9 @@ module u1e_core
    // /////////////////////////////////////////////////////////////////////////////////////
    // Debug circuitry
 
-   assign debug_clk = { EM_CLK, clk_fpga };
-
-/*
-   assign debug = { { rx_have_data, tx_have_space, EM_NCS6, EM_NCS5, EM_NCS4, EM_NWE, EM_NOE, rx_overrun },
-		    { tx_src_rdy, tx_src_rdy_int, tx_dst_rdy, tx_dst_rdy_int, rx_src_rdy, rx_src_rdy_int, rx_dst_rdy, rx_dst_rdy_int },
-		    { EM_D } };
-
-*/
-   assign debug = debug_gpmc;
-
-   assign debug_gpio_0 = { {run_tx, 2'b0, strobe_rx0, tx_i[11:0]}, 
-			   {2'b00, tx_src_rdy, tx_dst_rdy, tx_q[11:0]} };
-
-   assign debug_gpio_1 = debug_vt;
+   assign debug_clk = 2'b00; //{ EM_CLK, clk_fpga };
+   assign debug = 0;
+   assign debug_gpio_0 = 0;
+   assign debug_gpio_1 = 0;
    
-/*   
-   assign debug_gpio_1 = { {rx_enable, rx_src_rdy, rx_dst_rdy, rx_src_rdy & ~rx_dst_rdy},
-			   {tx_enable, tx_src_rdy, tx_dst_rdy, tx_dst_rdy & ~tx_src_rdy},
-			   {2'b0, rx_src_rdy, rx_dst_rdy, rx_data[33:32],2'b0},
-			   {2'b0, bus_error, debug_gpmc[4:0] },
-			   {misc_gpio[7:0]} };
-  */ 
 endmodule // u1e_core