diff options
| author | Wade Fife <wade.fife@ettus.com> | 2022-03-03 13:08:22 -0600 |
|---|---|---|
| committer | Wade Fife <wade.fife@ettus.com> | 2022-03-04 18:46:12 -0600 |
| commit | bbda5411548a06a3c3ada7b02df8fa7fb44aaad5 (patch) | |
| tree | 12ca91de18c77aa9e4a9afc10efe016f8dfb34d0 /fpga/usrp3 | |
| parent | 822cd03c8cd686f8b0554774adcbdd3803128bc2 (diff) | |
| download | uhd-bbda5411548a06a3c3ada7b02df8fa7fb44aaad5.tar.gz uhd-bbda5411548a06a3c3ada7b02df8fa7fb44aaad5.tar.bz2 uhd-bbda5411548a06a3c3ada7b02df8fa7fb44aaad5.zip | |
fpga: x400: Add support for DRAM with 400 MHz BW
Diffstat (limited to 'fpga/usrp3')
| -rw-r--r-- | fpga/usrp3/top/x400/Makefile | 30 | ||||
| -rw-r--r-- | fpga/usrp3/top/x400/x4xx_core.v | 16 |
2 files changed, 24 insertions, 22 deletions
diff --git a/fpga/usrp3/top/x400/Makefile b/fpga/usrp3/top/x400/Makefile index ad519be73..5098e58b1 100644 --- a/fpga/usrp3/top/x400/Makefile +++ b/fpga/usrp3/top/x400/Makefile @@ -43,22 +43,24 @@ QSFP1_100GBE = QSFP1_0=$(MGT_100GbE) QSFP1_1=$(MGT_Disabled) QSFP1_2=$(MGT_Disa # Target specific variables X410_IP: DEFS += $(QSFP0_10GBE) RFBW_100M=1 -X410_X1_100: DEFS += $(QSFP0_10GBE) RFBW_100M=1 -X410_XG_100: DEFS += $(QSFP0_10GBE) $(QSFP1_10GBE) RFBW_100M=1 -X410_X4_100: DEFS += $(QSFP0_4X10GBE) RFBW_100M=1 -X410_X4C_100: DEFS += $(QSFP0_4X10GBE) $(QSFP1_100GBE) RFBW_100M=1 -X410_CG_100: DEFS += $(QSFP0_100GBE) RFBW_100M=1 -X410_CG_200: DEFS += $(QSFP0_100GBE) RFBW_200M=1 -X410_XG_200: DEFS += $(QSFP0_10GBE) $(QSFP1_10GBE) RFBW_200M=1 -X410_X4_200: DEFS += $(QSFP0_4X10GBE) RFBW_200M=1 -X410_X4C_200: DEFS += $(QSFP0_4X10GBE) $(QSFP1_100GBE) RFBW_200M=1 -X410_C1_400: DEFS += $(QSFP0_100GBE) RFBW_400M=1 -X410_CG_400: DEFS += $(QSFP0_100GBE) $(QSFP1_100GBE) RFBW_400M=1 - -# DRAM IP inclusion. Set to 1 to include DRAM IP in design, 0 to exclude it. +X410_X1_100: DEFS += $(QSFP0_10GBE) RFBW_100M=1 DRAM_CH=4*$(DRAM) DRAM_W=64 +X410_XG_100: DEFS += $(QSFP0_10GBE) $(QSFP1_10GBE) RFBW_100M=1 DRAM_CH=4*$(DRAM) DRAM_W=64 +X410_X4_100: DEFS += $(QSFP0_4X10GBE) RFBW_100M=1 DRAM_CH=4*$(DRAM) DRAM_W=64 +X410_X4C_100: DEFS += $(QSFP0_4X10GBE) $(QSFP1_100GBE) RFBW_100M=1 DRAM_CH=0 +X410_CG_100: DEFS += $(QSFP0_100GBE) RFBW_100M=1 DRAM_CH=4*$(DRAM) DRAM_W=64 +X410_CG_200: DEFS += $(QSFP0_100GBE) RFBW_200M=1 DRAM_CH=4*$(DRAM) DRAM_W=64 +X410_X1_200: DEFS += $(QSFP0_10GBE) RFBW_200M=1 DRAM_CH=4*$(DRAM) DRAM_W=64 +X410_XG_200: DEFS += $(QSFP0_10GBE) $(QSFP1_10GBE) RFBW_200M=1 DRAM_CH=4*$(DRAM) DRAM_W=64 +X410_X4_200: DEFS += $(QSFP0_4X10GBE) RFBW_200M=1 DRAM_CH=4*$(DRAM) DRAM_W=64 +X410_X4C_200: DEFS += $(QSFP0_4X10GBE) $(QSFP1_100GBE) RFBW_200M=1 DRAM_CH=0 +X410_C1_400: DEFS += $(QSFP0_100GBE) RFBW_400M=1 DRAM_CH=0 +X410_CG_400: DEFS += $(QSFP0_100GBE) $(QSFP1_100GBE) RFBW_400M=1 DRAM_CH=0 + +# DRAM IP inclusion. Set to 1 to include DRAM memory controller in design, 0 to +# exclude it. Note that some targets exclude it regardless of this setting. DRAM ?= 1 -DEFS += $(OPTIONS) ENABLE_DRAM=$(DRAM) +DEFS += $(OPTIONS) # Defaults specific to the various targets: X410_100_DEFAULTS:=DEFAULT_RFNOC_IMAGE_CORE_FILE=x410_100_rfnoc_image_core.v DEFAULT_EDGE_FILE=$(abspath x410_100_static_router.hex) diff --git a/fpga/usrp3/top/x400/x4xx_core.v b/fpga/usrp3/top/x400/x4xx_core.v index df60b8a90..eac0b8f0a 100644 --- a/fpga/usrp3/top/x400/x4xx_core.v +++ b/fpga/usrp3/top/x400/x4xx_core.v @@ -394,16 +394,16 @@ module x4xx_core #( // DRAM //--------------------------------------------------------------------------- - `ifndef ENABLE_DRAM - `define ENABLE_DRAM 0 + `ifndef DRAM_CH + `define DRAM_CH 0 + `endif + `ifndef DRAM_W + `define DRAM_W 64 `endif - // Only the 100 and 200 MHz images currently support DRAM due to FPGA - // resource limitations. For 200 MHz and below, a 64-bit interface provides - // sufficient bandwidth. - localparam ENABLE_DRAM = (`ENABLE_DRAM) && (RF_BANDWIDTH <= 200); - localparam DRAM_NUM_PORTS = 4; - localparam DRAM_AXI_DWIDTH = (RF_BANDWIDTH <= 200) ? 64 : 128; + localparam DRAM_AXI_DWIDTH = `DRAM_W; + localparam ENABLE_DRAM = (`DRAM_CH > 0); + localparam DRAM_NUM_PORTS = `DRAM_CH; wire dram0_ui_clk; wire dram0_ui_clk_sync_rst; |