fpga: lib: add generic to disable bitq engine tri-stating

2 files changed, 16 insertions, 11 deletions

diff --git a/fpga/usrp3/lib/vivado_ipi/axi_bitq/axi_bitq.vhd b/fpga/usrp3/lib/vivado_ipi/axi_bitq/axi_bitq.vhd
index 322f706a4..6247941bd 100644
--- a/fpga/usrp3/lib/vivado_ipi/axi_bitq/axi_bitq.vhd
+++ b/fpga/usrp3/lib/vivado_ipi/axi_bitq/axi_bitq.vhd
@@ -90,7 +90,7 @@ begin
       S_AXI_RDATA <= (others => '0');
 
       case read_addr is
-      when "00" => 
+      when "00" =>
         S_AXI_RDATA(31 downto 0) <= wr_data;
       when "01" =>
         S_AXI_RDATA(31 downto 0) <= stb_data;
@@ -151,7 +151,7 @@ begin
       start <= '0';
     elsif (write_addr_token = '1') and (write_data_token = '1') then
       case write_addr(write_addr'left downto 2) is
-      when "00" => 
+      when "00" =>
         if (write_strb(0) = '1') and (ready = '1') then
           wr_data(7 downto 0) <= write_data(7 downto 0);
         end if;
@@ -164,7 +164,7 @@ begin
         if (write_strb(3) = '1') and (ready = '1') then
           wr_data(31 downto 24) <= write_data(31 downto 24);
         end if;
-      when "01" => 
+      when "01" =>
         if (write_strb(0) = '1') and (ready = '1') then
           stb_data(7 downto 0) <= write_data(7 downto 0);
         end if;
@@ -202,11 +202,14 @@ begin
   bitq_rstn <= '0' when (S_AXI_ARESETN = '0') or (bitq_soft_rst = '1') else '1';
 
   bitq_ctrl : entity bitq_fsm
+  generic map (
+    IDLE_VALUE => 'Z'
+  )
   port map (
     clk  => S_AXI_ACLK,
     rstn => S_AXI_ARESETN,
     prescalar => prescalar,
-  
+
     bit_clk  => bit_clk,
     bit_in   => bit_in,
     bit_out  => bit_out,
diff --git a/fpga/usrp3/lib/vivado_ipi/axi_bitq/bitq_fsm.vhd b/fpga/usrp3/lib/vivado_ipi/axi_bitq/bitq_fsm.vhd
index ed7ab4a50..a952c4b35 100644
--- a/fpga/usrp3/lib/vivado_ipi/axi_bitq/bitq_fsm.vhd
+++ b/fpga/usrp3/lib/vivado_ipi/axi_bitq/bitq_fsm.vhd
@@ -12,6 +12,9 @@ use ieee.std_logic_1164.all;
 use ieee.numeric_std.all;
 
 entity bitq_fsm is
+generic (
+  IDLE_VALUE : std_logic := 'Z'
+);
 port (
   clk  : in std_logic;
   rstn : in std_logic;
@@ -27,7 +30,6 @@ port (
   wr_data  : in std_logic_vector(31 downto 0);
   stb_data : in std_logic_vector(31 downto 0);
   rd_data  : out std_logic_vector(31 downto 0)
-
 );
 
 end bitq_fsm;
@@ -51,9 +53,9 @@ begin
   begin
     case (bitq_state) is
     when IDLE =>
-      bit_clk <= 'Z';
-      bit_out <= 'Z';
-      bit_stb <= 'Z';
+      bit_clk <= IDLE_VALUE;
+      bit_out <= IDLE_VALUE;
+      bit_stb <= IDLE_VALUE;
       ready   <= '1';
     when LOW =>
       bit_clk <= '0';
@@ -66,9 +68,9 @@ begin
       bit_stb <= bit_stb_r;
       ready <= '0';
     when others =>
-      bit_clk <= 'Z';
-      bit_out <= 'Z';
-      bit_stb <= 'Z';
+      bit_clk <= IDLE_VALUE;
+      bit_out <= IDLE_VALUE;
+      bit_stb <= IDLE_VALUE;
       ready   <= '1';
     end case;
   end process;