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authorWade Fife <wade.fife@ettus.com>2022-01-11 15:19:14 -0600
committerAaron Rossetto <aaron.rossetto@ni.com>2022-01-13 14:33:59 -0600
commit6bb7d61251abd303049dfd0f47bd0266656797fb (patch)
tree4222dec914d2d9eb5b47bd448533255b12fd7214 /fpga/usrp3
parent51384afc2c5d4db9e2e45d97382edce8c8039b10 (diff)
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fpga: tools: Fix adding directories for HDL source
Diffstat (limited to 'fpga/usrp3')
-rw-r--r--fpga/usrp3/tools/scripts/viv_utils.tcl2
1 files changed, 1 insertions, 1 deletions
diff --git a/fpga/usrp3/tools/scripts/viv_utils.tcl b/fpga/usrp3/tools/scripts/viv_utils.tcl
index 9ced39edf..e6683c151 100644
--- a/fpga/usrp3/tools/scripts/viv_utils.tcl
+++ b/fpga/usrp3/tools/scripts/viv_utils.tcl
@@ -64,7 +64,7 @@ proc ::vivado_utils::initialize_project { {save_to_disk 0} } {
if [expr [file isdirectory $src_file] == 1] {
puts "BUILDER: Expanding Directory : $src_file"
set dir_contents [glob $src_file/*.*]
- append design_srcs " " $dir_contents
+ append g_source_files " " $dir_contents
}
}