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| author | Wade Fife <wade.fife@ettus.com> | 2022-02-07 14:18:06 -0600 |
|---|---|---|
| committer | Wade Fife <wade.fife@ettus.com> | 2022-02-10 19:46:39 -0700 |
| commit | 6936a9ac664cbc312fd17a5ebab9b40069615f7a (patch) | |
| tree | c1375221ca842698627a93056bb038f00b0f14a6 /fpga/usrp3 | |
| parent | 4ea32ae32de0cc3e5b04b5203806bc6604f3d493 (diff) | |
| download | uhd-6936a9ac664cbc312fd17a5ebab9b40069615f7a.tar.gz uhd-6936a9ac664cbc312fd17a5ebab9b40069615f7a.tar.bz2 uhd-6936a9ac664cbc312fd17a5ebab9b40069615f7a.zip | |
fpga: rfnoc: Change AWIDTH default for axi_ram_fifo
Change AWIDTH to be the same as MEM_ADDR_W by default. Current USRPs
assume the AXI address width is the same as MEM_ADDR_W.
Diffstat (limited to 'fpga/usrp3')
| -rw-r--r-- | fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_axi_ram_fifo/rfnoc_block_axi_ram_fifo.v | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_axi_ram_fifo/rfnoc_block_axi_ram_fifo.v b/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_axi_ram_fifo/rfnoc_block_axi_ram_fifo.v index 68dbbd4ec..2a169366d 100644 --- a/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_axi_ram_fifo/rfnoc_block_axi_ram_fifo.v +++ b/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_axi_ram_fifo/rfnoc_block_axi_ram_fifo.v @@ -66,7 +66,7 @@ module rfnoc_block_axi_ram_fifo #( parameter MTU = 10, parameter MEM_DATA_W = CHDR_W, parameter MEM_ADDR_W = 32, - parameter AWIDTH = 32, + parameter AWIDTH = MEM_ADDR_W, parameter [NUM_PORTS*MEM_ADDR_W-1:0] FIFO_ADDR_BASE = {NUM_PORTS{ {MEM_ADDR_W{1'b0}} }}, parameter [NUM_PORTS*MEM_ADDR_W-1:0] FIFO_ADDR_MASK = {NUM_PORTS{ {(MEM_ADDR_W-$clog2(NUM_PORTS)){1'b1}} }}, parameter [ NUM_PORTS*32-1:0] BURST_TIMEOUT = {NUM_PORTS{ 32'd256 }}, |