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| author | Wade Fife <wade.fife@ettus.com> | 2020-06-04 18:21:24 -0500 |
|---|---|---|
| committer | Wade Fife <wade.fife@ettus.com> | 2020-06-11 09:53:00 -0500 |
| commit | 5cda86b7e09be7865807700a58e41ec021bf3c74 (patch) | |
| tree | 53ded86fa38dc91a4af717dc63b58c8c01325ef2 /fpga/usrp3 | |
| parent | 5476ec584efaa47bf986b360332973f3cf70b3ee (diff) | |
| download | uhd-5cda86b7e09be7865807700a58e41ec021bf3c74.tar.gz uhd-5cda86b7e09be7865807700a58e41ec021bf3c74.tar.bz2 uhd-5cda86b7e09be7865807700a58e41ec021bf3c74.zip | |
fpga: tools: Allow multiple top modules with ModelSim
Diffstat (limited to 'fpga/usrp3')
| -rw-r--r-- | fpga/usrp3/tools/make/viv_simulator.mak | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/fpga/usrp3/tools/make/viv_simulator.mak b/fpga/usrp3/tools/make/viv_simulator.mak index 5ced4ee32..66af10fec 100644 --- a/fpga/usrp3/tools/make/viv_simulator.mak +++ b/fpga/usrp3/tools/make/viv_simulator.mak @@ -78,7 +78,7 @@ SETUP_AND_LAUNCH_VLINT = \ SETUP_AND_LAUNCH_MODELSIM = \ @ \ export MSIM_PROJ_DIR=$(MODELSIM_PROJ_DIR); \ - export MSIM_SIM_TOP=$(SIM_TOP); \ + export MSIM_SIM_TOP="$(SIM_TOP)"; \ export MSIM_ARGS="$(MODELSIM_ARGS)"; \ export MSIM_LIBS="$(MODELSIM_LIBS)"; \ export MSIM_MODE=$(VIVADO_MODE); \ |