Removed copy of FPGA source files.

1 files changed, 0 insertions, 41 deletions

diff --git a/fpga/usrp3/vita_chdr.txt b/fpga/usrp3/vita_chdr.txt
deleted file mode 100644
index a194a88c6..000000000
--- a/fpga/usrp3/vita_chdr.txt
+++ /dev/null
@@ -1,41 +0,0 @@
-
-
-VRLP and VITA Fields
-====================
-
-All VRT (VITA 49.0) packets will be carried in a VRL (VITA 49.1) frame when outside the FPGA core.
-Every VRL frame will hold exactly one VRT packet.
-VRT packets must have stream ID
-VRT packets must NOT have integer seconds timestamps
-VRT packets must NOT have class ID
-VRT packets may have fractional seconds timestamps
-VRT packets may have trailer
-Only VITA IF Data and VITA Extension Context packets are allowed
-
-VITA Compressed Headers
-=======================
-
-Structure of a normal VRL-encapsulated VRT packet, in 64-bit wide format:
-
-VRLP { VRLP_text[31:0], frame_count[11:0], frame_size[19:0] }
-VRT0 { VRT_Header[31:0], Stream ID[31:0] }
-VRT1 { Fractional timestamp[63:0] } OPTIONAL
-...  Packet contents ...
-Optional Trailer
-"VEND"
-
-Since packet contents can have variable length, 64-bit alignment of trailer and VEND will vary
-
-Inside the FPGA switching fabric, the first line of "compressed vita packets" will be called the "CHDR".
-The "CHDR" compresses the contents of the VRLP header and VRT header and streamID, and has the following format:
-
-BIT      Meaning
-63       is_extension_context  (0 for data, 1 for control packets)
-62       reserved
-61       has_time (0 for no, 1 for time field on next line)
-60       EOB (end of burst indicator)
-59:48    12-bit sequence number (from VRLP frame count, bottom 4 bits should match VRT seq number)
-47:32    16-bit length in bytes (from VRT length in words32)
-31:0     stream ID
-
-Inside the fabric, the "VEND" from VRLP is dropped.