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| author | Martin Braun <martin.braun@ettus.com> | 2021-12-22 16:59:59 +0100 |
|---|---|---|
| committer | Wade Fife <wade.fife@ettus.com> | 2022-01-10 08:46:56 -0600 |
| commit | c891f2d8738bc1b73bb92d88623f4760f9e2bd1e (patch) | |
| tree | 8814370244604991590d694c89cdf9096498d67a /fpga/usrp3/top | |
| parent | a9e313676dfbd5703b4763a7c9dc03e62746335b (diff) | |
| download | uhd-c891f2d8738bc1b73bb92d88623f4760f9e2bd1e.tar.gz uhd-c891f2d8738bc1b73bb92d88623f4760f9e2bd1e.tar.bz2 uhd-c891f2d8738bc1b73bb92d88623f4760f9e2bd1e.zip | |
fpga: e320: Connect CTRL_IN pins to FPGA
These pins control hardware-controlled fast-lock for tuning or
cycle-accurate gain control. This commit does nothing to these pins
other than expose them into the design and assign them to zero. This
does not change the current behaviour (the motherboard has pull-downs on
these pins, so they're low by default).
Diffstat (limited to 'fpga/usrp3/top')
| -rw-r--r-- | fpga/usrp3/top/e320/e320.v | 6 | ||||
| -rw-r--r-- | fpga/usrp3/top/e320/mb_pins.xdc | 7 |
2 files changed, 12 insertions, 1 deletions
diff --git a/fpga/usrp3/top/e320/e320.v b/fpga/usrp3/top/e320/e320.v index 873677c06..501f6a06d 100644 --- a/fpga/usrp3/top/e320/e320.v +++ b/fpga/usrp3/top/e320/e320.v @@ -156,7 +156,8 @@ module e320 ( output wire XCVR_TXNRX, output wire XCVR_ENA_AGC, output wire XCVR_RESET_N, - input wire [7:0] XCVR_CTRL_OUT, + input wire [7:0] XCVR_CTRL_OUT, + output wire [3:0] XCVR_CTRL_IN, // Amplifiers output wire TX_HFAMP1_ENA, @@ -1844,5 +1845,8 @@ module e320 ( .device_id(device_id) ); + // Control pins to AD9361 will lay low for now + assign XCVR_CTRL_IN = 4'h0; + endmodule // e320 `default_nettype wire diff --git a/fpga/usrp3/top/e320/mb_pins.xdc b/fpga/usrp3/top/e320/mb_pins.xdc index 9fa7a5cd0..96160f22f 100644 --- a/fpga/usrp3/top/e320/mb_pins.xdc +++ b/fpga/usrp3/top/e320/mb_pins.xdc @@ -154,6 +154,13 @@ set_property IOSTANDARD LVCMOS18 [get_ports {XCVR_CTRL_OUT[*]}] set_property PULLUP TRUE [get_ports {XCVR_CTRL_OUT[6]}] set_property PULLUP TRUE [get_ports {XCVR_CTRL_OUT[7]}] +# CTRL_IN, Bank 13, 1.8 V +set_property PACKAGE_PIN U24 [get_ports {XCVR_CTRL_IN[0]}] +set_property PACKAGE_PIN V24 [get_ports {XCVR_CTRL_IN[1]}] +set_property PACKAGE_PIN V23 [get_ports {XCVR_CTRL_IN[2]}] +set_property PACKAGE_PIN W24 [get_ports {XCVR_CTRL_IN[3]}] +set_property IOSTANDARD LVCMOS18 [get_ports {XCVR_CTRL_IN[*]}] + ## RX/TX LEDs, Bank 10, 3.3 V set_property PACKAGE_PIN AG14 [get_ports {RX1_GRN_ENA}] set_property PACKAGE_PIN AG17 [get_ports {RX2_GRN_ENA}] |