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| author | Wade Fife <wade.fife@ettus.com> | 2020-10-13 16:52:34 -0500 |
|---|---|---|
| committer | Wade Fife <wade.fife@ettus.com> | 2020-12-11 07:41:13 -0600 |
| commit | c6578eda2ba482b87583ebd989cdf5cbd5c3f672 (patch) | |
| tree | 6ef5751015edb1a0a6b6f38ddf16c53612337c3a /fpga/usrp3/top | |
| parent | 744e60bd598df4677a88df10d1fceb56e7c1ee36 (diff) | |
| download | uhd-c6578eda2ba482b87583ebd989cdf5cbd5c3f672.tar.gz uhd-c6578eda2ba482b87583ebd989cdf5cbd5c3f672.tar.bz2 uhd-c6578eda2ba482b87583ebd989cdf5cbd5c3f672.zip | |
fpga: e320: Improve timing on LVDS interface
Diffstat (limited to 'fpga/usrp3/top')
| -rw-r--r-- | fpga/usrp3/top/e320/e320.v | 5 |
1 files changed, 2 insertions, 3 deletions
diff --git a/fpga/usrp3/top/e320/e320.v b/fpga/usrp3/top/e320/e320.v index 92a8332f8..873677c06 100644 --- a/fpga/usrp3/top/e320/e320.v +++ b/fpga/usrp3/top/e320/e320.v @@ -818,7 +818,6 @@ module e320 ( wire [REG_DWIDTH-1:0] dboard_status; wire mimo_busclk, mimo_radioclk; wire tx_chan_sel_busclk, tx_chan_sel_radioclk; - wire rx_aligned; wire tx_pll_lock_busclk, rx_pll_lock_busclk; @@ -890,7 +889,6 @@ module e320 ( .OUTPUT_CLOCK_DELAY (0), .OUTPUT_DATA_DELAY (OUTPUT_DATA_DELAY) ) cat_io_lvds_dual_mode_i0 ( - .rst (radio_rst), .clk200 (bus_clk), // 200 MHz clock // Data and frame timing @@ -911,9 +909,10 @@ module e320 ( .ctrl_ld_out_clk_delay (1'b0), // Sample interface + .radio_rst (radio_rst), .radio_clk (radio_clk), - .rx_aligned (rx_aligned), // + .rx_aligned (), .rx_i0 (rx_i0), .rx_q0 (rx_q0), .rx_i1 (rx_i1), |