e31x: Swap out liberio for internal Ethernet

5 files changed, 522 insertions, 429 deletions

diff --git a/fpga/usrp3/top/e31x/Makefile.e31x.inc b/fpga/usrp3/top/e31x/Makefile.e31x.inc
index 7dde9a8a5..5e2b63853 100644
--- a/fpga/usrp3/top/e31x/Makefile.e31x.inc
+++ b/fpga/usrp3/top/e31x/Makefile.e31x.inc
@@ -25,6 +25,7 @@ include $(LIB_DIR)/hls/Makefile.inc
 include $(LIB_DIR)/control/Makefile.srcs
 include $(LIB_DIR)/fifo/Makefile.srcs
 include $(LIB_DIR)/axi/Makefile.srcs
+include $(LIB_DIR)/xge_interface/Makefile.srcs
 include $(LIB_DIR)/timing/Makefile.srcs
 include $(LIB_DIR)/packet_proc/Makefile.srcs
 include $(LIB_DIR)/dsp/Makefile.srcs
@@ -66,6 +67,7 @@ DESIGN_SRCS = \
 $(abspath $(TOP_SRCS)) \
 $(CONTROL_LIB_SRCS) \
 $(IP_XCI_SRCS) \
+$(XGE_INTERFACE_SRCS) \
 $(PACKET_PROC_SRCS) \
 $(AXI_SRCS) \
 $(FIFO_SRCS) \
diff --git a/fpga/usrp3/top/e31x/dts/dma-common.dtsi b/fpga/usrp3/top/e31x/dts/dma-common.dtsi
index ab6096f08..d6671e16f 100644
--- a/fpga/usrp3/top/e31x/dts/dma-common.dtsi
+++ b/fpga/usrp3/top/e31x/dts/dma-common.dtsi
@@ -1,302 +1,37 @@
+// SPDX-License-Identifier: GPL-2.0 OR X11
 /*
  * Copyright (c) 2018 National Instruments Corp
- *
- * SPDX-License-Identifier: GPL-2.0 OR X11
  */
 
 &fpga_full {
-	tx_dma0: dma@43CA0000 {
-		compatible = "adi,axi-dmac-1.00.a";
-		reg = <0x43CA0000 0x10000>;
-		interrupts = <0 53 4>;
+	nixge_internal: ethernet@40020000 {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "ni,xge-enet-3.00";
+		reg = <0x40020000 0x4000
+		       0x40030000 0x2000>;
+		reg-names = "dma", "ctrl";
+			clocks = <&clkc 15>;
+			clock-names = "bus_clk";
+
+		interrupts = <0 52 4>, <0 53 4>;
+		interrupt-names = "rx", "tx";
 		interrupt-parent = <&intc>;
-		clocks = <&clkc 15>;
-		#dma-cells = <1>;
-		adi,channels {
-			#size-cells = <0>;
-			#address-cells = <1>;
-			dma-channel@0 {
-				reg = <0>;
-				adi,source-bus-type = <0>;
-				adi,source-bus-width = <0x20>;
-				adi,destination-bus-type = <1>;
-				adi,destination-bus-width = <0x20>;
-				adi,length-width = <24>;
-			};
-		};
-	};
-	tx_dma1: dma@43CB0000 {
-		compatible = "adi,axi-dmac-1.00.a";
-		reg = <0x43CB0000 0x10000>;
-		interrupts = <0 53 4>;
-		interrupt-parent = <&intc>;
-		clocks = <&clkc 15>;
-		#dma-cells = <1>;
-		adi,channels {
-			#size-cells = <0>;
-			#address-cells = <1>;
-			dma-channel@0 {
-				reg = <0>;
-				adi,source-bus-type = <0>;
-				adi,source-bus-width = <0x20>;
-				adi,destination-bus-type = <1>;
-				adi,destination-bus-width = <0x20>;
-				adi,length-width = <24>;
-			};
-		};
-	};
-	tx_dma2: dma@43CC0000 {
-		compatible = "adi,axi-dmac-1.00.a";
-		reg = <0x43CC0000 0x10000>;
-		interrupts = <0 53 4>;
-		interrupt-parent = <&intc>;
-		clocks = <&clkc 15>;
-		#dma-cells = <1>;
-		adi,channels {
-			#size-cells = <0>;
-			#address-cells = <1>;
-			dma-channel@0 {
-				reg = <0>;
-				adi,source-bus-type = <0>;
-				adi,source-bus-width = <0x20>;
-				adi,destination-bus-type = <1>;
-				adi,destination-bus-width = <0x20>;
-				adi,length-width = <24>;
-			};
-		};
-	};
-	tx_dma3: dma@43CD0000 {
-		compatible = "adi,axi-dmac-1.00.a";
-		reg = <0x43CD0000 0x10000>;
-		interrupts = <0 53 4>;
-		interrupt-parent = <&intc>;
-		clocks = <&clkc 15>;
-		#dma-cells = <1>;
-		adi,channels {
-			#size-cells = <0>;
-			#address-cells = <1>;
-			dma-channel@0 {
-				reg = <0>;
-				adi,source-bus-type = <0>;
-				adi,source-bus-width = <0x20>;
-				adi,destination-bus-type = <1>;
-				adi,destination-bus-width = <0x20>;
-				adi,length-width = <24>;
-			};
-		};
-	};
-	tx_dma4: dma@43CE0000 {
-		compatible = "adi,axi-dmac-1.00.a";
-		reg = <0x43CE0000 0x10000>;
-		interrupts = <0 53 4>;
-		interrupt-parent = <&intc>;
-		clocks = <&clkc 15>;
-		#dma-cells = <1>;
-		adi,channels {
-			#size-cells = <0>;
-			#address-cells = <1>;
-			dma-channel@0 {
-				reg = <0>;
-				adi,source-bus-type = <0>;
-				adi,source-bus-width = <0x20>;
-				adi,destination-bus-type = <1>;
-				adi,destination-bus-width = <0x20>;
-				adi,length-width = <24>;
-			};
-		};
-	};
-	rx_dma0: dma@43C00000 {
-		compatible = "adi,axi-dmac-1.00.a";
-		reg = <0x43C00000 0x10000>;
-		interrupts = <0 52 4>;
-		interrupt-parent = <&intc>;
-		clocks = <&clkc 15>;
-		#dma-cells = <1>;
-		adi,channels {
-			#size-cells = <0>;
-			#address-cells = <1>;
-			dma-channel@0 {
-				reg = <0>;
-				adi,source-bus-type = <1>;
-				adi,source-bus-width = <0x20>;
-				adi,destination-bus-type = <0>;
-				adi,destination-bus-width = <0x20>;
-				adi,length-width = <24>;
-			};
-		};
-	};
-	rx_dma1: dma@43C10000 {
-		compatible = "adi,axi-dmac-1.00.a";
-		reg = <0x43C10000 0x10000>;
-		interrupts = <0 52 4>;
-		interrupt-parent = <&intc>;
-		clocks = <&clkc 15>;
-		#dma-cells = <1>;
-		adi,channels {
-			#size-cells = <0>;
-			#address-cells = <1>;
-			dma-channel@0 {
-				reg = <0>;
-				adi,source-bus-type = <1>;
-				adi,source-bus-width = <0x20>;
-				adi,destination-bus-type = <0>;
-				adi,destination-bus-width = <0x20>;
-				adi,length-width = <24>;
-			};
-		};
-	};
-	rx_dma2: dma@43C20000 {
-		compatible = "adi,axi-dmac-1.00.a";
-		reg = <0x43C20000 0x10000>;
-		interrupts = <0 52 4>;
-		interrupt-parent = <&intc>;
-		clocks = <&clkc 15>;
-		#dma-cells = <1>;
-		adi,channels {
-			#size-cells = <0>;
-			#address-cells = <1>;
-			dma-channel@0 {
-				reg = <0>;
-				adi,source-bus-type = <1>;
-				adi,source-bus-width = <0x20>;
-				adi,destination-bus-type = <0>;
-				adi,destination-bus-width = <0x20>;
-				adi,length-width = <24>;
-			};
-		};
-	};
-	rx_dma3: dma@43C30000 {
-		compatible = "adi,axi-dmac-1.00.a";
-		reg = <0x43C30000 0x10000>;
-		interrupts = <0 52 4>;
-		interrupt-parent = <&intc>;
-		clocks = <&clkc 15>;
-		#dma-cells = <1>;
-		adi,channels {
-			#size-cells = <0>;
-			#address-cells = <1>;
-			dma-channel@0 {
-				reg = <0>;
-				adi,source-bus-type = <1>;
-				adi,source-bus-width = <0x20>;
-				adi,destination-bus-type = <0>;
-				adi,destination-bus-width = <0x20>;
-				adi,length-width = <24>;
-			};
-		};
-	};
-
-	rx_dma4: dma@43C40000 {
-		compatible = "adi,axi-dmac-1.00.a";
-		reg = <0x43C40000 0x10000>;
-		interrupts = <0 52 4>;
-		interrupt-parent = <&intc>;
-		clocks = <&clkc 15>;
-		#dma-cells = <1>;
-		adi,channels {
-			#size-cells = <0>;
-			#address-cells = <1>;
-			dma-channel@0 {
-				reg = <0>;
-				adi,source-bus-type = <1>;
-				adi,source-bus-width = <0x20>;
-				adi,destination-bus-type = <0>;
-				adi,destination-bus-width = <0x20>;
-				adi,length-width = <24>;
-			};
-		};
-	};
-
-    usrp_rx_dma0: usrp-rx-dma@43c00000 {
-		compatible = "ettus,usrp-rx-dma";
-		dmas = <&rx_dma0 0>;
-		dma-names = "dma";
-		port-id = <0>;
 		status = "okay";
 
-		regmap = <&dma_conf0>;
-		offset = <0x0>;
-	};
-
-	usrp_rx_dma1: usrp-rx-dma@43c10000 {
-		compatible = "ettus,usrp-rx-dma";
-		dmas = <&rx_dma1 0>;
-		dma-names = "dma";
-		port-id = <1>;
-
-		regmap = <&dma_conf0>;
-		offset = <0x4>;
-	};
-
-	usrp_rx_dma2: usrp-rx-dma@43c20000 {
-		compatible = "ettus,usrp-rx-dma";
-		dmas = <&rx_dma2 0>;
-		dma-names = "dma";
-		port-id = <2>;
-
-		regmap = <&dma_conf0>;
-		offset = <0x8>;
-	};
-
-	usrp_rx_dma3: usrp-rx-dma@43c30000 {
-		compatible = "ettus,usrp-rx-dma";
-		dmas = <&rx_dma3 0>;
-		dma-names = "dma";
-		port-id = <3>;
-
-		regmap = <&dma_conf0>;
-		offset = <0xc>;
-	};
+		phy-mode = "internal";
+		local-mac-address = <0x00 0x01 0x02 0x03 0x04 0x05>;
 
-	usrp_rx_dma4: usrp-rx-dma@43c40000 {
-		compatible = "ettus,usrp-rx-dma";
-		dmas = <&rx_dma4 0>;
-		dma-names = "dma";
-		port-id = <4>;
-
-		regmap = <&dma_conf0>;
-		offset = <0x10>;
-	};
-	usrp_tx_dma0: usrp-tx-dma@43ca0000 {
-		compatible = "ettus,usrp-tx-dma";
-		dmas = <&tx_dma0 0>;
-		dma-names = "dma";
-		port-id = <0>;
-	};
-
-	usrp_tx_dma1: usrp-tx-dma@43cb0000 {
-		compatible = "ettus,usrp-tx-dma";
-		dmas = <&tx_dma1 0>;
-		dma-names = "dma";
-		port-id = <1>;
-	};
-
-	usrp_tx_dma2: usrp-tx-dma@43cc0000 {
-		compatible = "ettus,usrp-tx-dma";
-		dmas = <&tx_dma2 0>;
-		dma-names = "dma";
-		port-id = <2>;
-		status = "okay";
-	};
-
-	usrp_tx_dma3: usrp-tx-dma@43cd0000 {
-		compatible = "ettus,usrp-tx-dma";
-		dmas = <&tx_dma3 0>;
-		dma-names = "dma";
-		port-id = <3>;
-	};
-
-	usrp_tx_dma4: usrp-tx-dma@43ce0000 {
-		compatible = "ettus,usrp-tx-dma";
-		dmas = <&tx_dma4 0>;
-		dma-names = "dma";
-		port-id = <4>;
-		status = "okay";
+		fixed-link {
+			speed = <1000>;
+			full-duplex;
+		};
 	};
 
-	dma_conf0: dma_conf0@42080000 {
-		compatible = "syscon";
-		reg = <0x42080000 0x1000>;
+	uio@40032000 {
+		compatible = "usrp-uio";
+		reg = <0x40032000 0x2000>;
+		reg-names = "misc-enet-int-regs";
 		status = "okay";
 	};
 };
diff --git a/fpga/usrp3/top/e31x/e31x.v b/fpga/usrp3/top/e31x/e31x.v
index 3902ed551..7f0d159a6 100644
--- a/fpga/usrp3/top/e31x/e31x.v
+++ b/fpga/usrp3/top/e31x/e31x.v
@@ -168,6 +168,22 @@ module e31x (
   wire clk40_rstn;
   wire FCLK_RESET0_N;
 
+  //ETH DMA
+  wire        m_axi_eth_internal_arvalid;
+  wire        m_axi_eth_internal_awvalid;
+  wire        m_axi_eth_internal_bready;
+  wire        m_axi_eth_internal_rready;
+  wire        m_axi_eth_internal_wvalid;
+  wire [31:0] m_axi_eth_internal_araddr;
+  wire [31:0] m_axi_eth_internal_awaddr;
+  wire [31:0] m_axi_eth_internal_wdata;
+  wire [3:0]  m_axi_eth_internal_wstrb;
+  wire        m_axi_eth_internal_rvalid;
+  wire        m_axi_eth_internal_wready;
+  wire [1:0]  m_axi_eth_internal_bresp;
+  wire [1:0]  m_axi_eth_internal_rresp;
+  wire [31:0] m_axi_eth_internal_rdata;  
+
   // Crossbar
   wire        m_axi_xbar_arvalid;
   wire        m_axi_xbar_awvalid;
@@ -212,15 +228,25 @@ module e31x (
   wire [3:0]  m_axi_pmu_wstrb;
   wire        m_axi_pmu_wvalid;
 
-  // DMA xport adapter to PS
+  // Internal Ethernet xport adapter to PS
+  wire [63:0] h2e_tdata;
+  wire [7:0]  h2e_tkeep;
+  wire        h2e_tlast;
+  wire        h2e_tready;
+  wire        h2e_tvalid;
+
+  wire [63:0] e2h_tdata;
+  wire [7:0]  e2h_tkeep;
+  wire        e2h_tlast;
+  wire        e2h_tready;
+  wire        e2h_tvalid;
+
   wire [63:0] m_axis_dma_tdata;
-  wire [3:0]  m_axis_dma_tuser;
   wire        m_axis_dma_tlast;
   wire        m_axis_dma_tready;
   wire        m_axis_dma_tvalid;
 
   wire [63:0] s_axis_dma_tdata;
-  wire [3:0]  s_axis_dma_tdest;
   wire        s_axis_dma_tlast;
   wire        s_axis_dma_tready;
   wire        s_axis_dma_tvalid;
@@ -356,6 +382,79 @@ module e31x (
 
   /////////////////////////////////////////////////////////////////////
   //
+  // Internal Ethernet Interface
+  //
+  //////////////////////////////////////////////////////////////////////
+  eth_internal #(
+    .DWIDTH(REG_DWIDTH),
+    .AWIDTH(REG_AWIDTH),
+    .PORTNUM(8'd1)
+  ) eth_internal_i (
+    // Resets
+    .bus_rst (bus_rst),
+
+    // Clocks
+    .bus_clk (bus_clk),
+
+    //Axi-lite
+    .s_axi_aclk     (clk40),
+    .s_axi_aresetn  (clk40_rstn),
+    .s_axi_awaddr   (m_axi_eth_internal_awaddr),
+    .s_axi_awvalid  (m_axi_eth_internal_awvalid),
+    .s_axi_awready  (m_axi_eth_internal_awready),
+
+    .s_axi_wdata    (m_axi_eth_internal_wdata),
+    .s_axi_wstrb    (m_axi_eth_internal_wstrb),
+    .s_axi_wvalid   (m_axi_eth_internal_wvalid),
+    .s_axi_wready   (m_axi_eth_internal_wready),
+
+    .s_axi_bresp    (m_axi_eth_internal_bresp),
+    .s_axi_bvalid   (m_axi_eth_internal_bvalid),
+    .s_axi_bready   (m_axi_eth_internal_bready),
+
+    .s_axi_araddr   (m_axi_eth_internal_araddr),
+    .s_axi_arvalid  (m_axi_eth_internal_arvalid),
+    .s_axi_arready  (m_axi_eth_internal_arready),
+
+    .s_axi_rdata    (m_axi_eth_internal_rdata),
+    .s_axi_rresp    (m_axi_eth_internal_rresp),
+    .s_axi_rvalid   (m_axi_eth_internal_rvalid),
+    .s_axi_rready   (m_axi_eth_internal_rready),
+
+    // Host-Ethernet DMA interface
+    .e2h_tdata    (e2h_tdata),
+    .e2h_tkeep    (e2h_tkeep),
+    .e2h_tlast    (e2h_tlast),
+    .e2h_tvalid   (e2h_tvalid),
+    .e2h_tready   (e2h_tready),
+
+    .h2e_tdata    (h2e_tdata),
+    .h2e_tkeep    (h2e_tkeep),
+    .h2e_tlast    (h2e_tlast),
+    .h2e_tvalid   (h2e_tvalid),
+    .h2e_tready   (h2e_tready),
+
+    // Vita router interface
+    .e2v_tdata    (m_axis_dma_tdata),
+    .e2v_tlast    (m_axis_dma_tlast),
+    .e2v_tvalid   (m_axis_dma_tvalid),
+    .e2v_tready   (m_axis_dma_tready),
+
+    .v2e_tdata    (s_axis_dma_tdata),
+    .v2e_tlast    (s_axis_dma_tlast),
+    .v2e_tvalid   (s_axis_dma_tvalid),
+    .v2e_tready   (s_axis_dma_tready),
+
+    // MISC
+    .port_info    (),
+    .device_id    (device_id),
+
+    .link_up      (),
+    .activity     ()
+  );
+
+  /////////////////////////////////////////////////////////////////////
+  //
   // PS Connections
   //
   //////////////////////////////////////////////////////////////////////
@@ -440,6 +539,27 @@ module e31x (
     .SPI1_SS_O(),
     .SPI1_SS_T(),
 
+    // Ethernet DMA engines
+    .m_axi_eth_internal_araddr(m_axi_eth_internal_araddr),
+    .m_axi_eth_internal_arprot(),
+    .m_axi_eth_internal_arready(m_axi_eth_internal_arready),
+    .m_axi_eth_internal_arvalid(m_axi_eth_internal_arvalid),
+    .m_axi_eth_internal_awaddr(m_axi_eth_internal_awaddr),
+    .m_axi_eth_internal_awprot(),
+    .m_axi_eth_internal_awready(m_axi_eth_internal_awready),
+    .m_axi_eth_internal_awvalid(m_axi_eth_internal_awvalid),
+    .m_axi_eth_internal_bready(m_axi_eth_internal_bready),
+    .m_axi_eth_internal_bresp(m_axi_eth_internal_bresp),
+    .m_axi_eth_internal_bvalid(m_axi_eth_internal_bvalid),
+    .m_axi_eth_internal_rdata(m_axi_eth_internal_rdata),
+    .m_axi_eth_internal_rready(m_axi_eth_internal_rready),
+    .m_axi_eth_internal_rresp(m_axi_eth_internal_rresp),
+    .m_axi_eth_internal_rvalid(m_axi_eth_internal_rvalid),
+    .m_axi_eth_internal_wdata(m_axi_eth_internal_wdata),
+    .m_axi_eth_internal_wready(m_axi_eth_internal_wready),
+    .m_axi_eth_internal_wstrb(m_axi_eth_internal_wstrb),
+    .m_axi_eth_internal_wvalid(m_axi_eth_internal_wvalid),
+
     // USB
     .USBIND_0_port_indctl(),
     .USBIND_0_vbus_pwrfault(),
@@ -495,16 +615,16 @@ module e31x (
     .m_axi_pmu_wvalid(m_axi_pmu_wvalid),
 
     // DMA
-    .s_axis_dma_tdata(s_axis_dma_tdata),
-    .s_axis_dma_tdest(s_axis_dma_tdest),
-    .s_axis_dma_tlast(s_axis_dma_tlast),
-    .s_axis_dma_tready(s_axis_dma_tready),
-    .s_axis_dma_tvalid(s_axis_dma_tvalid),
-    .m_axis_dma_tdata(m_axis_dma_tdata),
-    .m_axis_dma_tuser(m_axis_dma_tuser),
-    .m_axis_dma_tlast(m_axis_dma_tlast),
-    .m_axis_dma_tready(m_axis_dma_tready),
-    .m_axis_dma_tvalid(m_axis_dma_tvalid)
+    .s_axis_dma_tdata(e2h_tdata),
+    .s_axis_dma_tkeep(e2h_tkeep),
+    .s_axis_dma_tlast(e2h_tlast),
+    .s_axis_dma_tready(e2h_tready),
+    .s_axis_dma_tvalid(e2h_tvalid),
+    .m_axis_dma_tdata(h2e_tdata),
+    .m_axis_dma_tkeep(h2e_tkeep),
+    .m_axis_dma_tlast(h2e_tlast),
+    .m_axis_dma_tready(h2e_tready),
+    .m_axis_dma_tvalid(h2e_tvalid)
   );
 
   /////////////////////////////////////////////////////////////////////
@@ -787,15 +907,13 @@ module e31x (
     .rx(rx_flat),
     .tx(tx_flat),
 
-    // DMA to PS
+    // Internal DMA to PS
     .m_dma_tdata(s_axis_dma_tdata),
-    .m_dma_tdest(s_axis_dma_tdest),
     .m_dma_tlast(s_axis_dma_tlast),
     .m_dma_tready(s_axis_dma_tready),
     .m_dma_tvalid(s_axis_dma_tvalid),
 
     .s_dma_tdata(m_axis_dma_tdata),
-    .s_dma_tuser(m_axis_dma_tuser),
     .s_dma_tlast(m_axis_dma_tlast),
     .s_dma_tready(m_axis_dma_tready),
     .s_dma_tvalid(m_axis_dma_tvalid),
diff --git a/fpga/usrp3/top/e31x/e31x_core.v b/fpga/usrp3/top/e31x/e31x_core.v
index 7cd2dddf4..fc911553d 100644
--- a/fpga/usrp3/top/e31x/e31x_core.v
+++ b/fpga/usrp3/top/e31x/e31x_core.v
@@ -98,13 +98,11 @@ module e31x_core #(
 
   // DMA xport adapter to PS
   input wire  [63:0] s_dma_tdata,
-  input wire  [3:0]  s_dma_tuser,
   input wire         s_dma_tlast,
   output wire        s_dma_tready,
   input wire         s_dma_tvalid,
 
   output wire [63:0] m_dma_tdata,
-  output wire [3:0]  m_dma_tdest,
   output wire        m_dma_tlast,
   input wire         m_dma_tready,
   output wire        m_dma_tvalid,
@@ -370,50 +368,6 @@ module e31x_core #(
 
   /////////////////////////////////////////////////////////////////////////////
   //
-  // DMA Transport Adapter
-  //
-  /////////////////////////////////////////////////////////////////////////////
-  wire [63:0] dmao_tdata;
-  wire        dmao_tlast;
-  wire        dmao_tvalid;
-  wire        dmao_tready;
-
-  wire [63:0] dmai_tdata;
-  wire        dmai_tlast;
-  wire        dmai_tvalid;
-  wire        dmai_tready;
-
-  liberio_chdr64_adapter #(
-    .DMA_ID_WIDTH                    (4)
-  ) dma_xport_adapter (
-    .clk                             (bus_clk),
-    .rst                             (bus_rst),
-    .device_id                       (device_id),
-    // From DMA engine to core
-    .s_dma_tdata                     (s_dma_tdata),
-    .s_dma_tuser                     (s_dma_tuser),
-    .s_dma_tlast                     (s_dma_tlast),
-    .s_dma_tvalid                    (s_dma_tvalid),
-    .s_dma_tready                    (s_dma_tready),
-    // From core to DMA engine
-    .m_dma_tdata                     (m_dma_tdata),
-    .m_dma_tuser                     (m_dma_tdest),
-    .m_dma_tlast                     (m_dma_tlast),
-    .m_dma_tvalid                    (m_dma_tvalid),
-    .m_dma_tready                    (m_dma_tready),
-    // CHDR buses
-    .s_chdr_tdata                    (dmao_tdata),
-    .s_chdr_tlast                    (dmao_tlast),
-    .s_chdr_tvalid                   (dmao_tvalid),
-    .s_chdr_tready                   (dmao_tready),
-    .m_chdr_tdata                    (dmai_tdata),
-    .m_chdr_tlast                    (dmai_tlast),
-    .m_chdr_tvalid                   (dmai_tvalid),
-    .m_chdr_tready                   (dmai_tready)
-  );
-
-  /////////////////////////////////////////////////////////////////////////////
-  //
   // Radio Daughter board and Front End Control
   //
   /////////////////////////////////////////////////////////////////////////////
@@ -637,14 +591,14 @@ module e31x_core #(
     .radio_tx_stb            ({tx_stb[1],     tx_stb[0]    }),
     .radio_tx_data           ({tx_data[1],    tx_data[0]   }),
     .radio_tx_running        ({tx_running[1], tx_running[0]}),
-    .s_dma_tdata             (dmai_tdata),
-    .s_dma_tlast             (dmai_tlast),
-    .s_dma_tvalid            (dmai_tvalid),
-    .s_dma_tready            (dmai_tready),
-    .m_dma_tdata             (dmao_tdata),
-    .m_dma_tlast             (dmao_tlast),
-    .m_dma_tvalid            (dmao_tvalid),
-    .m_dma_tready            (dmao_tready)
+    .s_dma_tdata             (s_dma_tdata),
+    .s_dma_tlast             (s_dma_tlast),
+    .s_dma_tvalid            (s_dma_tvalid),
+    .s_dma_tready            (s_dma_tready),
+    .m_dma_tdata             (m_dma_tdata),
+    .m_dma_tlast             (m_dma_tlast),
+    .m_dma_tvalid            (m_dma_tvalid),
+    .m_dma_tready            (m_dma_tready)
   );
 
   //---------------------------------------------------------------------------
diff --git a/fpga/usrp3/top/e31x/ip/e31x_ps_bd/e31x_ps_bd.tcl b/fpga/usrp3/top/e31x/ip/e31x_ps_bd/e31x_ps_bd.tcl
index b6b3cb1e5..55ab5fad9 100644
--- a/fpga/usrp3/top/e31x/ip/e31x_ps_bd/e31x_ps_bd.tcl
+++ b/fpga/usrp3/top/e31x/ip/e31x_ps_bd/e31x_ps_bd.tcl
@@ -1,6 +1,60 @@
+
+################################################################
+# This is a generated script based on design: e31x_ps_bd
+#
+# Though there are limitations about the generated script,
+# the main purpose of this utility is to make learning
+# IP Integrator Tcl commands easier.
+################################################################
+
+namespace eval _tcl {
+proc get_script_folder {} {
+   set script_path [file normalize [info script]]
+   set script_folder [file dirname $script_path]
+   return $script_folder
+}
+}
+variable script_folder
+set script_folder [_tcl::get_script_folder]
+
+################################################################
+# Check if script is running in correct Vivado version.
+################################################################
+set scripts_vivado_version 2019.1
+set current_vivado_version [version -short]
+
+if { [string first $scripts_vivado_version $current_vivado_version] == -1 } {
+   puts ""
+   catch {common::send_msg_id "BD_TCL-109" "ERROR" "This script was generated using Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Please run the script in Vivado <$scripts_vivado_version> then open the design in Vivado <$current_vivado_version>. Upgrade the design by running \"Tools => Report => Report IP Status...\", then run write_bd_tcl to create an updated script."}
+
+   return 1
+}
+
+################################################################
+# START
+################################################################
+
+# To test this script, run the following commands from Vivado Tcl console:
+# source e31x_ps_bd_script.tcl
+
+# If there is no project opened, this script will create a
+# project, but make sure you do not have an existing project
+# <./myproj/project_1.xpr> in the current working folder.
+
+set list_projs [get_projects -quiet]
+if { $list_projs eq "" } {
+   create_project project_1 myproj -part xc7z020clg484-3
+}
+
+
 # CHANGE DESIGN NAME HERE
+variable design_name
 set design_name e31x_ps_bd
 
+# If you do not already have an existing IP Integrator design open,
+# you can create a design using the following command:
+#    create_bd_design $design_name
+
 # Creating design if needed
 set errMsg ""
 set nRet 0
@@ -8,25 +62,216 @@ set nRet 0
 set cur_design [current_bd_design -quiet]
 set list_cells [get_bd_cells -quiet]
 
-create_bd_design $design_name
-current_bd_design $design_name
+if { ${design_name} eq "" } {
+   # USE CASES:
+   #    1) Design_name not set
+
+   set errMsg "Please set the variable <design_name> to a non-empty value."
+   set nRet 1
+
+} elseif { ${cur_design} ne "" && ${list_cells} eq "" } {
+   # USE CASES:
+   #    2): Current design opened AND is empty AND names same.
+   #    3): Current design opened AND is empty AND names diff; design_name NOT in project.
+   #    4): Current design opened AND is empty AND names diff; design_name exists in project.
+
+   if { $cur_design ne $design_name } {
+      common::send_msg_id "BD_TCL-001" "INFO" "Changing value of <design_name> from <$design_name> to <$cur_design> since current design is empty."
+      set design_name [get_property NAME $cur_design]
+   }
+   common::send_msg_id "BD_TCL-002" "INFO" "Constructing design in IPI design <$cur_design>..."
+
+} elseif { ${cur_design} ne "" && $list_cells ne "" && $cur_design eq $design_name } {
+   # USE CASES:
+   #    5) Current design opened AND has components AND same names.
+
+   set errMsg "Design <$design_name> already exists in your project, please set the variable <design_name> to another value."
+   set nRet 1
+} elseif { [get_files -quiet ${design_name}.bd] ne "" } {
+   # USE CASES: 
+   #    6) Current opened design, has components, but diff names, design_name exists in project.
+   #    7) No opened design, design_name exists in project.
+
+   set errMsg "Design <$design_name> already exists in your project, please set the variable <design_name> to another value."
+   set nRet 2
+
+} else {
+   # USE CASES:
+   #    8) No opened design, design_name not in project.
+   #    9) Current opened design, has components, but diff names, design_name not in project.
+
+   common::send_msg_id "BD_TCL-003" "INFO" "Currently there is no design <$design_name> in project, so creating one..."
+
+   create_bd_design $design_name
+
+   common::send_msg_id "BD_TCL-004" "INFO" "Making design <$design_name> as current_bd_design."
+   current_bd_design $design_name
+
+}
+
+common::send_msg_id "BD_TCL-005" "INFO" "Currently the variable <design_name> is equal to \"$design_name\"."
 
 if { $nRet != 0 } {
-   puts $errMsg
+   catch {common::send_msg_id "BD_TCL-114" "ERROR" $errMsg}
    return $nRet
 }
 
-set scriptDir [file dirname [info script]]
+set bCheckIPsPassed 1
+##################################################################
+# CHECK IPs
+##################################################################
+set bCheckIPs 1
+if { $bCheckIPs == 1 } {
+   set list_check_ips "\ 
+xilinx.com:ip:processing_system7:5.5\
+xilinx.com:ip:smartconnect:1.0\
+xilinx.com:ip:xlconcat:2.1\
+xilinx.com:ip:xlslice:1.0\
+xilinx.com:ip:axi_dma:7.1\
+xilinx.com:ip:axi_protocol_converter:2.1\
+"
+
+   set list_ips_missing ""
+   common::send_msg_id "BD_TCL-006" "INFO" "Checking if the following IPs exist in the project's IP catalog: $list_check_ips ."
+
+   foreach ip_vlnv $list_check_ips {
+      set ip_obj [get_ipdefs -all $ip_vlnv]
+      if { $ip_obj eq "" } {
+         lappend list_ips_missing $ip_vlnv
+      }
+   }
+
+   if { $list_ips_missing ne "" } {
+      catch {common::send_msg_id "BD_TCL-115" "ERROR" "The following IPs are not found in the IP Catalog:\n  $list_ips_missing\n\nResolution: Please add the repository containing the IP(s) to the project." }
+      set bCheckIPsPassed 0
+   }
+
+}
+
+if { $bCheckIPsPassed != 1 } {
+  common::send_msg_id "BD_TCL-1003" "WARNING" "Will not continue with creation of design due to the error(s) above."
+  return 3
+}
 
 ##################################################################
 # DESIGN PROCs
 ##################################################################
-source "$scriptDir/chdr_dma_top.tcl"
+
+
+# Hierarchical cell: dma
+proc create_hier_cell_dma { parentCell nameHier } {
+
+  variable script_folder
+
+  if { $parentCell eq "" || $nameHier eq "" } {
+     catch {common::send_msg_id "BD_TCL-102" "ERROR" "create_hier_cell_dma() - Empty argument(s)!"}
+     return
+  }
+
+  # Get object for parentCell
+  set parentObj [get_bd_cells $parentCell]
+  if { $parentObj == "" } {
+     catch {common::send_msg_id "BD_TCL-100" "ERROR" "Unable to find parent cell <$parentCell>!"}
+     return
+  }
+
+  # Make sure parentObj is hier blk
+  set parentType [get_property TYPE $parentObj]
+  if { $parentType ne "hier" } {
+     catch {common::send_msg_id "BD_TCL-101" "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>."}
+     return
+  }
+
+  # Save current instance; Restore later
+  set oldCurInst [current_bd_instance .]
+
+  # Set parent object as current
+  current_bd_instance $parentObj
+
+  # Create cell and set as current instance
+  set hier_obj [create_bd_cell -type hier $nameHier]
+  current_bd_instance $hier_obj
+
+  # Create interface pins
+  create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 M_AXI_DMA_SG
+
+  create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 M_AXI_RX_DMA
+
+  create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 M_AXI_TX_DMA
+
+  create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:axis_rtl:1.0 m_axis_dma
+
+  create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 s_axi_dmac
+
+  create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:axis_rtl:1.0 s_axis_dma
+
+
+  # Create pins
+  create_bd_pin -dir I bus_clk
+  create_bd_pin -dir I bus_rstn
+  create_bd_pin -dir I clk40
+  create_bd_pin -dir I clk40_rstn
+  create_bd_pin -dir O rx_irq
+  create_bd_pin -dir O tx_irq
+
+  # Create instance: axi_dma_eth_internal, and set properties
+  set axi_dma_eth_internal [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_dma:7.1 axi_dma_eth_internal ]
+  set_property -dict [ list \
+   CONFIG.c_enable_multi_channel {0} \
+   CONFIG.c_include_mm2s_dre {1} \
+   CONFIG.c_include_s2mm_dre {1} \
+   CONFIG.c_m_axi_mm2s_data_width {64} \
+   CONFIG.c_m_axis_mm2s_tdata_width {64} \
+   CONFIG.c_mm2s_burst_size {16} \
+   CONFIG.c_num_mm2s_channels {1} \
+   CONFIG.c_num_s2mm_channels {1} \
+   CONFIG.c_s2mm_burst_size {16} \
+   CONFIG.c_sg_include_stscntrl_strm {0} \
+ ] $axi_dma_eth_internal
+
+  # Create instance: axi_protocol_convert_rx, and set properties
+  set axi_protocol_convert_rx [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_protocol_converter:2.1 axi_protocol_convert_rx ]
+  set_property -dict [ list \
+   CONFIG.TRANSLATION_MODE {0} \
+ ] $axi_protocol_convert_rx
+
+  # Create instance: axi_protocol_convert_tx, and set properties
+  set axi_protocol_convert_tx [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_protocol_converter:2.1 axi_protocol_convert_tx ]
+  set_property -dict [ list \
+   CONFIG.TRANSLATION_MODE {0} \
+ ] $axi_protocol_convert_tx
+
+  # Create interface connections
+  connect_bd_intf_net -intf_net axi_dma_0_M_AXIS_MM2S [get_bd_intf_pins m_axis_dma] [get_bd_intf_pins axi_dma_eth_internal/M_AXIS_MM2S]
+  connect_bd_intf_net -intf_net axi_dma_0_M_AXI_MM2S [get_bd_intf_pins axi_dma_eth_internal/M_AXI_MM2S] [get_bd_intf_pins axi_protocol_convert_tx/S_AXI]
+  connect_bd_intf_net -intf_net axi_dma_0_M_AXI_S2MM [get_bd_intf_pins axi_dma_eth_internal/M_AXI_S2MM] [get_bd_intf_pins axi_protocol_convert_rx/S_AXI]
+  connect_bd_intf_net -intf_net axi_dma_eth_internal_M_AXI_SG [get_bd_intf_pins M_AXI_DMA_SG] [get_bd_intf_pins axi_dma_eth_internal/M_AXI_SG]
+  connect_bd_intf_net -intf_net axi_protocol_convert_0_M_AXI [get_bd_intf_pins M_AXI_TX_DMA] [get_bd_intf_pins axi_protocol_convert_tx/M_AXI]
+  connect_bd_intf_net -intf_net axi_protocol_convert_1_M_AXI [get_bd_intf_pins M_AXI_RX_DMA] [get_bd_intf_pins axi_protocol_convert_rx/M_AXI]
+  connect_bd_intf_net -intf_net s_axi_dmac_1 [get_bd_intf_pins s_axi_dmac] [get_bd_intf_pins axi_dma_eth_internal/S_AXI_LITE]
+  connect_bd_intf_net -intf_net s_axis_dma_1 [get_bd_intf_pins s_axis_dma] [get_bd_intf_pins axi_dma_eth_internal/S_AXIS_S2MM]
+
+  # Create port connections
+  connect_bd_net -net axi_dma_0_mm2s_introut [get_bd_pins tx_irq] [get_bd_pins axi_dma_eth_internal/mm2s_introut]
+  connect_bd_net -net axi_dma_0_s2mm_introut [get_bd_pins rx_irq] [get_bd_pins axi_dma_eth_internal/s2mm_introut]
+  connect_bd_net -net axi_dma_0_s2mm_prmry_reset_out_n [get_bd_pins axi_dma_eth_internal/s2mm_prmry_reset_out_n] [get_bd_pins axi_protocol_convert_rx/aresetn]
+  connect_bd_net -net axi_dma_eth_internal_mm2s_prmry_reset_out_n [get_bd_pins axi_dma_eth_internal/mm2s_prmry_reset_out_n] [get_bd_pins axi_protocol_convert_tx/aresetn]
+  connect_bd_net -net bus_clk_1 [get_bd_pins bus_clk] [get_bd_pins axi_dma_eth_internal/m_axi_mm2s_aclk] [get_bd_pins axi_dma_eth_internal/m_axi_s2mm_aclk] [get_bd_pins axi_dma_eth_internal/m_axi_sg_aclk] [get_bd_pins axi_protocol_convert_rx/aclk] [get_bd_pins axi_protocol_convert_tx/aclk]
+  connect_bd_net -net clk40_1 [get_bd_pins clk40] [get_bd_pins axi_dma_eth_internal/s_axi_lite_aclk]
+  connect_bd_net -net clk40_rstn_1 [get_bd_pins clk40_rstn] [get_bd_pins axi_dma_eth_internal/axi_resetn]
+
+  # Restore current instance
+  current_bd_instance $oldCurInst
+}
+
 
 # Procedure to create entire design; Provide argument to make
 # procedure reusable. If parentCell is "", will use root.
 proc create_root_design { parentCell } {
 
+  variable script_folder
+  variable design_name
+
   if { $parentCell eq "" } {
      set parentCell [get_bd_cells /]
   }
@@ -34,14 +279,14 @@ proc create_root_design { parentCell } {
   # Get object for parentCell
   set parentObj [get_bd_cells $parentCell]
   if { $parentObj == "" } {
-     puts "ERROR: Unable to find parent cell <$parentCell>!"
+     catch {common::send_msg_id "BD_TCL-100" "ERROR" "Unable to find parent cell <$parentCell>!"}
      return
   }
 
   # Make sure parentObj is hier blk
   set parentType [get_property TYPE $parentObj]
   if { $parentType ne "hier" } {
-     puts "ERROR: Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>."
+     catch {common::send_msg_id "BD_TCL-101" "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>."}
      return
   }
 
@@ -54,14 +299,27 @@ proc create_root_design { parentCell } {
 
   # Create interface ports
   set DDR [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:ddrx_rtl:1.0 DDR ]
+
   set GPIO_0 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:gpio_rtl:1.0 GPIO_0 ]
-  set m_axis_dma [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:axis_rtl:1.0 m_axis_dma ]
-  set s_axis_dma [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:axis_rtl:1.0 s_axis_dma ]
+
+  set USBIND_0 [ create_bd_intf_port -mode Master -vlnv xilinx.com:display_processing_system7:usbctrl_rtl:1.0 USBIND_0 ]
+
+  set m_axi_eth_internal [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 m_axi_eth_internal ]
   set_property -dict [ list \
-   CONFIG.HAS_TLAST 1 \
-   CONFIG.TDATA_NUM_BYTES 8 \
-   CONFIG.TDEST_WIDTH 4 \
-  ] $s_axis_dma
+   CONFIG.ADDR_WIDTH {31} \
+   CONFIG.DATA_WIDTH {32} \
+   CONFIG.FREQ_HZ {40000000} \
+   CONFIG.HAS_BURST {0} \
+   CONFIG.HAS_CACHE {0} \
+   CONFIG.HAS_LOCK {0} \
+   CONFIG.HAS_PROT {0} \
+   CONFIG.HAS_QOS {0} \
+   CONFIG.HAS_WSTRB {0} \
+   CONFIG.NUM_READ_OUTSTANDING {2} \
+   CONFIG.NUM_WRITE_OUTSTANDING {2} \
+   CONFIG.PROTOCOL {AXI4LITE} \
+   ] $m_axi_eth_internal
+
   set m_axi_pmu [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 m_axi_pmu ]
   set_property -dict [ list \
    CONFIG.ADDR_WIDTH {32} \
@@ -77,6 +335,7 @@ proc create_root_design { parentCell } {
    CONFIG.NUM_WRITE_OUTSTANDING {2} \
    CONFIG.PROTOCOL {AXI4LITE} \
    ] $m_axi_pmu
+
   set m_axi_xbar [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 m_axi_xbar ]
   set_property -dict [ list \
    CONFIG.ADDR_WIDTH {32} \
@@ -92,7 +351,26 @@ proc create_root_design { parentCell } {
    CONFIG.NUM_WRITE_OUTSTANDING {2} \
    CONFIG.PROTOCOL {AXI4LITE} \
    ] $m_axi_xbar
-  set USBIND_0 [ create_bd_intf_port -mode Master -vlnv xilinx.com:display_processing_system7:usbctrl_rtl:1.0 USBIND_0 ]
+
+  set m_axis_dma [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:axis_rtl:1.0 m_axis_dma ]
+  set_property -dict [ list \
+   CONFIG.FREQ_HZ {200000000} \
+   ] $m_axis_dma
+
+  set s_axis_dma [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:axis_rtl:1.0 s_axis_dma ]
+  set_property -dict [ list \
+   CONFIG.FREQ_HZ {200000000} \
+   CONFIG.HAS_TKEEP {0} \
+   CONFIG.HAS_TLAST {1} \
+   CONFIG.HAS_TREADY {1} \
+   CONFIG.HAS_TSTRB {0} \
+   CONFIG.LAYERED_METADATA {undef} \
+   CONFIG.TDATA_NUM_BYTES {8} \
+   CONFIG.TDEST_WIDTH {4} \
+   CONFIG.TID_WIDTH {0} \
+   CONFIG.TUSER_WIDTH {0} \
+   ] $s_axis_dma
+
 
   # Create ports
   set DDR_VRN [ create_bd_port -dir IO DDR_VRN ]
@@ -154,7 +432,7 @@ proc create_root_design { parentCell } {
   set bus_rstn [ create_bd_port -dir I -type rst bus_rstn ]
   set clk40 [ create_bd_port -dir I -type clk clk40 ]
   set_property -dict [ list \
-   CONFIG.ASSOCIATED_BUSIF {m_axi_xbar:m_axi_pmu} \
+   CONFIG.ASSOCIATED_BUSIF {m_axi_pmu:m_axi_xbar:m_axi_eth_internal} \
    CONFIG.ASSOCIATED_RESET {clk40_rstn} \
    CONFIG.FREQ_HZ {40000000} \
  ] $clk40
@@ -164,16 +442,16 @@ proc create_root_design { parentCell } {
   set axi_interconnect_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_interconnect_0 ]
   set_property -dict [ list \
    CONFIG.ENABLE_ADVANCED_OPTIONS {0} \
-   CONFIG.NUM_MI {5} \
+   CONFIG.NUM_MI {4} \
  ] $axi_interconnect_0
 
   # Create instance: dma
-  create_hier_cell_dma [current_bd_instance .] dma 5
+  create_hier_cell_dma [current_bd_instance .] dma
 
   # Create instance: processing_system7_0, and set properties
   set processing_system7_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:processing_system7:5.5 processing_system7_0 ]
   set_property -dict [ list \
-   CONFIG.PCW_ACT_APU_PERIPHERAL_FREQMHZ {666.666687} \
+   CONFIG.PCW_ACT_APU_PERIPHERAL_FREQMHZ {866.666687} \
    CONFIG.PCW_ACT_CAN_PERIPHERAL_FREQMHZ {10.000000} \
    CONFIG.PCW_ACT_DCI_PERIPHERAL_FREQMHZ {10.158730} \
    CONFIG.PCW_ACT_ENET0_PERIPHERAL_FREQMHZ {125.000000} \
@@ -188,23 +466,23 @@ proc create_root_design { parentCell } {
    CONFIG.PCW_ACT_SMC_PERIPHERAL_FREQMHZ {10.000000} \
    CONFIG.PCW_ACT_SPI_PERIPHERAL_FREQMHZ {166.666672} \
    CONFIG.PCW_ACT_TPIU_PERIPHERAL_FREQMHZ {200.000000} \
-   CONFIG.PCW_ACT_TTC0_CLK0_PERIPHERAL_FREQMHZ {111.111115} \
-   CONFIG.PCW_ACT_TTC0_CLK1_PERIPHERAL_FREQMHZ {111.111115} \
-   CONFIG.PCW_ACT_TTC0_CLK2_PERIPHERAL_FREQMHZ {111.111115} \
-   CONFIG.PCW_ACT_TTC1_CLK0_PERIPHERAL_FREQMHZ {111.111115} \
-   CONFIG.PCW_ACT_TTC1_CLK1_PERIPHERAL_FREQMHZ {111.111115} \
-   CONFIG.PCW_ACT_TTC1_CLK2_PERIPHERAL_FREQMHZ {111.111115} \
+   CONFIG.PCW_ACT_TTC0_CLK0_PERIPHERAL_FREQMHZ {144.444443} \
+   CONFIG.PCW_ACT_TTC0_CLK1_PERIPHERAL_FREQMHZ {144.444443} \
+   CONFIG.PCW_ACT_TTC0_CLK2_PERIPHERAL_FREQMHZ {144.444443} \
+   CONFIG.PCW_ACT_TTC1_CLK0_PERIPHERAL_FREQMHZ {144.444443} \
+   CONFIG.PCW_ACT_TTC1_CLK1_PERIPHERAL_FREQMHZ {144.444443} \
+   CONFIG.PCW_ACT_TTC1_CLK2_PERIPHERAL_FREQMHZ {144.444443} \
    CONFIG.PCW_ACT_UART_PERIPHERAL_FREQMHZ {100.000000} \
-   CONFIG.PCW_ACT_WDT_PERIPHERAL_FREQMHZ {111.111115} \
+   CONFIG.PCW_ACT_WDT_PERIPHERAL_FREQMHZ {144.444443} \
    CONFIG.PCW_APU_PERIPHERAL_FREQMHZ {1000} \
-   CONFIG.PCW_ARMPLL_CTRL_FBDIV {40} \
+   CONFIG.PCW_ARMPLL_CTRL_FBDIV {52} \
    CONFIG.PCW_CAN_PERIPHERAL_DIVISOR0 {1} \
    CONFIG.PCW_CAN_PERIPHERAL_DIVISOR1 {1} \
    CONFIG.PCW_CLK0_FREQ {100000000} \
    CONFIG.PCW_CLK1_FREQ {40000000} \
    CONFIG.PCW_CLK2_FREQ {166666672} \
    CONFIG.PCW_CLK3_FREQ {200000000} \
-   CONFIG.PCW_CPU_CPU_PLL_FREQMHZ {1333.333} \
+   CONFIG.PCW_CPU_CPU_PLL_FREQMHZ {1733.333} \
    CONFIG.PCW_CPU_PERIPHERAL_DIVISOR0 {2} \
    CONFIG.PCW_DCI_PERIPHERAL_DIVISOR0 {15} \
    CONFIG.PCW_DCI_PERIPHERAL_DIVISOR1 {7} \
@@ -216,7 +494,7 @@ proc create_root_design { parentCell } {
    CONFIG.PCW_ENET0_GRP_MDIO_ENABLE {1} \
    CONFIG.PCW_ENET0_GRP_MDIO_IO {MIO 52 .. 53} \
    CONFIG.PCW_ENET0_PERIPHERAL_CLKSRC {IO PLL} \
-   CONFIG.PCW_ENET0_PERIPHERAL_DIVISOR0 {8} \
+   CONFIG.PCW_ENET0_PERIPHERAL_DIVISOR0 {16} \
    CONFIG.PCW_ENET0_PERIPHERAL_DIVISOR1 {1} \
    CONFIG.PCW_ENET0_PERIPHERAL_ENABLE {1} \
    CONFIG.PCW_ENET0_PERIPHERAL_FREQMHZ {1000 Mbps} \
@@ -252,13 +530,13 @@ proc create_root_design { parentCell } {
    CONFIG.PCW_EN_UART1 {1} \
    CONFIG.PCW_EN_USB0 {1} \
    CONFIG.PCW_FCLK0_PERIPHERAL_DIVISOR0 {5} \
-   CONFIG.PCW_FCLK0_PERIPHERAL_DIVISOR1 {2} \
-   CONFIG.PCW_FCLK1_PERIPHERAL_DIVISOR0 {5} \
+   CONFIG.PCW_FCLK0_PERIPHERAL_DIVISOR1 {4} \
+   CONFIG.PCW_FCLK1_PERIPHERAL_DIVISOR0 {10} \
    CONFIG.PCW_FCLK1_PERIPHERAL_DIVISOR1 {5} \
-   CONFIG.PCW_FCLK2_PERIPHERAL_DIVISOR0 {3} \
-   CONFIG.PCW_FCLK2_PERIPHERAL_DIVISOR1 {2} \
+   CONFIG.PCW_FCLK2_PERIPHERAL_DIVISOR0 {4} \
+   CONFIG.PCW_FCLK2_PERIPHERAL_DIVISOR1 {3} \
    CONFIG.PCW_FCLK3_PERIPHERAL_DIVISOR0 {5} \
-   CONFIG.PCW_FCLK3_PERIPHERAL_DIVISOR1 {1} \
+   CONFIG.PCW_FCLK3_PERIPHERAL_DIVISOR1 {2} \
    CONFIG.PCW_FCLK_CLK1_BUF {TRUE} \
    CONFIG.PCW_FCLK_CLK2_BUF {TRUE} \
    CONFIG.PCW_FCLK_CLK3_BUF {TRUE} \
@@ -284,11 +562,11 @@ proc create_root_design { parentCell } {
    CONFIG.PCW_I2C1_I2C1_IO {<Select>} \
    CONFIG.PCW_I2C1_PERIPHERAL_ENABLE {0} \
    CONFIG.PCW_I2C1_RESET_ENABLE {0} \
-   CONFIG.PCW_I2C_PERIPHERAL_FREQMHZ {111.111115} \
+   CONFIG.PCW_I2C_PERIPHERAL_FREQMHZ {144.444443} \
    CONFIG.PCW_I2C_RESET_ENABLE {0} \
    CONFIG.PCW_I2C_RESET_SELECT {<Select>} \
-   CONFIG.PCW_IOPLL_CTRL_FBDIV {30} \
-   CONFIG.PCW_IO_IO_PLL_FREQMHZ {1000.000} \
+   CONFIG.PCW_IOPLL_CTRL_FBDIV {60} \
+   CONFIG.PCW_IO_IO_PLL_FREQMHZ {2000.000} \
    CONFIG.PCW_IRQ_F2P_INTR {1} \
    CONFIG.PCW_MIO_0_DIRECTION {inout} \
    CONFIG.PCW_MIO_0_IOTYPE {LVCMOS 1.8V} \
@@ -508,7 +786,7 @@ proc create_root_design { parentCell } {
    CONFIG.PCW_MIO_9_SLEW {slow} \
    CONFIG.PCW_MIO_TREE_PERIPHERALS {GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#USB Reset#GPIO#ENET Reset#GPIO#GPIO#UART 0#UART 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#SD 0#SD 0#SD 0#SD 0#SD 0#SD 0#I2C 0#I2C 0#UART 1#UART 1#GPIO#GPIO#Enet 0#Enet 0} \
    CONFIG.PCW_MIO_TREE_SIGNALS {gpio[0]#gpio[1]#gpio[2]#gpio[3]#gpio[4]#gpio[5]#gpio[6]#gpio[7]#gpio[8]#reset#gpio[10]#reset#gpio[12]#gpio[13]#rx#tx#tx_clk#txd[0]#txd[1]#txd[2]#txd[3]#tx_ctl#rx_clk#rxd[0]#rxd[1]#rxd[2]#rxd[3]#rx_ctl#data[4]#dir#stp#nxt#data[0]#data[1]#data[2]#data[3]#clk#data[5]#data[6]#data[7]#clk#cmd#data[0]#data[1]#data[2]#data[3]#scl#sda#tx#rx#gpio[50]#gpio[51]#mdc#mdio} \
-   CONFIG.PCW_PCAP_PERIPHERAL_DIVISOR0 {5} \
+   CONFIG.PCW_PCAP_PERIPHERAL_DIVISOR0 {10} \
    CONFIG.PCW_PJTAG_PERIPHERAL_ENABLE {0} \
    CONFIG.PCW_PJTAG_PJTAG_IO {<Select>} \
    CONFIG.PCW_PRESET_BANK0_VOLTAGE {LVCMOS 1.8V} \
@@ -519,7 +797,7 @@ proc create_root_design { parentCell } {
    CONFIG.PCW_SD0_GRP_WP_ENABLE {0} \
    CONFIG.PCW_SD0_PERIPHERAL_ENABLE {1} \
    CONFIG.PCW_SD0_SD0_IO {MIO 40 .. 45} \
-   CONFIG.PCW_SDIO_PERIPHERAL_DIVISOR0 {10} \
+   CONFIG.PCW_SDIO_PERIPHERAL_DIVISOR0 {20} \
    CONFIG.PCW_SDIO_PERIPHERAL_FREQMHZ {100} \
    CONFIG.PCW_SDIO_PERIPHERAL_VALID {1} \
    CONFIG.PCW_SMC_PERIPHERAL_DIVISOR0 {1} \
@@ -539,7 +817,7 @@ proc create_root_design { parentCell } {
    CONFIG.PCW_SPI1_GRP_SS2_IO {EMIO} \
    CONFIG.PCW_SPI1_PERIPHERAL_ENABLE {1} \
    CONFIG.PCW_SPI1_SPI1_IO {EMIO} \
-   CONFIG.PCW_SPI_PERIPHERAL_DIVISOR0 {6} \
+   CONFIG.PCW_SPI_PERIPHERAL_DIVISOR0 {12} \
    CONFIG.PCW_SPI_PERIPHERAL_FREQMHZ {166.666666} \
    CONFIG.PCW_SPI_PERIPHERAL_VALID {1} \
    CONFIG.PCW_TPIU_PERIPHERAL_DIVISOR0 {1} \
@@ -549,7 +827,7 @@ proc create_root_design { parentCell } {
    CONFIG.PCW_UART1_GRP_FULL_ENABLE {0} \
    CONFIG.PCW_UART1_PERIPHERAL_ENABLE {1} \
    CONFIG.PCW_UART1_UART1_IO {MIO 48 .. 49} \
-   CONFIG.PCW_UART_PERIPHERAL_DIVISOR0 {10} \
+   CONFIG.PCW_UART_PERIPHERAL_DIVISOR0 {20} \
    CONFIG.PCW_UART_PERIPHERAL_FREQMHZ {100} \
    CONFIG.PCW_UART_PERIPHERAL_VALID {1} \
    CONFIG.PCW_UIPARAM_ACT_DDR_FREQ_MHZ {533.333374} \
@@ -586,7 +864,7 @@ proc create_root_design { parentCell } {
    CONFIG.PCW_USE_FABRIC_INTERRUPT {1} \
    CONFIG.PCW_USE_HIGH_OCM {1} \
    CONFIG.PCW_USE_PS_SLCR_REGISTERS {1} \
-   CONFIG.PCW_USE_S_AXI_GP0 {0} \
+   CONFIG.PCW_USE_S_AXI_GP0 {1} \
    CONFIG.PCW_USE_S_AXI_GP1 {0} \
    CONFIG.PCW_USE_S_AXI_HP0 {0} \
    CONFIG.PCW_USE_S_AXI_HP1 {1} \
@@ -594,6 +872,12 @@ proc create_root_design { parentCell } {
    CONFIG.PCW_USE_S_AXI_HP3 {0} \
  ] $processing_system7_0
 
+  # Create instance: smartconnect_dma, and set properties
+  set smartconnect_dma [ create_bd_cell -type ip -vlnv xilinx.com:ip:smartconnect:1.0 smartconnect_dma ]
+  set_property -dict [ list \
+   CONFIG.NUM_SI {1} \
+ ] $smartconnect_dma
+
   # Create instance: xlconcat_0, and set properties
   set xlconcat_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 xlconcat_0 ]
   set_property -dict [ list \
@@ -613,17 +897,18 @@ proc create_root_design { parentCell } {
   # Create interface connections
   connect_bd_intf_net -intf_net S00_AXI_1 [get_bd_intf_pins axi_interconnect_0/S00_AXI] [get_bd_intf_pins processing_system7_0/M_AXI_GP0]
   connect_bd_intf_net -intf_net axi_interconnect_0_M00_AXI [get_bd_intf_ports m_axi_xbar] [get_bd_intf_pins axi_interconnect_0/M00_AXI]
-  connect_bd_intf_net -intf_net axi_interconnect_0_M03_AXI [get_bd_intf_pins axi_interconnect_0/M03_AXI] [get_bd_intf_pins dma/s_axi_tx_dmac]
   connect_bd_intf_net -intf_net axi_interconnect_0_M01_AXI [get_bd_intf_ports m_axi_pmu] [get_bd_intf_pins axi_interconnect_0/M01_AXI]
+  connect_bd_intf_net -intf_net axi_interconnect_0_M02_AXI [get_bd_intf_pins axi_interconnect_0/M02_AXI] [get_bd_intf_pins dma/s_axi_dmac]
+  connect_bd_intf_net -intf_net axi_interconnect_0_M03_AXI [get_bd_intf_ports m_axi_eth_internal] [get_bd_intf_pins axi_interconnect_0/M03_AXI]
+  connect_bd_intf_net -intf_net dma_M_AXI_DMA_SG [get_bd_intf_pins dma/M_AXI_DMA_SG] [get_bd_intf_pins smartconnect_dma/S00_AXI]
   connect_bd_intf_net -intf_net dma_M_AXI_RX_DMA [get_bd_intf_pins dma/M_AXI_RX_DMA] [get_bd_intf_pins processing_system7_0/S_AXI_HP1]
   connect_bd_intf_net -intf_net dma_M_AXI_TX_DMA [get_bd_intf_pins dma/M_AXI_TX_DMA] [get_bd_intf_pins processing_system7_0/S_AXI_HP2]
-  connect_bd_intf_net -intf_net s_axis_dma_1 [get_bd_intf_ports s_axis_dma] [get_bd_intf_pins dma/s_axis_dma]
   connect_bd_intf_net -intf_net m_axis_dma_1 [get_bd_intf_ports m_axis_dma] [get_bd_intf_pins dma/m_axis_dma]
   connect_bd_intf_net -intf_net processing_system7_0_DDR [get_bd_intf_ports DDR] [get_bd_intf_pins processing_system7_0/DDR]
   connect_bd_intf_net -intf_net processing_system7_0_GPIO_0 [get_bd_intf_ports GPIO_0] [get_bd_intf_pins processing_system7_0/GPIO_0]
   connect_bd_intf_net -intf_net processing_system7_0_USBIND_0 [get_bd_intf_ports USBIND_0] [get_bd_intf_pins processing_system7_0/USBIND_0]
-  connect_bd_intf_net -intf_net s_axi_regfile_1 [get_bd_intf_pins axi_interconnect_0/M04_AXI] [get_bd_intf_pins dma/s_axi_regfile]
-  connect_bd_intf_net -intf_net s_axi_rx_dmac_1 [get_bd_intf_pins axi_interconnect_0/M02_AXI] [get_bd_intf_pins dma/s_axi_rx_dmac]
+  connect_bd_intf_net -intf_net s_axis_dma_1 [get_bd_intf_ports s_axis_dma] [get_bd_intf_pins dma/s_axis_dma]
+  connect_bd_intf_net -intf_net smartconnect_dma_M00_AXI [get_bd_intf_pins processing_system7_0/S_AXI_GP0] [get_bd_intf_pins smartconnect_dma/M00_AXI]
 
   # Create port connections
   connect_bd_net -net IRQ_F2P_1 [get_bd_ports IRQ_F2P] [get_bd_pins xlslice_2/Din]
@@ -637,10 +922,10 @@ proc create_root_design { parentCell } {
   connect_bd_net -net SPI1_SS_I_0_1 [get_bd_ports SPI1_SS_I] [get_bd_pins processing_system7_0/SPI1_SS_I]
   connect_bd_net -net S_AXI_GP0_ACLK_1 [get_bd_ports S_AXI_GP0_ACLK] [get_bd_pins axi_interconnect_0/ACLK]
   connect_bd_net -net S_AXI_GP0_ARESETN_1 [get_bd_ports S_AXI_GP0_ARESETN] [get_bd_pins axi_interconnect_0/ARESETN]
-  connect_bd_net -net bus_clk [get_bd_ports bus_clk] [get_bd_pins dma/bus_clk]
-  connect_bd_net -net bus_rstn [get_bd_ports bus_rstn] [get_bd_pins dma/bus_rstn]
-  connect_bd_net -net clk40 [get_bd_ports clk40] [get_bd_pins axi_interconnect_0/M00_ACLK] [get_bd_pins axi_interconnect_0/M02_ACLK] [get_bd_pins axi_interconnect_0/M03_ACLK] [get_bd_pins axi_interconnect_0/M04_ACLK] [get_bd_pins axi_interconnect_0/M01_ACLK] [get_bd_pins axi_interconnect_0/S00_ACLK] [get_bd_pins dma/clk40] [get_bd_pins processing_system7_0/M_AXI_GP0_ACLK] [get_bd_pins processing_system7_0/S_AXI_HP1_ACLK] [get_bd_pins processing_system7_0/S_AXI_HP2_ACLK]
-  connect_bd_net -net clk40_rstn [get_bd_ports clk40_rstn] [get_bd_pins axi_interconnect_0/M00_ARESETN] [get_bd_pins axi_interconnect_0/M02_ARESETN] [get_bd_pins axi_interconnect_0/M03_ARESETN] [get_bd_pins axi_interconnect_0/M04_ARESETN] [get_bd_pins axi_interconnect_0/M01_ARESETN] [get_bd_pins axi_interconnect_0/S00_ARESETN] [get_bd_pins dma/clk40_rstn]
+  connect_bd_net -net bus_clk [get_bd_ports bus_clk] [get_bd_pins dma/bus_clk] [get_bd_pins processing_system7_0/S_AXI_GP0_ACLK] [get_bd_pins processing_system7_0/S_AXI_HP1_ACLK] [get_bd_pins processing_system7_0/S_AXI_HP2_ACLK] [get_bd_pins smartconnect_dma/aclk]
+  connect_bd_net -net bus_rstn [get_bd_ports bus_rstn] [get_bd_pins dma/bus_rstn] [get_bd_pins smartconnect_dma/aresetn]
+  connect_bd_net -net clk40_1 [get_bd_ports clk40] [get_bd_pins axi_interconnect_0/M00_ACLK] [get_bd_pins axi_interconnect_0/M01_ACLK] [get_bd_pins axi_interconnect_0/M02_ACLK] [get_bd_pins axi_interconnect_0/M03_ACLK] [get_bd_pins axi_interconnect_0/S00_ACLK] [get_bd_pins dma/clk40] [get_bd_pins processing_system7_0/M_AXI_GP0_ACLK]
+  connect_bd_net -net clk40_rstn [get_bd_ports clk40_rstn] [get_bd_pins axi_interconnect_0/M00_ARESETN] [get_bd_pins axi_interconnect_0/M01_ARESETN] [get_bd_pins axi_interconnect_0/M02_ARESETN] [get_bd_pins axi_interconnect_0/M03_ARESETN] [get_bd_pins axi_interconnect_0/S00_ARESETN] [get_bd_pins dma/clk40_rstn]
   connect_bd_net -net ddr_vrn [get_bd_ports DDR_VRN] [get_bd_pins processing_system7_0/DDR_VRN]
   connect_bd_net -net ddr_vrp [get_bd_ports DDR_VRP] [get_bd_pins processing_system7_0/DDR_VRP]
   connect_bd_net -net dma_tx_irq [get_bd_pins dma/tx_irq] [get_bd_pins xlconcat_0/In2]
@@ -678,34 +963,33 @@ proc create_root_design { parentCell } {
   connect_bd_net -net xlslice_2_Dout [get_bd_pins xlconcat_0/In0] [get_bd_pins xlslice_2/Dout]
 
   # Create address segments
-  create_bd_addr_seg -range 0x00004000 -offset 0x40010000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs m_axi_xbar/Reg] SEG_m_axi_xbar_Reg
-  create_bd_addr_seg -range 0x00001000 -offset 0x42080000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs dma/axi_regfile_0/S_AXI/regs] SEG_axi_regfile_0_regs
-  create_bd_addr_seg -range 0x00010000 -offset 0x43C00000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs dma/rx/dma0/axi_rx_dmac/s_axi/axi_lite] SEG_axi_rx_dmac_axi_lite
-  create_bd_addr_seg -range 0x00010000 -offset 0x43C10000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs dma/rx/dma1/axi_rx_dmac/s_axi/axi_lite] SEG_axi_rx_dmac_axi_lite1
-  create_bd_addr_seg -range 0x00010000 -offset 0x43C20000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs dma/rx/dma2/axi_rx_dmac/s_axi/axi_lite] SEG_axi_rx_dmac_axi_lite2
-  create_bd_addr_seg -range 0x00010000 -offset 0x43C30000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs dma/rx/dma3/axi_rx_dmac/s_axi/axi_lite] SEG_axi_rx_dmac_axi_lite3
-  create_bd_addr_seg -range 0x00010000 -offset 0x43C40000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs dma/rx/dma4/axi_rx_dmac/s_axi/axi_lite] SEG_axi_rx_dmac_axi_lite4
-  create_bd_addr_seg -range 0x00010000 -offset 0x43CA0000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs dma/tx/axi_tx_dmac_0/s_axi/axi_lite] SEG_axi_tx_dmac_0_axi_lite
-  create_bd_addr_seg -range 0x00010000 -offset 0x43CB0000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs dma/tx/axi_tx_dmac_1/s_axi/axi_lite] SEG_axi_tx_dmac_1_axi_lite
-  create_bd_addr_seg -range 0x00010000 -offset 0x43CC0000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs dma/tx/axi_tx_dmac_2/s_axi/axi_lite] SEG_axi_tx_dmac_2_axi_lite
-  create_bd_addr_seg -range 0x00010000 -offset 0x43CD0000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs dma/tx/axi_tx_dmac_3/s_axi/axi_lite] SEG_axi_tx_dmac_3_axi_lite
-  create_bd_addr_seg -range 0x00010000 -offset 0x43CE0000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs dma/tx/axi_tx_dmac_4/s_axi/axi_lite] SEG_axi_tx_dmac_4_axi_lite
+  create_bd_addr_seg -range 0x00004000 -offset 0x40020000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs dma/axi_dma_eth_internal/S_AXI_LITE/Reg] SEG_axi_dma_eth_internal_Reg
+  create_bd_addr_seg -range 0x00004000 -offset 0x40030000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs m_axi_eth_internal/Reg] SEG_m_axi_eth_internal_Reg
   create_bd_addr_seg -range 0x00004000 -offset 0x40000000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs m_axi_pmu/Reg] SEG_m_axi_pmu_Reg
-  create_bd_addr_seg -range 0x40000000 -offset 0x00000000 [get_bd_addr_spaces dma/tx/axi_tx_dmac_0/m_src_axi] [get_bd_addr_segs processing_system7_0/S_AXI_HP2/HP2_DDR_LOWOCM] SEG_processing_system7_0_HP2_DDR_LOWOCM
-  create_bd_addr_seg -range 0x40000000 -offset 0x00000000 [get_bd_addr_spaces dma/tx/axi_tx_dmac_1/m_src_axi] [get_bd_addr_segs processing_system7_0/S_AXI_HP2/HP2_DDR_LOWOCM] SEG_processing_system7_0_HP2_DDR_LOWOCM
-  create_bd_addr_seg -range 0x40000000 -offset 0x00000000 [get_bd_addr_spaces dma/tx/axi_tx_dmac_2/m_src_axi] [get_bd_addr_segs processing_system7_0/S_AXI_HP2/HP2_DDR_LOWOCM] SEG_processing_system7_0_HP2_DDR_LOWOCM
-  create_bd_addr_seg -range 0x40000000 -offset 0x00000000 [get_bd_addr_spaces dma/tx/axi_tx_dmac_3/m_src_axi] [get_bd_addr_segs processing_system7_0/S_AXI_HP2/HP2_DDR_LOWOCM] SEG_processing_system7_0_HP2_DDR_LOWOCM
-  create_bd_addr_seg -range 0x40000000 -offset 0x00000000 [get_bd_addr_spaces dma/tx/axi_tx_dmac_4/m_src_axi] [get_bd_addr_segs processing_system7_0/S_AXI_HP2/HP2_DDR_LOWOCM] SEG_processing_system7_0_HP2_DDR_LOWOCM
-  create_bd_addr_seg -range 0x40000000 -offset 0x00000000 [get_bd_addr_spaces dma/rx/dma0/axi_rx_dmac/m_dest_axi] [get_bd_addr_segs processing_system7_0/S_AXI_HP1/HP1_DDR_LOWOCM] SEG_processing_system7_0_HP1_DDR_LOWOCM
-  create_bd_addr_seg -range 0x40000000 -offset 0x00000000 [get_bd_addr_spaces dma/rx/dma1/axi_rx_dmac/m_dest_axi] [get_bd_addr_segs processing_system7_0/S_AXI_HP1/HP1_DDR_LOWOCM] SEG_processing_system7_0_HP1_DDR_LOWOCM
-  create_bd_addr_seg -range 0x40000000 -offset 0x00000000 [get_bd_addr_spaces dma/rx/dma2/axi_rx_dmac/m_dest_axi] [get_bd_addr_segs processing_system7_0/S_AXI_HP1/HP1_DDR_LOWOCM] SEG_processing_system7_0_HP1_DDR_LOWOCM
-  create_bd_addr_seg -range 0x40000000 -offset 0x00000000 [get_bd_addr_spaces dma/rx/dma3/axi_rx_dmac/m_dest_axi] [get_bd_addr_segs processing_system7_0/S_AXI_HP1/HP1_DDR_LOWOCM] SEG_processing_system7_0_HP1_DDR_LOWOCM
-  create_bd_addr_seg -range 0x40000000 -offset 0x00000000 [get_bd_addr_spaces dma/rx/dma4/axi_rx_dmac/m_dest_axi] [get_bd_addr_segs processing_system7_0/S_AXI_HP1/HP1_DDR_LOWOCM] SEG_processing_system7_0_HP1_DDR_LOWOCM
+  create_bd_addr_seg -range 0x00004000 -offset 0x40010000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs m_axi_xbar/Reg] SEG_m_axi_xbar_Reg
+  create_bd_addr_seg -range 0x40000000 -offset 0x00000000 [get_bd_addr_spaces dma/axi_dma_eth_internal/Data_SG] [get_bd_addr_segs processing_system7_0/S_AXI_GP0/GP0_DDR_LOWOCM] SEG_processing_system7_0_GP0_DDR_LOWOCM
+  create_bd_addr_seg -range 0x00040000 -offset 0xFFFC0000 [get_bd_addr_spaces dma/axi_dma_eth_internal/Data_SG] [get_bd_addr_segs processing_system7_0/S_AXI_GP0/GP0_HIGH_OCM] SEG_processing_system7_0_GP0_HIGH_OCM
+  create_bd_addr_seg -range 0x40000000 -offset 0x00000000 [get_bd_addr_spaces dma/axi_dma_eth_internal/Data_S2MM] [get_bd_addr_segs processing_system7_0/S_AXI_HP1/HP1_DDR_LOWOCM] SEG_processing_system7_0_HP1_DDR_LOWOCM
+  create_bd_addr_seg -range 0x00040000 -offset 0xFFFC0000 [get_bd_addr_spaces dma/axi_dma_eth_internal/Data_S2MM] [get_bd_addr_segs processing_system7_0/S_AXI_HP1/HP1_HIGH_OCM] SEG_processing_system7_0_HP1_HIGH_OCM
+  create_bd_addr_seg -range 0x40000000 -offset 0x00000000 [get_bd_addr_spaces dma/axi_dma_eth_internal/Data_MM2S] [get_bd_addr_segs processing_system7_0/S_AXI_HP2/HP2_DDR_LOWOCM] SEG_processing_system7_0_HP2_DDR_LOWOCM
+  create_bd_addr_seg -range 0x00040000 -offset 0xFFFC0000 [get_bd_addr_spaces dma/axi_dma_eth_internal/Data_MM2S] [get_bd_addr_segs processing_system7_0/S_AXI_HP2/HP2_HIGH_OCM] SEG_processing_system7_0_HP2_HIGH_OCM
+
+  # Exclude Address Segments
+  create_bd_addr_seg -range 0x00400000 -offset 0xE0000000 [get_bd_addr_spaces dma/axi_dma_eth_internal/Data_SG] [get_bd_addr_segs processing_system7_0/S_AXI_GP0/GP0_IOP] SEG_processing_system7_0_GP0_IOP
+  exclude_bd_addr_seg [get_bd_addr_segs dma/axi_dma_eth_internal/Data_SG/SEG_processing_system7_0_GP0_IOP]
+
+  create_bd_addr_seg -range 0x40000000 -offset 0x40000000 [get_bd_addr_spaces dma/axi_dma_eth_internal/Data_SG] [get_bd_addr_segs processing_system7_0/S_AXI_GP0/GP0_M_AXI_GP0] SEG_processing_system7_0_GP0_M_AXI_GP0
+  exclude_bd_addr_seg [get_bd_addr_segs dma/axi_dma_eth_internal/Data_SG/SEG_processing_system7_0_GP0_M_AXI_GP0]
+
+  create_bd_addr_seg -range 0x00010000 -offset 0xF8000000 [get_bd_addr_spaces dma/axi_dma_eth_internal/Data_SG] [get_bd_addr_segs processing_system7_0/S_AXI_GP0/GP0_PS_SLCR_REGS] SEG_processing_system7_0_GP0_PS_SLCR_REGS
+  exclude_bd_addr_seg [get_bd_addr_segs dma/axi_dma_eth_internal/Data_SG/SEG_processing_system7_0_GP0_PS_SLCR_REGS]
+
 
 
   # Restore current instance
   current_bd_instance $oldCurInst
 
+  validate_bd_design
   save_bd_design
 }
 # End of create_root_design()