fpga: Updating FPGA code for UHD-3.7.2-rc1

author: Ben Hilburn <ben.hilburn@ettus.com> 2014-07-22 15:49:02 -0700
committer: Ben Hilburn <ben.hilburn@ettus.com> 2014-07-22 15:49:02 -0700
commit: b63507efb3cf1a8fa20794c452d57028e18da182 (patch)
tree: 13f6ec6c3098dff29a3fb50ff3c70bc4d22e7e32 /fpga/usrp3/top
parent: 7911d3e2e90672f44eafc635208053fe75ff19d9 (diff)
download: uhd-b63507efb3cf1a8fa20794c452d57028e18da182.tar.gz
uhd-b63507efb3cf1a8fa20794c452d57028e18da182.tar.bz2
uhd-b63507efb3cf1a8fa20794c452d57028e18da182.zip
54 files changed, 3101 insertions, 3107 deletions
diff --git a/fpga/usrp3/top/b200/b200_core.v b/fpga/usrp3/top/b200/b200_core.v
index 016037688..dc8baba4f 100644
--- a/fpga/usrp3/top/b200/b200_core.v
+++ b/fpga/usrp3/top/b200/b200_core.v
@@ -1,5 +1,5 @@
 //
-// Copyright 2013 Ettus Research LLC
+// Copyright 2013-14 Ettus Research LLC
 //
 
 
@@ -78,11 +78,24 @@ module b200_core
     /*******************************************************************
      * PPS Timing stuff
      ******************************************************************/
-    reg [1:0] 	 int_pps_del, ext_pps_del;
+
+    // Generate an internal PPS signal
+    wire int_pps;
+    pps_generator #(.CLK_FREQ(100000000)) pps_gen
+    (.clk(bus_clk), .pps(int_pps));
+
+    // Flop PPS signals into radio clock domain
+    reg [1:0] 	 gpsdo_pps_del, ext_pps_del, int_pps_del;
     always @(posedge radio_clk) ext_pps_del[1:0] <= {ext_pps_del[0], pps_ext};
-    always @(posedge radio_clk) int_pps_del[1:0] <= {int_pps_del[0], pps_int};
-    wire pps_select;
-    wire pps = pps_select? ext_pps_del[1] : int_pps_del[1];
+    always @(posedge radio_clk) gpsdo_pps_del[1:0] <= {gpsdo_pps_del[0], pps_int};
+    always @(posedge radio_clk) int_pps_del[1:0] <= {int_pps_del[0], int_pps};
+
+    // PPS mux
+    wire [1:0] pps_select;
+    wire pps =  (pps_select == 2'b00)? gpsdo_pps_del[1] :
+                (pps_select == 2'b01)? ext_pps_del[1] :
+                (pps_select == 2'b10)? int_pps_del[1] :
+                1'b0;
 
     /*******************************************************************
      * Response mux Routing logic
@@ -189,7 +202,7 @@ module b200_core
      (.clk(bus_clk), .rst(1'b0/*keep*/), .strobe(set_stb), .addr(set_addr), .in(set_data),
       .out(gpsdo_st), .changed());
 
-    setting_reg #(.my_addr(SR_CORE_PPS_SEL), .awidth(8), .width(1)) sr_pps_sel
+    setting_reg #(.my_addr(SR_CORE_PPS_SEL), .awidth(8), .width(2)) sr_pps_sel
      (.clk(bus_clk), .rst(bus_rst), .strobe(set_stb), .addr(set_addr), .in(set_data),
       .out(pps_select), .changed());
 
diff --git a/fpga/usrp3/top/b200/coregen/chipscope_icon.gise b/fpga/usrp3/top/b200/coregen/chipscope_icon.gise
index a4f878755..29d14a154 100644
--- a/fpga/usrp3/top/b200/coregen/chipscope_icon.gise
+++ b/fpga/usrp3/top/b200/coregen/chipscope_icon.gise
@@ -15,7 +15,7 @@
 
   <!--                                                          -->
 
-  <!-- Copyright (c) 1995-2012 Xilinx, Inc.  All rights reserved. -->
+  <!-- Copyright (c) 1995-2013 Xilinx, Inc.  All rights reserved. -->
 
   <version xmlns="http://www.xilinx.com/XMLSchema">11.1</version>
 
diff --git a/fpga/usrp3/top/b200/coregen/chipscope_icon.xise b/fpga/usrp3/top/b200/coregen/chipscope_icon.xise
index 669cbf101..5cb07142c 100644
--- a/fpga/usrp3/top/b200/coregen/chipscope_icon.xise
+++ b/fpga/usrp3/top/b200/coregen/chipscope_icon.xise
@@ -9,10 +9,10 @@
     <!-- along with the project source files, is sufficient to open and    -->
     <!-- implement in ISE Project Navigator.                               -->
     <!--                                                                   -->
-    <!-- Copyright (c) 1995-2012 Xilinx, Inc.  All rights reserved. -->
+    <!-- Copyright (c) 1995-2013 Xilinx, Inc.  All rights reserved. -->
   </header>
 
-  <version xil_pn:ise_version="14.4" xil_pn:schema_version="2"/>
+  <version xil_pn:ise_version="14.6" xil_pn:schema_version="2"/>
 
   <files>
     <file xil_pn:name="chipscope_icon.ngc" xil_pn:type="FILE_NGC">
diff --git a/fpga/usrp3/top/b200/coregen/chipscope_ila_128.gise b/fpga/usrp3/top/b200/coregen/chipscope_ila_128.gise
index 3af396d70..8f50adfb5 100644
--- a/fpga/usrp3/top/b200/coregen/chipscope_ila_128.gise
+++ b/fpga/usrp3/top/b200/coregen/chipscope_ila_128.gise
@@ -15,7 +15,7 @@
 
   <!--                                                          -->
 
-  <!-- Copyright (c) 1995-2012 Xilinx, Inc.  All rights reserved. -->
+  <!-- Copyright (c) 1995-2013 Xilinx, Inc.  All rights reserved. -->
 
   <version xmlns="http://www.xilinx.com/XMLSchema">11.1</version>
 
diff --git a/fpga/usrp3/top/b200/coregen/chipscope_ila_128.xise b/fpga/usrp3/top/b200/coregen/chipscope_ila_128.xise
index 3bc65beca..d89d10530 100644
--- a/fpga/usrp3/top/b200/coregen/chipscope_ila_128.xise
+++ b/fpga/usrp3/top/b200/coregen/chipscope_ila_128.xise
@@ -9,10 +9,10 @@
     <!-- along with the project source files, is sufficient to open and    -->
     <!-- implement in ISE Project Navigator.                               -->
     <!--                                                                   -->
-    <!-- Copyright (c) 1995-2012 Xilinx, Inc.  All rights reserved. -->
+    <!-- Copyright (c) 1995-2013 Xilinx, Inc.  All rights reserved. -->
   </header>
 
-  <version xil_pn:ise_version="14.4" xil_pn:schema_version="2"/>
+  <version xil_pn:ise_version="14.6" xil_pn:schema_version="2"/>
 
   <files>
     <file xil_pn:name="chipscope_ila_128.ngc" xil_pn:type="FILE_NGC">
diff --git a/fpga/usrp3/top/b200/coregen/chipscope_ila_256.gise b/fpga/usrp3/top/b200/coregen/chipscope_ila_256.gise
index 6305e6288..85cc00a94 100644
--- a/fpga/usrp3/top/b200/coregen/chipscope_ila_256.gise
+++ b/fpga/usrp3/top/b200/coregen/chipscope_ila_256.gise
@@ -15,7 +15,7 @@
 
   <!--                                                          -->
 
-  <!-- Copyright (c) 1995-2012 Xilinx, Inc.  All rights reserved. -->
+  <!-- Copyright (c) 1995-2013 Xilinx, Inc.  All rights reserved. -->
 
   <version xmlns="http://www.xilinx.com/XMLSchema">11.1</version>
 
diff --git a/fpga/usrp3/top/b200/coregen/chipscope_ila_256.xise b/fpga/usrp3/top/b200/coregen/chipscope_ila_256.xise
index f8c51bac1..a9e75da04 100644
--- a/fpga/usrp3/top/b200/coregen/chipscope_ila_256.xise
+++ b/fpga/usrp3/top/b200/coregen/chipscope_ila_256.xise
@@ -9,10 +9,10 @@
     <!-- along with the project source files, is sufficient to open and    -->
     <!-- implement in ISE Project Navigator.                               -->
     <!--                                                                   -->
-    <!-- Copyright (c) 1995-2012 Xilinx, Inc.  All rights reserved. -->
+    <!-- Copyright (c) 1995-2013 Xilinx, Inc.  All rights reserved. -->
   </header>
 
-  <version xil_pn:ise_version="14.4" xil_pn:schema_version="2"/>
+  <version xil_pn:ise_version="14.6" xil_pn:schema_version="2"/>
 
   <files>
     <file xil_pn:name="chipscope_ila_256.ngc" xil_pn:type="FILE_NGC">
diff --git a/fpga/usrp3/top/b200/coregen/chipscope_ila_32.gise b/fpga/usrp3/top/b200/coregen/chipscope_ila_32.gise
index 4bc01d034..e5487e74a 100644
--- a/fpga/usrp3/top/b200/coregen/chipscope_ila_32.gise
+++ b/fpga/usrp3/top/b200/coregen/chipscope_ila_32.gise
@@ -15,7 +15,7 @@
 
   <!--                                                          -->
 
-  <!-- Copyright (c) 1995-2012 Xilinx, Inc.  All rights reserved. -->
+  <!-- Copyright (c) 1995-2013 Xilinx, Inc.  All rights reserved. -->
 
   <version xmlns="http://www.xilinx.com/XMLSchema">11.1</version>
 
diff --git a/fpga/usrp3/top/b200/coregen/chipscope_ila_32.xise b/fpga/usrp3/top/b200/coregen/chipscope_ila_32.xise
index 9a9fb9459..8d210d750 100644
--- a/fpga/usrp3/top/b200/coregen/chipscope_ila_32.xise
+++ b/fpga/usrp3/top/b200/coregen/chipscope_ila_32.xise
@@ -9,10 +9,10 @@
     <!-- along with the project source files, is sufficient to open and    -->
     <!-- implement in ISE Project Navigator.                               -->
     <!--                                                                   -->
-    <!-- Copyright (c) 1995-2012 Xilinx, Inc.  All rights reserved. -->
+    <!-- Copyright (c) 1995-2013 Xilinx, Inc.  All rights reserved. -->
   </header>
 
-  <version xil_pn:ise_version="14.4" xil_pn:schema_version="2"/>
+  <version xil_pn:ise_version="14.6" xil_pn:schema_version="2"/>
 
   <files>
     <file xil_pn:name="chipscope_ila_32.ngc" xil_pn:type="FILE_NGC">
diff --git a/fpga/usrp3/top/b200/coregen/fifo_4k_2clk.gise b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk.gise
index c631a4815..ae7343223 100644
--- a/fpga/usrp3/top/b200/coregen/fifo_4k_2clk.gise
+++ b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk.gise
@@ -15,7 +15,7 @@
 
   <!--                                                          -->
 
-  <!-- Copyright (c) 1995-2012 Xilinx, Inc.  All rights reserved. -->
+  <!-- Copyright (c) 1995-2013 Xilinx, Inc.  All rights reserved. -->
 
   <version xmlns="http://www.xilinx.com/XMLSchema">11.1</version>
 
diff --git a/fpga/usrp3/top/b200/coregen/fifo_4k_2clk.xise b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk.xise
index 2d8132c10..951b199cf 100644
--- a/fpga/usrp3/top/b200/coregen/fifo_4k_2clk.xise
+++ b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk.xise
@@ -9,10 +9,10 @@
     <!-- along with the project source files, is sufficient to open and    -->
     <!-- implement in ISE Project Navigator.                               -->
     <!--                                                                   -->
-    <!-- Copyright (c) 1995-2012 Xilinx, Inc.  All rights reserved. -->
+    <!-- Copyright (c) 1995-2013 Xilinx, Inc.  All rights reserved. -->
   </header>
 
-  <version xil_pn:ise_version="14.4" xil_pn:schema_version="2"/>
+  <version xil_pn:ise_version="14.6" xil_pn:schema_version="2"/>
 
   <files>
     <file xil_pn:name="fifo_4k_2clk.ngc" xil_pn:type="FILE_NGC">
diff --git a/fpga/usrp3/top/b200/coregen/fifo_short_2clk.gise b/fpga/usrp3/top/b200/coregen/fifo_short_2clk.gise
index ea47d0f4b..ddb581fc1 100644
--- a/fpga/usrp3/top/b200/coregen/fifo_short_2clk.gise
+++ b/fpga/usrp3/top/b200/coregen/fifo_short_2clk.gise
@@ -15,7 +15,7 @@
 
   <!--                                                          -->
 
-  <!-- Copyright (c) 1995-2012 Xilinx, Inc.  All rights reserved. -->
+  <!-- Copyright (c) 1995-2013 Xilinx, Inc.  All rights reserved. -->
 
   <version xmlns="http://www.xilinx.com/XMLSchema">11.1</version>
 
diff --git a/fpga/usrp3/top/b200/coregen/fifo_short_2clk.xise b/fpga/usrp3/top/b200/coregen/fifo_short_2clk.xise
index 1ca7d35ee..1f72b185a 100644
--- a/fpga/usrp3/top/b200/coregen/fifo_short_2clk.xise
+++ b/fpga/usrp3/top/b200/coregen/fifo_short_2clk.xise
@@ -9,10 +9,10 @@
     <!-- along with the project source files, is sufficient to open and    -->
     <!-- implement in ISE Project Navigator.                               -->
     <!--                                                                   -->
-    <!-- Copyright (c) 1995-2012 Xilinx, Inc.  All rights reserved. -->
+    <!-- Copyright (c) 1995-2013 Xilinx, Inc.  All rights reserved. -->
   </header>
 
-  <version xil_pn:ise_version="14.4" xil_pn:schema_version="2"/>
+  <version xil_pn:ise_version="14.6" xil_pn:schema_version="2"/>
 
   <files>
     <file xil_pn:name="fifo_short_2clk.ngc" xil_pn:type="FILE_NGC">
diff --git a/fpga/usrp3/top/x300/Makefile b/fpga/usrp3/top/x300/Makefile
index a5a0b22c8..dbe3bdd55 100644
--- a/fpga/usrp3/top/x300/Makefile
+++ b/fpga/usrp3/top/x300/Makefile
@@ -83,10 +83,10 @@ X310_HGS:
 	$(call post_build,X310,HGS)
 
 X300_HGS:
-	make -f Makefile.x300.inc bin NAME=$@ DEVICE=XC7K325T $(HYBRID_SRAM_DEFS) EXTRA_DEFS="$(HYBRID_SRAM_DEFS)"
+	make -f Makefile.x300.inc bin NAME=$@ DEVICE=XC7K325T FLOORPLAN=1 $(HYBRID_SRAM_DEFS) EXTRA_DEFS="$(HYBRID_SRAM_DEFS)"
 	$(call post_build,X300,HGS)
 
-# 1Gig on both ports, SRAM Tx FIFO's
+# 10Gig on both ports, SRAM Tx FIFO's
 X310_XGS: 
 	make -f Makefile.x300.inc bin NAME=$@ DEVICE=XC7K410T $(XGIGE_SRAM_DEFS) EXTRA_DEFS="$(XGIGE_SRAM_DEFS)"
 	$(call post_build,X310,XGS)
diff --git a/fpga/usrp3/top/x300/coregen/axi_intercon_2x64_128.gise b/fpga/usrp3/top/x300/coregen/axi_intercon_2x64_128.gise
index a0a0f007e..0712f3aec 100644
--- a/fpga/usrp3/top/x300/coregen/axi_intercon_2x64_128.gise
+++ b/fpga/usrp3/top/x300/coregen/axi_intercon_2x64_128.gise
@@ -15,7 +15,7 @@
 
   <!--                                                          -->
 
-  <!-- Copyright (c) 1995-2012 Xilinx, Inc.  All rights reserved. -->
+  <!-- Copyright (c) 1995-2013 Xilinx, Inc.  All rights reserved. -->
 
   <version xmlns="http://www.xilinx.com/XMLSchema">11.1</version>
 
diff --git a/fpga/usrp3/top/x300/coregen/axi_intercon_2x64_128.ncf b/fpga/usrp3/top/x300/coregen/axi_intercon_2x64_128.ncf
new file mode 100644
index 000000000..3f2148f6a
--- /dev/null
+++ b/fpga/usrp3/top/x300/coregen/axi_intercon_2x64_128.ncf
@@ -0,0 +1,4 @@
+NET "*_resync*" TNM = FFS "axi_intercon_2x64_128_reset_resync";
+NET "*INTERCONNECT_ARESETN" TNM = FFS "axi_intercon_2x64_128_reset_resync";
+TIMESPEC "TS_axi_intercon_2x64_128_reset_resync" = TO "axi_intercon_2x64_128_reset_resync" TIG;
+
diff --git a/fpga/usrp3/top/x300/coregen/axi_intercon_2x64_128.xise b/fpga/usrp3/top/x300/coregen/axi_intercon_2x64_128.xise
index fb1579c69..822e58aee 100644
--- a/fpga/usrp3/top/x300/coregen/axi_intercon_2x64_128.xise
+++ b/fpga/usrp3/top/x300/coregen/axi_intercon_2x64_128.xise
@@ -9,10 +9,10 @@
     <!-- along with the project source files, is sufficient to open and    -->
     <!-- implement in ISE Project Navigator.                               -->
     <!--                                                                   -->
-    <!-- Copyright (c) 1995-2012 Xilinx, Inc.  All rights reserved. -->
+    <!-- Copyright (c) 1995-2013 Xilinx, Inc.  All rights reserved. -->
   </header>
 
-  <version xil_pn:ise_version="14.4" xil_pn:schema_version="2"/>
+  <version xil_pn:ise_version="14.6" xil_pn:schema_version="2"/>
 
   <files>
     <file xil_pn:name="axi_intercon_2x64_128/hdl/verilog/ict106_a_axi3_conv.v" xil_pn:type="FILE_VERILOG">
diff --git a/fpga/usrp3/top/x300/coregen/bootram.coe b/fpga/usrp3/top/x300/coregen/bootram.coe
index b14aa4f1e..c124e2bee 100755
--- a/fpga/usrp3/top/x300/coregen/bootram.coe
+++ b/fpga/usrp3/top/x300/coregen/bootram.coe
@@ -2,15 +2,15 @@ memory_initialization_radix=16;
 memory_initialization_vector=
 0b0b0b0b,
 82700b0b,
-8196c80c,
+8196cc0c,
 3a0b0b80,
-fec90400,
+fecc0400,
 00000000,
 00000000,
 00000000,
 80088408,
 88080b0b,
-80ff942d,
+80ff972d,
 880c840c,
 800c0400,
 00000000,
@@ -162,7 +162,7 @@ c4040000,
 00000000,
 71fc0608,
 0b0b8196,
-b4738306,
+b8738306,
 10100508,
 060b0b0b,
 88aa0400,
@@ -171,7 +171,7 @@ b4738306,
 80088408,
 88087575,
 0b0b80f5,
-ee2d5050,
+f12d5050,
 80085688,
 0c840c80,
 0c510400,
@@ -179,7 +179,7 @@ ee2d5050,
 80088408,
 88087575,
 0b0b80f7,
-a02d5050,
+a32d5050,
 80085688,
 0c840c80,
 0c510400,
@@ -209,7 +209,7 @@ a02d5050,
 00000000,
 00000000,
 810b0b0b,
-8196c40c,
+8196c80c,
 51040000,
 00000000,
 00000000,
@@ -257,7 +257,7 @@ a02d5050,
 00000000,
 00000000,
 82813f80,
-f8b53f04,
+f8b83f04,
 10101010,
 10101010,
 10101010,
@@ -280,56 +280,56 @@ fc060c51,
 0a100a53,
 72ed3851,
 51535104,
-8196c408,
-802ea438,
 8196c808,
+802ea438,
+8196cc08,
 822ebd38,
 8380800b,
 0b0b819e,
-bc0c82a0,
+c00c82a0,
 800b819e,
-c00c8290,
+c40c8290,
 800b819e,
-c40c04f8,
+c80c04f8,
 808080a4,
 0b0b0b81,
-9ebc0cf8,
+9ec00cf8,
 80808280,
-0b819ec0,
+0b819ec4,
 0cf88080,
 84800b81,
-9ec40c04,
+9ec80c04,
 80c0a880,
 8c0b0b0b,
-819ebc0c,
+819ec00c,
 80c0a880,
 940b819e,
-c00c0b0b,
-8180e80b,
-819ec40c,
+c40c0b0b,
+8180ec0b,
+819ec80c,
 04ff3d0d,
-819ec833,
+819ecc33,
 5170a738,
-8196d008,
+8196d408,
 70085252,
 70802e94,
 38841281,
-96d00c70,
-2d8196d0,
+96d40c70,
+2d8196d4,
 08700852,
 5270ee38,
 810b819e,
-c834833d,
+cc34833d,
 0d040480,
 3d0d0b0b,
-819eb808,
+819ebc08,
 802e8e38,
 0b0b0b0b,
 800b802e,
 09810685,
 38823d0d,
 040b0b81,
-9eb8510b,
+9ebc510b,
 0b0bf5d4,
 3f823d0d,
 0404f93d,
@@ -357,57 +357,57 @@ b1387218,
 04e23d0d,
 8ba65283,
 fa805198,
-813f8ba6,
+843f8ba6,
 5283f280,
-5197f73f,
+5197fa3f,
 8b885280,
-51a2a63f,
+51a2a93f,
 81a65281,
-80f051a2,
-a73f80cf,
+80f451a2,
+aa3f80cf,
 bcc3ab52,
 83fc8051,
-989d3f80,
+98a03f80,
 cfbcc3ab,
 5283fe80,
-5198903f,
+5198933f,
 80cfbcc3,
 ab5283f8,
-80519883,
+80519886,
 3f810b82,
 c0840c82,
 c0900855,
 8a567481,
 2e833881,
 56755281,
-819c51a1,
-e33f82c0,
+81a051a1,
+e63f82c0,
 9408558a,
 5674812e,
 83388156,
 75528181,
-b451a1cc,
+b851a1cf,
 3fbffc53,
 82808052,
-819ecc51,
-a2e33f81,
-9ecc0852,
-8181cc51,
-a1b23f81,
-9ecc51a7,
-ad3f80e6,
-be3f8d3d,
+819ed051,
+a2e63f81,
+9ed00852,
+8181d051,
+a1b53f81,
+9ed051a7,
+b03f80e6,
+c13f8d3d,
 5b80cc53,
-8196d452,
+8196d852,
 7a5180ee,
-9d3f8254,
-8180ec53,
+a03f8254,
+8180f053,
 80d05283,
 fe805198,
-d43f80cc,
+d73f80cc,
 547a5380,
 d05283fe,
-805197ac,
+805197af,
 3f82c090,
 08558257,
 74833874,
@@ -415,36 +415,36 @@ d05283fe,
 0855835c,
 74833881,
 5c865381,
-96dc52a0,
+96e052a0,
 3dffbc05,
 51fdab3f,
 80085686,
-538196e4,
+538196e8,
 52a03dc4,
 0551fd9a,
 3f800858,
 84537682,
-2b819780,
+2b819784,
 1153701c,
 ac115358,
 55fd833f,
 80085a84,
-538196f0,
+538196f4,
 15529c17,
 51fcf33f,
 80085984,
 537b822b,
-81978011,
+81978411,
 53701cac,
 11535855,
 fcdc3f80,
 085b8453,
-8196f015,
+8196f415,
 529c1751,
 fccc3f80,
 0879557a,
 54765357,
-8051a686,
+8051a689,
 3f841633,
 85173371,
 882b0783,
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-38727081,
-05543374,
-70810556,
-34ff1252,
-71ff2e09,
-8106ea38,
-74800c86,
-3d0d0474,
-51727084,
-05540871,
-70840553,
-0c727084,
-05540871,
-70840553,
-0c727084,
-05540871,
-70840553,
-0c727084,
-05540871,
-70840553,
-0cf01252,
-718f26c9,
-38837227,
-95387270,
-84055408,
-71708405,
-530cfc12,
-52718326,
-ed387054,
-ff8339fa,
-3d0d787a,
-7c727272,
-57575759,
-56567476,
-27b23876,
-15517571,
-27aa3870,
-7717ff14,
-54555371,
-ff2e9638,
-ff14ff14,
-54547233,
-7434ff12,
+318c0888,
+050c8c08,
+f805088c,
+08fc0508,
+078c08f8,
+050c8c08,
+fc050881,
+2a8c08fc,
+050c8c08,
+8c050881,
+2a8c088c,
+050cffaf,
+398c0890,
+0508802e,
+8f388c08,
+88050870,
+8c08f405,
+0c518d39,
+8c08f805,
+08708c08,
+f4050c51,
+8c08f405,
+08800c85,
+3d0d8c0c,
+04fc3d0d,
+78777956,
+56528372,
+278c3874,
+74078306,
+5170802e,
+b038ff12,
 5271ff2e,
-098106ec,
-3875800c,
-883d0d04,
-768f2697,
-38ff1252,
-71ff2eed,
-38727081,
-05543374,
-70810556,
-34eb3974,
-76078306,
-5170e238,
-75755451,
+a0387433,
+74335253,
+72712e09,
+8106bd38,
+81158115,
+ff145455,
+5571ff2e,
+098106e2,
+38800b80,
+0c863d0d,
+04747454,
+51700873,
+082e0981,
+068f3884,
+118414fc,
+14545451,
+718326e9,
+38707355,
+55ffaf39,
+72713180,
+0c863d0d,
+04fc3d0d,
+7670797b,
+55555555,
+8f72278c,
+38727507,
+83065170,
+802ea738,
+ff125271,
+ff2e9838,
+72708105,
+54337470,
+81055634,
+ff125271,
+ff2e0981,
+06ea3874,
+800c863d,
+0d047451,
 72708405,
 54087170,
 8405530c,
@@ -4014,114 +3966,163 @@ f0125271,
 0cfc1252,
 718326ed,
 387054ff,
-8839fc3d,
-0d767971,
-028c059f,
-05335755,
-53558372,
-278a3874,
-83065170,
-802ea238,
+8339fa3d,
+0d787a7c,
+72727257,
+57575956,
+56747627,
+b2387615,
+51757127,
+aa387077,
+17ff1454,
+555371ff,
+2e9638ff,
+14ff1454,
+54723374,
+34ff1252,
+71ff2e09,
+8106ec38,
+75800c88,
+3d0d0476,
+8f269738,
 ff125271,
-ff2e9338,
-73737081,
-055534ff,
-125271ff,
-2e098106,
-ef387480,
-0c863d0d,
-04747488,
-2b750770,
-71902b07,
-5154518f,
-7227a538,
-72717084,
+ff2eed38,
+72708105,
+54337470,
+81055634,
+eb397476,
+07830651,
+70e23875,
+75545172,
+70840554,
+08717084,
+05530c72,
+70840554,
+08717084,
 05530c72,
+70840554,
+08717084,
+05530c72,
+70840554,
+08717084,
+05530cf0,
+1252718f,
+26c93883,
+72279538,
+72708405,
+54087170,
+8405530c,
+fc125271,
+8326ed38,
+7054ff88,
+39fc3d0d,
+76797102,
+8c059f05,
+33575553,
+55837227,
+8a387483,
+06517080,
+2ea238ff,
+125271ff,
+2e933873,
+73708105,
+5534ff12,
+5271ff2e,
+098106ef,
+3874800c,
+863d0d04,
+7474882b,
+75077071,
+902b0751,
+54518f72,
+27a53872,
 71708405,
 530c7271,
 70840553,
 0c727170,
 8405530c,
-f0125271,
-8f26dd38,
-83722790,
-38727170,
-8405530c,
-fc125271,
-8326f238,
-7053ff90,
-39fd3d0d,
-800b8196,
-c8085454,
-72812e9d,
-387381b8,
-fc0cff89,
-ff3fff89,
-9b3f8197,
-a4528151,
-ff9da03f,
-800851a3,
-3f7281b8,
-fc0cff89,
-e33fff88,
-ff3f8197,
-a4528151,
-ff9d843f,
-80085187,
-3f00ff39,
-00ff39f7,
-3d0d7b81,
-97a80882,
-c811085a,
-545a7780,
-2e80da38,
-81881884,
-1908ff05,
-81712b59,
-55598074,
-2480ea38,
-807424b5,
-3873822b,
-78118805,
-56568180,
-19087706,
-5372802e,
-b6387816,
-70085353,
-79517408,
+72717084,
+05530cf0,
+1252718f,
+26dd3883,
+72279038,
+72717084,
+05530cfc,
+12527183,
+26f23870,
+53ff9039,
+fd3d0d80,
+0b8196cc,
+08545472,
+812e9d38,
+7381b980,
+0cff89fc,
+3fff8998,
+3f8197a8,
+528151ff,
+9d9d3f80,
+0851a33f,
+7281b980,
+0cff89e0,
+3fff88fc,
+3f8197a8,
+528151ff,
+9d813f80,
+0851873f,
+00ff3900,
+ff39f73d,
+0d7b8197,
+ac0882c8,
+11085a54,
+5a77802e,
+80da3881,
+88188419,
+08ff0581,
+712b5955,
+59807424,
+80ea3880,
+7424b538,
+73822b78,
+11880556,
+56818019,
+08770653,
+72802eb6,
+38781670,
+08535379,
+51740853,
+722dff14,
+fc17fc17,
+79812c5a,
+57575473,
+8025d638,
+77085877,
+ffad3881,
+97ac0853,
+bc1308a5,
+387951ff,
+833f7408,
 53722dff,
 14fc17fc,
 1779812c,
 5a575754,
-738025d6,
-38770858,
-77ffad38,
-8197a808,
-53bc1308,
-a5387951,
-ff833f74,
-0853722d,
-ff14fc17,
-fc177981,
-2c5a5757,
-54738025,
-ffa838d1,
-398057ff,
-93397251,
-bc130853,
-722d7951,
-fed73fff,
-3d0d819e,
-ac0bfc05,
+738025ff,
+a838d139,
+8057ff93,
+397251bc,
+13085372,
+2d7951fe,
+d73fff3d,
+0d819eb0,
+0bfc0570,
+08525270,
+ff2e9138,
+702dfc12,
 70085252,
-70ff2e91,
-38702dfc,
-12700852,
-5270ff2e,
-098106f1,
-38833d0d,
-0404ff88,
-e83f0400,
+70ff2e09,
+8106f138,
+833d0d04,
+04ff88e5,
+3f040000,
 00000040,
 00000000,
 58333030,
@@ -4714,75 +4715,75 @@ e83f0400,
 46502b20,
 74797065,
 2e0a0000,
-00002467,
-0000246e,
-00002461,
-00002461,
-00002461,
-00002461,
-0000246e,
-0000246e,
-0000246e,
-0000246e,
-0000246e,
-0000245b,
-0000246e,
-0000246e,
-00002455,
-0000244f,
-000025aa,
-000025a4,
-0000259e,
-00002598,
-00002592,
-0000258c,
-00002586,
-00002580,
-000026b1,
-000028c6,
-000028c6,
-000028c6,
-000026aa,
-000026a3,
-0000269c,
-00002695,
-0000268e,
-00002687,
-00002680,
-00002679,
-00002672,
-0000266b,
-00002664,
-0000265d,
-000027fc,
-000027ee,
-000027e0,
-000027d2,
-000027c3,
-000027b3,
-000027a3,
-00002793,
-00002783,
-00002773,
-0000276c,
-00002765,
-00002755,
-00002745,
-0000280b,
-0000272e,
-0000286a,
-00002864,
-0000285e,
-00002858,
-000028bd,
-000028bd,
-000028bd,
-000028bd,
-000028bd,
-000028bd,
-000028bd,
-00002852,
-0000284c,
+0000246a,
+00002471,
+00002464,
+00002464,
+00002464,
+00002464,
+00002471,
+00002471,
+00002471,
+00002471,
+00002471,
+0000245e,
+00002471,
+00002471,
+00002458,
+00002452,
+000025ad,
+000025a7,
+000025a1,
+0000259b,
+00002595,
+0000258f,
+00002589,
+00002583,
+000026b4,
+000028c9,
+000028c9,
+000028c9,
+000026ad,
+000026a6,
+0000269f,
+00002698,
+00002691,
+0000268a,
+00002683,
+0000267c,
+00002675,
+0000266e,
+00002667,
+00002660,
+000027ff,
+000027f1,
+000027e3,
+000027d5,
+000027c6,
+000027b6,
+000027a6,
+00002796,
+00002786,
+00002776,
+0000276f,
+00002768,
+00002758,
+00002748,
+0000280e,
+00002731,
+0000286d,
+00002867,
+00002861,
+0000285b,
+000028c0,
+000028c0,
+000028c0,
+000028c0,
+000028c0,
+000028c0,
+000028c0,
+00002855,
+0000284f,
 00000000,
 00000001,
 00000004,
@@ -4820,7 +4821,7 @@ ffffff00,
 00000000,
 00000000,
 00000000,
-00004f34,
+00004f38,
 00000000,
 00000000,
 0050c285,
@@ -4841,12 +4842,12 @@ c0a82802,
 00000000,
 00000000,
 00006000,
-00004b24,
-00004bac,
+00004b28,
+00004bb0,
 00000000,
-00004e14,
-00004e70,
-00004ecc,
+00004e18,
+00004e74,
+00004ed0,
 00000000,
 00000000,
 00000000,
@@ -4856,7 +4857,7 @@ c0a82802,
 00000000,
 00000000,
 00000000,
-00004b30,
+00004b34,
 00000000,
 00000000,
 00000000,
@@ -8190,5 +8191,4 @@ ffffffff,
 00000000,
 00000000,
 00000000,
-00000000,
 00000000;
 \ No newline at end of file
diff --git a/fpga/usrp3/top/x300/coregen/chipscope_icon.gise b/fpga/usrp3/top/x300/coregen/chipscope_icon.gise
index a4f878755..29d14a154 100644
--- a/fpga/usrp3/top/x300/coregen/chipscope_icon.gise
+++ b/fpga/usrp3/top/x300/coregen/chipscope_icon.gise
@@ -15,7 +15,7 @@
 
   <!--                                                          -->
 
-  <!-- Copyright (c) 1995-2012 Xilinx, Inc.  All rights reserved. -->
+  <!-- Copyright (c) 1995-2013 Xilinx, Inc.  All rights reserved. -->
 
   <version xmlns="http://www.xilinx.com/XMLSchema">11.1</version>
 
diff --git a/fpga/usrp3/top/x300/coregen/chipscope_icon.xise b/fpga/usrp3/top/x300/coregen/chipscope_icon.xise
index 45b6ff0c5..82f131ab5 100644
--- a/fpga/usrp3/top/x300/coregen/chipscope_icon.xise
+++ b/fpga/usrp3/top/x300/coregen/chipscope_icon.xise
@@ -9,10 +9,10 @@
     <!-- along with the project source files, is sufficient to open and    -->
     <!-- implement in ISE Project Navigator.                               -->
     <!--                                                                   -->
-    <!-- Copyright (c) 1995-2012 Xilinx, Inc.  All rights reserved. -->
+    <!-- Copyright (c) 1995-2013 Xilinx, Inc.  All rights reserved. -->
   </header>
 
-  <version xil_pn:ise_version="14.4" xil_pn:schema_version="2"/>
+  <version xil_pn:ise_version="14.6" xil_pn:schema_version="2"/>
 
   <files>
     <file xil_pn:name="chipscope_icon.ngc" xil_pn:type="FILE_NGC">
diff --git a/fpga/usrp3/top/x300/coregen/chipscope_icon_2port.gise b/fpga/usrp3/top/x300/coregen/chipscope_icon_2port.gise
index 36f5c446e..e17e6e891 100644
--- a/fpga/usrp3/top/x300/coregen/chipscope_icon_2port.gise
+++ b/fpga/usrp3/top/x300/coregen/chipscope_icon_2port.gise
@@ -15,7 +15,7 @@
 
   <!--                                                          -->
 
-  <!-- Copyright (c) 1995-2012 Xilinx, Inc.  All rights reserved. -->
+  <!-- Copyright (c) 1995-2013 Xilinx, Inc.  All rights reserved. -->
 
   <version xmlns="http://www.xilinx.com/XMLSchema">11.1</version>
 
diff --git a/fpga/usrp3/top/x300/coregen/chipscope_icon_2port.xise b/fpga/usrp3/top/x300/coregen/chipscope_icon_2port.xise
index 84e1a9201..c1b1aa977 100644
--- a/fpga/usrp3/top/x300/coregen/chipscope_icon_2port.xise
+++ b/fpga/usrp3/top/x300/coregen/chipscope_icon_2port.xise
@@ -9,10 +9,10 @@
     <!-- along with the project source files, is sufficient to open and    -->
     <!-- implement in ISE Project Navigator.                               -->
     <!--                                                                   -->
-    <!-- Copyright (c) 1995-2012 Xilinx, Inc.  All rights reserved. -->
+    <!-- Copyright (c) 1995-2013 Xilinx, Inc.  All rights reserved. -->
   </header>
 
-  <version xil_pn:ise_version="14.4" xil_pn:schema_version="2"/>
+  <version xil_pn:ise_version="14.6" xil_pn:schema_version="2"/>
 
   <files>
     <file xil_pn:name="chipscope_icon_2port.ngc" xil_pn:type="FILE_NGC">
diff --git a/fpga/usrp3/top/x300/coregen/chipscope_ila.gise b/fpga/usrp3/top/x300/coregen/chipscope_ila.gise
index bf58d19ac..ee7bbd2ac 100644
--- a/fpga/usrp3/top/x300/coregen/chipscope_ila.gise
+++ b/fpga/usrp3/top/x300/coregen/chipscope_ila.gise
@@ -15,7 +15,7 @@
 
   <!--                                                          -->
 
-  <!-- Copyright (c) 1995-2012 Xilinx, Inc.  All rights reserved. -->
+  <!-- Copyright (c) 1995-2013 Xilinx, Inc.  All rights reserved. -->
 
   <version xmlns="http://www.xilinx.com/XMLSchema">11.1</version>
 
diff --git a/fpga/usrp3/top/x300/coregen/chipscope_ila.xise b/fpga/usrp3/top/x300/coregen/chipscope_ila.xise
index 9c38762e8..c77f79bd9 100644
--- a/fpga/usrp3/top/x300/coregen/chipscope_ila.xise
+++ b/fpga/usrp3/top/x300/coregen/chipscope_ila.xise
@@ -9,10 +9,10 @@
     <!-- along with the project source files, is sufficient to open and    -->
     <!-- implement in ISE Project Navigator.                               -->
     <!--                                                                   -->
-    <!-- Copyright (c) 1995-2012 Xilinx, Inc.  All rights reserved. -->
+    <!-- Copyright (c) 1995-2013 Xilinx, Inc.  All rights reserved. -->
   </header>
 
-  <version xil_pn:ise_version="14.4" xil_pn:schema_version="2"/>
+  <version xil_pn:ise_version="14.6" xil_pn:schema_version="2"/>
 
   <files>
     <file xil_pn:name="chipscope_ila.ngc" xil_pn:type="FILE_NGC">
diff --git a/fpga/usrp3/top/x300/coregen/chipscope_ila_64.gise b/fpga/usrp3/top/x300/coregen/chipscope_ila_64.gise
index 53cc8f886..c0b0e6a23 100644
--- a/fpga/usrp3/top/x300/coregen/chipscope_ila_64.gise
+++ b/fpga/usrp3/top/x300/coregen/chipscope_ila_64.gise
@@ -15,7 +15,7 @@
 
   <!--                                                          -->
 
-  <!-- Copyright (c) 1995-2012 Xilinx, Inc.  All rights reserved. -->
+  <!-- Copyright (c) 1995-2013 Xilinx, Inc.  All rights reserved. -->
 
   <version xmlns="http://www.xilinx.com/XMLSchema">11.1</version>
 
diff --git a/fpga/usrp3/top/x300/coregen/chipscope_ila_64.xise b/fpga/usrp3/top/x300/coregen/chipscope_ila_64.xise
index 3a41b0d74..bc394c976 100644
--- a/fpga/usrp3/top/x300/coregen/chipscope_ila_64.xise
+++ b/fpga/usrp3/top/x300/coregen/chipscope_ila_64.xise
@@ -9,10 +9,10 @@
     <!-- along with the project source files, is sufficient to open and    -->
     <!-- implement in ISE Project Navigator.                               -->
     <!--                                                                   -->
-    <!-- Copyright (c) 1995-2012 Xilinx, Inc.  All rights reserved. -->
+    <!-- Copyright (c) 1995-2013 Xilinx, Inc.  All rights reserved. -->
   </header>
 
-  <version xil_pn:ise_version="14.4" xil_pn:schema_version="2"/>
+  <version xil_pn:ise_version="14.6" xil_pn:schema_version="2"/>
 
   <files>
     <file xil_pn:name="chipscope_ila_64.ngc" xil_pn:type="FILE_NGC">
diff --git a/fpga/usrp3/top/x300/coregen/coregen.cgp b/fpga/usrp3/top/x300/coregen/coregen.cgp
index 3e343ea49..287f67be4 100644
--- a/fpga/usrp3/top/x300/coregen/coregen.cgp
+++ b/fpga/usrp3/top/x300/coregen/coregen.cgp
@@ -1,6 +1,6 @@
 SET busformat = BusFormatAngleBracketNotRipped
 SET designentry = Verilog
-SET device = xc7k325t
+SET device = xc7k410t
 SET devicefamily = kintex7
 SET flowvendor = Foundation_ISE
 SET package = ffg900
diff --git a/fpga/usrp3/top/x300/coregen/ddr3_32bit.gise b/fpga/usrp3/top/x300/coregen/ddr3_32bit.gise
index ad3ed0e03..53c91b2d8 100644
--- a/fpga/usrp3/top/x300/coregen/ddr3_32bit.gise
+++ b/fpga/usrp3/top/x300/coregen/ddr3_32bit.gise
@@ -15,7 +15,7 @@
 
   <!--                                                          -->
 
-  <!-- Copyright (c) 1995-2012 Xilinx, Inc.  All rights reserved. -->
+  <!-- Copyright (c) 1995-2013 Xilinx, Inc.  All rights reserved. -->
 
   <version xmlns="http://www.xilinx.com/XMLSchema">11.1</version>
 
diff --git a/fpga/usrp3/top/x300/coregen/ddr3_32bit.xise b/fpga/usrp3/top/x300/coregen/ddr3_32bit.xise
index be231b442..d8694a9ea 100644
--- a/fpga/usrp3/top/x300/coregen/ddr3_32bit.xise
+++ b/fpga/usrp3/top/x300/coregen/ddr3_32bit.xise
@@ -9,10 +9,10 @@
     <!-- along with the project source files, is sufficient to open and    -->
     <!-- implement in ISE Project Navigator.                               -->
     <!--                                                                   -->
-    <!-- Copyright (c) 1995-2012 Xilinx, Inc.  All rights reserved. -->
+    <!-- Copyright (c) 1995-2013 Xilinx, Inc.  All rights reserved. -->
   </header>
 
-  <version xil_pn:ise_version="14.4" xil_pn:schema_version="2"/>
+  <version xil_pn:ise_version="14.6" xil_pn:schema_version="2"/>
 
   <files>
     <file xil_pn:name="ddr3_32bit/user_design/rtl/axi/mig_7series_v1_8_axi_ctrl_addr_decode.v" xil_pn:type="FILE_VERILOG">
diff --git a/fpga/usrp3/top/x300/coregen/fifo_short_2clk.gise b/fpga/usrp3/top/x300/coregen/fifo_short_2clk.gise
index ea47d0f4b..ddb581fc1 100644
--- a/fpga/usrp3/top/x300/coregen/fifo_short_2clk.gise
+++ b/fpga/usrp3/top/x300/coregen/fifo_short_2clk.gise
@@ -15,7 +15,7 @@
 
   <!--                                                          -->
 
-  <!-- Copyright (c) 1995-2012 Xilinx, Inc.  All rights reserved. -->
+  <!-- Copyright (c) 1995-2013 Xilinx, Inc.  All rights reserved. -->
 
   <version xmlns="http://www.xilinx.com/XMLSchema">11.1</version>
 
diff --git a/fpga/usrp3/top/x300/coregen/fifo_short_2clk.xise b/fpga/usrp3/top/x300/coregen/fifo_short_2clk.xise
index 0fa5fd50e..a23da93b5 100644
--- a/fpga/usrp3/top/x300/coregen/fifo_short_2clk.xise
+++ b/fpga/usrp3/top/x300/coregen/fifo_short_2clk.xise
@@ -9,10 +9,10 @@
     <!-- along with the project source files, is sufficient to open and    -->
     <!-- implement in ISE Project Navigator.                               -->
     <!--                                                                   -->
-    <!-- Copyright (c) 1995-2012 Xilinx, Inc.  All rights reserved. -->
+    <!-- Copyright (c) 1995-2013 Xilinx, Inc.  All rights reserved. -->
   </header>
 
-  <version xil_pn:ise_version="14.4" xil_pn:schema_version="2"/>
+  <version xil_pn:ise_version="14.6" xil_pn:schema_version="2"/>
 
   <files>
     <file xil_pn:name="fifo_short_2clk.ngc" xil_pn:type="FILE_NGC">
diff --git a/fpga/usrp3/top/x300/coregen/fifo_xlnx_16x40_2clk.gise b/fpga/usrp3/top/x300/coregen/fifo_xlnx_16x40_2clk.gise
index a66f268df..64c479aaf 100644
--- a/fpga/usrp3/top/x300/coregen/fifo_xlnx_16x40_2clk.gise
+++ b/fpga/usrp3/top/x300/coregen/fifo_xlnx_16x40_2clk.gise
@@ -15,7 +15,7 @@
 
   <!--                                                          -->
 
-  <!-- Copyright (c) 1995-2012 Xilinx, Inc.  All rights reserved. -->
+  <!-- Copyright (c) 1995-2013 Xilinx, Inc.  All rights reserved. -->
 
   <version xmlns="http://www.xilinx.com/XMLSchema">11.1</version>
 
diff --git a/fpga/usrp3/top/x300/coregen/fifo_xlnx_16x40_2clk.xise b/fpga/usrp3/top/x300/coregen/fifo_xlnx_16x40_2clk.xise
index 4c5ef82d1..9d088377d 100644
--- a/fpga/usrp3/top/x300/coregen/fifo_xlnx_16x40_2clk.xise
+++ b/fpga/usrp3/top/x300/coregen/fifo_xlnx_16x40_2clk.xise
@@ -9,10 +9,10 @@
     <!-- along with the project source files, is sufficient to open and    -->
     <!-- implement in ISE Project Navigator.                               -->
     <!--                                                                   -->
-    <!-- Copyright (c) 1995-2012 Xilinx, Inc.  All rights reserved. -->
+    <!-- Copyright (c) 1995-2013 Xilinx, Inc.  All rights reserved. -->
   </header>
 
-  <version xil_pn:ise_version="14.4" xil_pn:schema_version="2"/>
+  <version xil_pn:ise_version="14.6" xil_pn:schema_version="2"/>
 
   <files>
     <file xil_pn:name="fifo_xlnx_16x40_2clk.ngc" xil_pn:type="FILE_NGC">
diff --git a/fpga/usrp3/top/x300/coregen_dsp/coregen.cgp b/fpga/usrp3/top/x300/coregen_dsp/coregen.cgp
index 75b625f9b..593e2f179 100644
--- a/fpga/usrp3/top/x300/coregen_dsp/coregen.cgp
+++ b/fpga/usrp3/top/x300/coregen_dsp/coregen.cgp
@@ -1,6 +1,6 @@
 SET busformat = BusFormatAngleBracketNotRipped
 SET designentry = Verilog
-SET device = xc7k325t
+SET device = xc7k410t
 SET devicefamily = kintex7
 SET flowvendor = Other
 SET package = ffg900
diff --git a/fpga/usrp3/top/x300/coregen_dsp/hbdec1.gise b/fpga/usrp3/top/x300/coregen_dsp/hbdec1.gise
index 89731aaf8..5caeab612 100644
--- a/fpga/usrp3/top/x300/coregen_dsp/hbdec1.gise
+++ b/fpga/usrp3/top/x300/coregen_dsp/hbdec1.gise
@@ -15,7 +15,7 @@
 
   <!--                                                          -->
 
-  <!-- Copyright (c) 1995-2012 Xilinx, Inc.  All rights reserved. -->
+  <!-- Copyright (c) 1995-2013 Xilinx, Inc.  All rights reserved. -->
 
   <version xmlns="http://www.xilinx.com/XMLSchema">11.1</version>
 
diff --git a/fpga/usrp3/top/x300/coregen_dsp/hbdec1.ncf b/fpga/usrp3/top/x300/coregen_dsp/hbdec1.ncf
new file mode 100644
index 000000000..e69de29bb
--- /dev/null
+++ b/fpga/usrp3/top/x300/coregen_dsp/hbdec1.ncf
diff --git a/fpga/usrp3/top/x300/coregen_dsp/hbdec1.xise b/fpga/usrp3/top/x300/coregen_dsp/hbdec1.xise
index 0d52b5d47..61795798c 100644
--- a/fpga/usrp3/top/x300/coregen_dsp/hbdec1.xise
+++ b/fpga/usrp3/top/x300/coregen_dsp/hbdec1.xise
@@ -9,10 +9,10 @@
     <!-- along with the project source files, is sufficient to open and    -->
     <!-- implement in ISE Project Navigator.                               -->
     <!--                                                                   -->
-    <!-- Copyright (c) 1995-2012 Xilinx, Inc.  All rights reserved. -->
+    <!-- Copyright (c) 1995-2013 Xilinx, Inc.  All rights reserved. -->
   </header>
 
-  <version xil_pn:ise_version="14.4" xil_pn:schema_version="2"/>
+  <version xil_pn:ise_version="14.6" xil_pn:schema_version="2"/>
 
   <files>
     <file xil_pn:name="hbdec1.ngc" xil_pn:type="FILE_NGC">
diff --git a/fpga/usrp3/top/x300/coregen_dsp/hbdec2.gise b/fpga/usrp3/top/x300/coregen_dsp/hbdec2.gise
index 3a0d858e5..e87ebf933 100644
--- a/fpga/usrp3/top/x300/coregen_dsp/hbdec2.gise
+++ b/fpga/usrp3/top/x300/coregen_dsp/hbdec2.gise
@@ -15,7 +15,7 @@
 
   <!--                                                          -->
 
-  <!-- Copyright (c) 1995-2012 Xilinx, Inc.  All rights reserved. -->
+  <!-- Copyright (c) 1995-2013 Xilinx, Inc.  All rights reserved. -->
 
   <version xmlns="http://www.xilinx.com/XMLSchema">11.1</version>
 
diff --git a/fpga/usrp3/top/x300/coregen_dsp/hbdec2.ncf b/fpga/usrp3/top/x300/coregen_dsp/hbdec2.ncf
new file mode 100644
index 000000000..e69de29bb
--- /dev/null
+++ b/fpga/usrp3/top/x300/coregen_dsp/hbdec2.ncf
diff --git a/fpga/usrp3/top/x300/coregen_dsp/hbdec2.xise b/fpga/usrp3/top/x300/coregen_dsp/hbdec2.xise
index ea71dfd55..af99fb5fb 100644
--- a/fpga/usrp3/top/x300/coregen_dsp/hbdec2.xise
+++ b/fpga/usrp3/top/x300/coregen_dsp/hbdec2.xise
@@ -9,10 +9,10 @@
     <!-- along with the project source files, is sufficient to open and    -->
     <!-- implement in ISE Project Navigator.                               -->
     <!--                                                                   -->
-    <!-- Copyright (c) 1995-2012 Xilinx, Inc.  All rights reserved. -->
+    <!-- Copyright (c) 1995-2013 Xilinx, Inc.  All rights reserved. -->
   </header>
 
-  <version xil_pn:ise_version="14.4" xil_pn:schema_version="2"/>
+  <version xil_pn:ise_version="14.6" xil_pn:schema_version="2"/>
 
   <files>
     <file xil_pn:name="hbdec2.ngc" xil_pn:type="FILE_NGC">
diff --git a/fpga/usrp3/top/x300/coregen_dsp/hbdec3.gise b/fpga/usrp3/top/x300/coregen_dsp/hbdec3.gise
index 97abfa58f..d23808b1b 100644
--- a/fpga/usrp3/top/x300/coregen_dsp/hbdec3.gise
+++ b/fpga/usrp3/top/x300/coregen_dsp/hbdec3.gise
@@ -15,7 +15,7 @@
 
   <!--                                                          -->
 
-  <!-- Copyright (c) 1995-2012 Xilinx, Inc.  All rights reserved. -->
+  <!-- Copyright (c) 1995-2013 Xilinx, Inc.  All rights reserved. -->
 
   <version xmlns="http://www.xilinx.com/XMLSchema">11.1</version>
 
diff --git a/fpga/usrp3/top/x300/coregen_dsp/hbdec3.ncf b/fpga/usrp3/top/x300/coregen_dsp/hbdec3.ncf
new file mode 100644
index 000000000..e69de29bb
--- /dev/null
+++ b/fpga/usrp3/top/x300/coregen_dsp/hbdec3.ncf
diff --git a/fpga/usrp3/top/x300/coregen_dsp/hbdec3.xise b/fpga/usrp3/top/x300/coregen_dsp/hbdec3.xise
index d38b61410..1af65c49d 100644
--- a/fpga/usrp3/top/x300/coregen_dsp/hbdec3.xise
+++ b/fpga/usrp3/top/x300/coregen_dsp/hbdec3.xise
@@ -9,10 +9,10 @@
     <!-- along with the project source files, is sufficient to open and    -->
     <!-- implement in ISE Project Navigator.                               -->
     <!--                                                                   -->
-    <!-- Copyright (c) 1995-2012 Xilinx, Inc.  All rights reserved. -->
+    <!-- Copyright (c) 1995-2013 Xilinx, Inc.  All rights reserved. -->
   </header>
 
-  <version xil_pn:ise_version="14.4" xil_pn:schema_version="2"/>
+  <version xil_pn:ise_version="14.6" xil_pn:schema_version="2"/>
 
   <files>
     <file xil_pn:name="hbdec3.ngc" xil_pn:type="FILE_NGC">
diff --git a/fpga/usrp3/top/x300/coregen_dsp/hbint1.gise b/fpga/usrp3/top/x300/coregen_dsp/hbint1.gise
index fb4e6f8ff..c6c4013b9 100644
--- a/fpga/usrp3/top/x300/coregen_dsp/hbint1.gise
+++ b/fpga/usrp3/top/x300/coregen_dsp/hbint1.gise
@@ -15,7 +15,7 @@
 
   <!--                                                          -->
 
-  <!-- Copyright (c) 1995-2012 Xilinx, Inc.  All rights reserved. -->
+  <!-- Copyright (c) 1995-2013 Xilinx, Inc.  All rights reserved. -->
 
   <version xmlns="http://www.xilinx.com/XMLSchema">11.1</version>
 
diff --git a/fpga/usrp3/top/x300/coregen_dsp/hbint1.ncf b/fpga/usrp3/top/x300/coregen_dsp/hbint1.ncf
new file mode 100644
index 000000000..e69de29bb
--- /dev/null
+++ b/fpga/usrp3/top/x300/coregen_dsp/hbint1.ncf
diff --git a/fpga/usrp3/top/x300/coregen_dsp/hbint1.xise b/fpga/usrp3/top/x300/coregen_dsp/hbint1.xise
index a18bcca78..ddfc071f2 100644
--- a/fpga/usrp3/top/x300/coregen_dsp/hbint1.xise
+++ b/fpga/usrp3/top/x300/coregen_dsp/hbint1.xise
@@ -9,10 +9,10 @@
     <!-- along with the project source files, is sufficient to open and    -->
     <!-- implement in ISE Project Navigator.                               -->
     <!--                                                                   -->
-    <!-- Copyright (c) 1995-2012 Xilinx, Inc.  All rights reserved. -->
+    <!-- Copyright (c) 1995-2013 Xilinx, Inc.  All rights reserved. -->
   </header>
 
-  <version xil_pn:ise_version="14.4" xil_pn:schema_version="2"/>
+  <version xil_pn:ise_version="14.6" xil_pn:schema_version="2"/>
 
   <files>
     <file xil_pn:name="hbint1.ngc" xil_pn:type="FILE_NGC">
diff --git a/fpga/usrp3/top/x300/coregen_dsp/hbint2.gise b/fpga/usrp3/top/x300/coregen_dsp/hbint2.gise
index f1ee7b4ca..e4b9546a7 100644
--- a/fpga/usrp3/top/x300/coregen_dsp/hbint2.gise
+++ b/fpga/usrp3/top/x300/coregen_dsp/hbint2.gise
@@ -15,7 +15,7 @@
 
   <!--                                                          -->
 
-  <!-- Copyright (c) 1995-2012 Xilinx, Inc.  All rights reserved. -->
+  <!-- Copyright (c) 1995-2013 Xilinx, Inc.  All rights reserved. -->
 
   <version xmlns="http://www.xilinx.com/XMLSchema">11.1</version>
 
diff --git a/fpga/usrp3/top/x300/coregen_dsp/hbint2.ncf b/fpga/usrp3/top/x300/coregen_dsp/hbint2.ncf
new file mode 100644
index 000000000..e69de29bb
--- /dev/null
+++ b/fpga/usrp3/top/x300/coregen_dsp/hbint2.ncf
diff --git a/fpga/usrp3/top/x300/coregen_dsp/hbint2.xise b/fpga/usrp3/top/x300/coregen_dsp/hbint2.xise
index 86c139f4e..471c12463 100644
--- a/fpga/usrp3/top/x300/coregen_dsp/hbint2.xise
+++ b/fpga/usrp3/top/x300/coregen_dsp/hbint2.xise
@@ -9,10 +9,10 @@
     <!-- along with the project source files, is sufficient to open and    -->
     <!-- implement in ISE Project Navigator.                               -->
     <!--                                                                   -->
-    <!-- Copyright (c) 1995-2012 Xilinx, Inc.  All rights reserved. -->
+    <!-- Copyright (c) 1995-2013 Xilinx, Inc.  All rights reserved. -->
   </header>
 
-  <version xil_pn:ise_version="14.4" xil_pn:schema_version="2"/>
+  <version xil_pn:ise_version="14.6" xil_pn:schema_version="2"/>
 
   <files>
     <file xil_pn:name="hbint2.ngc" xil_pn:type="FILE_NGC">
diff --git a/fpga/usrp3/top/x300/coregen_dsp/hbint3.gise b/fpga/usrp3/top/x300/coregen_dsp/hbint3.gise
index 2ba7d5965..bad4add7b 100644
--- a/fpga/usrp3/top/x300/coregen_dsp/hbint3.gise
+++ b/fpga/usrp3/top/x300/coregen_dsp/hbint3.gise
@@ -15,7 +15,7 @@
 
   <!--                                                          -->
 
-  <!-- Copyright (c) 1995-2012 Xilinx, Inc.  All rights reserved. -->
+  <!-- Copyright (c) 1995-2013 Xilinx, Inc.  All rights reserved. -->
 
   <version xmlns="http://www.xilinx.com/XMLSchema">11.1</version>
 
diff --git a/fpga/usrp3/top/x300/coregen_dsp/hbint3.ncf b/fpga/usrp3/top/x300/coregen_dsp/hbint3.ncf
new file mode 100644
index 000000000..e69de29bb
--- /dev/null
+++ b/fpga/usrp3/top/x300/coregen_dsp/hbint3.ncf
diff --git a/fpga/usrp3/top/x300/coregen_dsp/hbint3.xise b/fpga/usrp3/top/x300/coregen_dsp/hbint3.xise
index 764b94b96..a608666d2 100644
--- a/fpga/usrp3/top/x300/coregen_dsp/hbint3.xise
+++ b/fpga/usrp3/top/x300/coregen_dsp/hbint3.xise
@@ -9,10 +9,10 @@
     <!-- along with the project source files, is sufficient to open and    -->
     <!-- implement in ISE Project Navigator.                               -->
     <!--                                                                   -->
-    <!-- Copyright (c) 1995-2012 Xilinx, Inc.  All rights reserved. -->
+    <!-- Copyright (c) 1995-2013 Xilinx, Inc.  All rights reserved. -->
   </header>
 
-  <version xil_pn:ise_version="14.4" xil_pn:schema_version="2"/>
+  <version xil_pn:ise_version="14.6" xil_pn:schema_version="2"/>
 
   <files>
     <file xil_pn:name="hbint3.ngc" xil_pn:type="FILE_NGC">
diff --git a/fpga/usrp3/top/x300/floorplan_X300.ucf b/fpga/usrp3/top/x300/floorplan_X300.ucf
index e2b704d7b..5e1b278c1 100644
--- a/fpga/usrp3/top/x300/floorplan_X300.ucf
+++ b/fpga/usrp3/top/x300/floorplan_X300.ucf
@@ -1,30 +1,4 @@
 
-INST "x300_core/bus_int/sc/sys_ram/sys_ram0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_init.ram/NO_BMM_INFO.SP.SIMPLE_PRIM36.ram" LOC = RAMB36_X3Y39;
-INST "x300_core/bus_int/sc/sys_ram/sys_ram0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_init.ram/NO_BMM_INFO.SP.SIMPLE_PRIM36.ram" LOC = RAMB36_X3Y40;
-INST "x300_core/bus_int/sc/sys_ram/sys_ram0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_init.ram/NO_BMM_INFO.SP.SIMPLE_PRIM36.ram" LOC = RAMB36_X3Y41;
-INST "x300_core/bus_int/sc/sys_ram/sys_ram0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_init.ram/NO_BMM_INFO.SP.SIMPLE_PRIM36.ram" LOC = RAMB36_X3Y42;
-INST "x300_core/bus_int/sc/sys_ram/sys_ram0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_init.ram/NO_BMM_INFO.SP.SIMPLE_PRIM36.ram" LOC = RAMB36_X3Y43;
-INST "x300_core/bus_int/sc/sys_ram/sys_ram0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_init.ram/NO_BMM_INFO.SP.SIMPLE_PRIM36.ram" LOC = RAMB36_X3Y44;
-INST "x300_core/bus_int/sc/sys_ram/sys_ram0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_init.ram/NO_BMM_INFO.SP.SIMPLE_PRIM36.ram" LOC = RAMB36_X3Y45;
-INST "x300_core/bus_int/sc/sys_ram/sys_ram0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_init.ram/NO_BMM_INFO.SP.SIMPLE_PRIM36.ram" LOC = RAMB36_X3Y46;
-
-INST "x300_core/bus_int/sc/sys_ram/sys_ram1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_init.ram/NO_BMM_INFO.SP.SIMPLE_PRIM36.ram" LOC = RAMB36_X4Y39;
-INST "x300_core/bus_int/sc/sys_ram/sys_ram1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_init.ram/NO_BMM_INFO.SP.SIMPLE_PRIM36.ram" LOC = RAMB36_X4Y40;
-INST "x300_core/bus_int/sc/sys_ram/sys_ram1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_init.ram/NO_BMM_INFO.SP.SIMPLE_PRIM36.ram" LOC = RAMB36_X4Y41;
-INST "x300_core/bus_int/sc/sys_ram/sys_ram1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_init.ram/NO_BMM_INFO.SP.SIMPLE_PRIM36.ram" LOC = RAMB36_X4Y42;
-INST "x300_core/bus_int/sc/sys_ram/sys_ram1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_init.ram/NO_BMM_INFO.SP.SIMPLE_PRIM36.ram" LOC = RAMB36_X4Y43;
-INST "x300_core/bus_int/sc/sys_ram/sys_ram1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_init.ram/NO_BMM_INFO.SP.SIMPLE_PRIM36.ram" LOC = RAMB36_X4Y44;
-INST "x300_core/bus_int/sc/sys_ram/sys_ram1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_init.ram/NO_BMM_INFO.SP.SIMPLE_PRIM36.ram" LOC = RAMB36_X4Y45;
-INST "x300_core/bus_int/sc/sys_ram/sys_ram1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_init.ram/NO_BMM_INFO.SP.SIMPLE_PRIM36.ram" LOC = RAMB36_X4Y46;
-
-INST "x300_core/bus_int/sc/axi_stream_to_wb/input_stream_bram/Mram_ram1" LOC = RAMB36_X3Y35;
-INST "x300_core/bus_int/sc/axi_stream_to_wb/input_stream_bram/Mram_ram2" LOC = RAMB36_X3Y36;
-
-INST "x300_core/bus_int/sc/axi_stream_to_wb/output_stream_bram/Mram_ram1" LOC = RAMB36_X3Y37;
-INST "x300_core/bus_int/sc/axi_stream_to_wb/output_stream_bram/Mram_ram2" LOC = RAMB36_X3Y38;
-
-INST "x300_core/bus_int/sc/zpu_top0*" AREA_GROUP = "pblock_0";
-AREA_GROUP "pblock_0" RANGE=SLICE_X80Y179:SLICE_X145Y242;
 
 INST "x300_core/radio0/*" AREA_GROUP = "pblock_1";
 AREA_GROUP "pblock_1" RANGE=SLICE_X0Y101:SLICE_X79Y248;
diff --git a/fpga/usrp3/top/x300/gen_ddrlvds.v b/fpga/usrp3/top/x300/gen_ddrlvds.v
index 396d5feda..680b10c84 100644
--- a/fpga/usrp3/top/x300/gen_ddrlvds.v
+++ b/fpga/usrp3/top/x300/gen_ddrlvds.v
@@ -31,6 +31,8 @@ module gen_ddrlvds
    reg 		rising_edge;
    wire [15:0] 	i_and_q_2x;
    reg 		sync_2x;
+   reg 		sync_dacs_reg;
+   
    
    
    genvar 	z;
@@ -55,6 +57,7 @@ module gen_ddrlvds
      begin
 	i_reg <= i;
 	q_reg <= q;
+	sync_dacs_reg <= sync_dacs;
      end  
 
    always @(posedge tx_clk_2x)
@@ -67,7 +70,7 @@ module gen_ddrlvds
 	// To sync multiple AD9146 DAC's an extended assertion of FRAME is required,
 	// when sync flag set, squash one rising_edge assertion which causes a 3 word assertion of FRAME,
 	// also reset sync flag. "sync_dacs" comes from 1x clk and pulse lasts 2 2x clock cycles...this is accounted for.
-	sync_2x <=  (phase_eq_phase2x && sync_2x) ? 1'b0 /*RESET */ : (sync_dacs) ? 1'b1 /* SET */ : sync_2x /* HOLD */;
+	sync_2x <=  (phase_eq_phase2x && sync_2x) ? 1'b0 /*RESET */ : (sync_dacs_reg) ? 1'b1 /* SET */ : sync_2x /* HOLD */;
 	rising_edge <= (phase_eq_phase2x && ~sync_2x);
 	phase_2x <= phase;
      end
author	Ben Hilburn <ben.hilburn@ettus.com>	2014-07-22 15:49:02 -0700
committer	Ben Hilburn <ben.hilburn@ettus.com>	2014-07-22 15:49:02 -0700
commit	b63507efb3cf1a8fa20794c452d57028e18da182 (patch)
tree	13f6ec6c3098dff29a3fb50ff3c70bc4d22e7e32 /fpga/usrp3/top
parent	7911d3e2e90672f44eafc635208053fe75ff19d9 (diff)
download	uhd-b63507efb3cf1a8fa20794c452d57028e18da182.tar.gz uhd-b63507efb3cf1a8fa20794c452d57028e18da182.tar.bz2 uhd-b63507efb3cf1a8fa20794c452d57028e18da182.zip