diff options
author | Wade Fife <wade.fife@ettus.com> | 2022-03-29 19:11:54 -0500 |
---|---|---|
committer | Aaron Rossetto <aaron.rossetto@ni.com> | 2022-03-31 13:51:23 -0700 |
commit | 002ff9698e09b94c396736613e493f79e9c56442 (patch) | |
tree | 91680b09b654a0a53d7ee94f51c24e3653863ac1 /fpga/usrp3/top/x400 | |
parent | 07ee9ab75172beca11c6d68dd2daeb586ef2c3e7 (diff) | |
download | uhd-002ff9698e09b94c396736613e493f79e9c56442.tar.gz uhd-002ff9698e09b94c396736613e493f79e9c56442.tar.bz2 uhd-002ff9698e09b94c396736613e493f79e9c56442.zip |
fpga: Update all RFNoC images
Diffstat (limited to 'fpga/usrp3/top/x400')
-rw-r--r-- | fpga/usrp3/top/x400/x410_100_rfnoc_image_core.v | 14 | ||||
-rw-r--r-- | fpga/usrp3/top/x400/x410_100_rfnoc_image_core.vh | 6 | ||||
-rw-r--r-- | fpga/usrp3/top/x400/x410_200_rfnoc_image_core.v | 42 | ||||
-rw-r--r-- | fpga/usrp3/top/x400/x410_200_rfnoc_image_core.vh | 6 | ||||
-rw-r--r-- | fpga/usrp3/top/x400/x410_400_128_rfnoc_image_core.v | 6 | ||||
-rw-r--r-- | fpga/usrp3/top/x400/x410_400_128_rfnoc_image_core.vh | 6 | ||||
-rw-r--r-- | fpga/usrp3/top/x400/x410_400_rfnoc_image_core.v | 4 | ||||
-rw-r--r-- | fpga/usrp3/top/x400/x410_400_rfnoc_image_core.vh | 4 |
8 files changed, 44 insertions, 44 deletions
diff --git a/fpga/usrp3/top/x400/x410_100_rfnoc_image_core.v b/fpga/usrp3/top/x400/x410_100_rfnoc_image_core.v index 398ef32dd..968361f4e 100644 --- a/fpga/usrp3/top/x400/x410_100_rfnoc_image_core.v +++ b/fpga/usrp3/top/x400/x410_100_rfnoc_image_core.v @@ -13,9 +13,9 @@ // This file was automatically generated by the RFNoC image builder tool. // Re-running that tool will overwrite this file! // -// File generated on: 2022-02-02T14:39:07.260299 -// Source: ./x410_100_rfnoc_image_core.yml -// Source SHA256: 0171fb376a68431d88c4d9a1f5b69c5b20ebb0e5b4efacb34173f9349a25e3d9 +// File generated on: 2022-03-29T22:54:34.224724 +// Source: x410_100_rfnoc_image_core.yml +// Source SHA256: 9e62fec6fb4c74b9aedd932cb474c3eac35f1455a9947cd72c82d3d3eff505d7 // `default_nettype none @@ -569,7 +569,7 @@ module rfnoc_image_core #( // If requested buffer size is 0, use the minimum SRL-based FIFO size. // Otherwise, make sure it's at least two MTU-sized packets. - localparam REQ_BUFF_SIZE_EP4 = (4096)/(CHDR_W/8); + localparam REQ_BUFF_SIZE_EP4 = (16384)/(CHDR_W/8); localparam INGRESS_BUFF_SIZE_EP4 = REQ_BUFF_SIZE_EP4 == 0 ? 5 : REQ_BUFF_SIZE_EP4 < 2*(2**MTU) ? MTU+1 : @@ -638,7 +638,7 @@ module rfnoc_image_core #( // If requested buffer size is 0, use the minimum SRL-based FIFO size. // Otherwise, make sure it's at least two MTU-sized packets. - localparam REQ_BUFF_SIZE_EP5 = (4096)/(CHDR_W/8); + localparam REQ_BUFF_SIZE_EP5 = (16384)/(CHDR_W/8); localparam INGRESS_BUFF_SIZE_EP5 = REQ_BUFF_SIZE_EP5 == 0 ? 5 : REQ_BUFF_SIZE_EP5 < 2*(2**MTU) ? MTU+1 : @@ -707,7 +707,7 @@ module rfnoc_image_core #( // If requested buffer size is 0, use the minimum SRL-based FIFO size. // Otherwise, make sure it's at least two MTU-sized packets. - localparam REQ_BUFF_SIZE_EP6 = (4096)/(CHDR_W/8); + localparam REQ_BUFF_SIZE_EP6 = (16384)/(CHDR_W/8); localparam INGRESS_BUFF_SIZE_EP6 = REQ_BUFF_SIZE_EP6 == 0 ? 5 : REQ_BUFF_SIZE_EP6 < 2*(2**MTU) ? MTU+1 : @@ -776,7 +776,7 @@ module rfnoc_image_core #( // If requested buffer size is 0, use the minimum SRL-based FIFO size. // Otherwise, make sure it's at least two MTU-sized packets. - localparam REQ_BUFF_SIZE_EP7 = (4096)/(CHDR_W/8); + localparam REQ_BUFF_SIZE_EP7 = (16384)/(CHDR_W/8); localparam INGRESS_BUFF_SIZE_EP7 = REQ_BUFF_SIZE_EP7 == 0 ? 5 : REQ_BUFF_SIZE_EP7 < 2*(2**MTU) ? MTU+1 : diff --git a/fpga/usrp3/top/x400/x410_100_rfnoc_image_core.vh b/fpga/usrp3/top/x400/x410_100_rfnoc_image_core.vh index b72dbf932..1502b6bc8 100644 --- a/fpga/usrp3/top/x400/x410_100_rfnoc_image_core.vh +++ b/fpga/usrp3/top/x400/x410_100_rfnoc_image_core.vh @@ -12,9 +12,9 @@ // This file was automatically generated by the RFNoC image builder tool. // Re-running that tool will overwrite this file! // -// File generated on: 2022-02-02T14:39:07.293349 -// Source: ./x410_100_rfnoc_image_core.yml -// Source SHA256: 0171fb376a68431d88c4d9a1f5b69c5b20ebb0e5b4efacb34173f9349a25e3d9 +// File generated on: 2022-03-29T22:54:34.258722 +// Source: x410_100_rfnoc_image_core.yml +// Source SHA256: 9e62fec6fb4c74b9aedd932cb474c3eac35f1455a9947cd72c82d3d3eff505d7 // `define CHDR_WIDTH 64 diff --git a/fpga/usrp3/top/x400/x410_200_rfnoc_image_core.v b/fpga/usrp3/top/x400/x410_200_rfnoc_image_core.v index 9e71ff039..8b8126bd6 100644 --- a/fpga/usrp3/top/x400/x410_200_rfnoc_image_core.v +++ b/fpga/usrp3/top/x400/x410_200_rfnoc_image_core.v @@ -13,9 +13,9 @@ // This file was automatically generated by the RFNoC image builder tool. // Re-running that tool will overwrite this file! // -// File generated on: 2022-02-02T14:39:11.377126 -// Source: ./x410_200_rfnoc_image_core.yml -// Source SHA256: 57ca44ee7facd8ddcd6a88170463ea9665328e011511c8b5d87684fc78b43bd6 +// File generated on: 2022-03-29T22:54:34.653995 +// Source: x410_200_rfnoc_image_core.yml +// Source SHA256: 2f39eb00e4449ba15add66b6a3921d729afa21f8c34d609b82ca51d6b4ab8bec // `default_nettype none @@ -569,7 +569,7 @@ module rfnoc_image_core #( // If requested buffer size is 0, use the minimum SRL-based FIFO size. // Otherwise, make sure it's at least two MTU-sized packets. - localparam REQ_BUFF_SIZE_EP4 = (4096)/(CHDR_W/8); + localparam REQ_BUFF_SIZE_EP4 = (16384)/(CHDR_W/8); localparam INGRESS_BUFF_SIZE_EP4 = REQ_BUFF_SIZE_EP4 == 0 ? 5 : REQ_BUFF_SIZE_EP4 < 2*(2**MTU) ? MTU+1 : @@ -638,7 +638,7 @@ module rfnoc_image_core #( // If requested buffer size is 0, use the minimum SRL-based FIFO size. // Otherwise, make sure it's at least two MTU-sized packets. - localparam REQ_BUFF_SIZE_EP5 = (4096)/(CHDR_W/8); + localparam REQ_BUFF_SIZE_EP5 = (16384)/(CHDR_W/8); localparam INGRESS_BUFF_SIZE_EP5 = REQ_BUFF_SIZE_EP5 == 0 ? 5 : REQ_BUFF_SIZE_EP5 < 2*(2**MTU) ? MTU+1 : @@ -707,7 +707,7 @@ module rfnoc_image_core #( // If requested buffer size is 0, use the minimum SRL-based FIFO size. // Otherwise, make sure it's at least two MTU-sized packets. - localparam REQ_BUFF_SIZE_EP6 = (4096)/(CHDR_W/8); + localparam REQ_BUFF_SIZE_EP6 = (16384)/(CHDR_W/8); localparam INGRESS_BUFF_SIZE_EP6 = REQ_BUFF_SIZE_EP6 == 0 ? 5 : REQ_BUFF_SIZE_EP6 < 2*(2**MTU) ? MTU+1 : @@ -776,7 +776,7 @@ module rfnoc_image_core #( // If requested buffer size is 0, use the minimum SRL-based FIFO size. // Otherwise, make sure it's at least two MTU-sized packets. - localparam REQ_BUFF_SIZE_EP7 = (4096)/(CHDR_W/8); + localparam REQ_BUFF_SIZE_EP7 = (16384)/(CHDR_W/8); localparam INGRESS_BUFF_SIZE_EP7 = REQ_BUFF_SIZE_EP7 == 0 ? 5 : REQ_BUFF_SIZE_EP7 < 2*(2**MTU) ? MTU+1 : @@ -1604,20 +1604,6 @@ module rfnoc_image_core #( assign radio1_m_ctrlport_resp_status = m_ctrlport_radio1_resp_status; assign radio1_m_ctrlport_resp_data = m_ctrlport_radio1_resp_data; - assign radio0_radio_rx_data = radio_rx_data_radio0; - assign radio0_radio_rx_stb = radio_rx_stb_radio0; - assign radio_rx_running_radio0 = radio0_radio_rx_running; - assign radio_tx_data_radio0 = radio0_radio_tx_data; - assign radio0_radio_tx_stb = radio_tx_stb_radio0; - assign radio_tx_running_radio0 = radio0_radio_tx_running; - - assign radio1_radio_rx_data = radio_rx_data_radio1; - assign radio1_radio_rx_stb = radio_rx_stb_radio1; - assign radio_rx_running_radio1 = radio1_radio_rx_running; - assign radio_tx_data_radio1 = radio1_radio_tx_data; - assign radio1_radio_tx_stb = radio_tx_stb_radio1; - assign radio_tx_running_radio1 = radio1_radio_tx_running; - assign replay0_axi_rst = axi_rst; assign m_axi_awid = replay0_m_axi_awid; assign m_axi_awaddr = replay0_m_axi_awaddr; @@ -1664,6 +1650,20 @@ module rfnoc_image_core #( assign replay0_m_axi_rvalid = m_axi_rvalid; assign m_axi_rready = replay0_m_axi_rready; + assign radio0_radio_rx_data = radio_rx_data_radio0; + assign radio0_radio_rx_stb = radio_rx_stb_radio0; + assign radio_rx_running_radio0 = radio0_radio_rx_running; + assign radio_tx_data_radio0 = radio0_radio_tx_data; + assign radio0_radio_tx_stb = radio_tx_stb_radio0; + assign radio_tx_running_radio0 = radio0_radio_tx_running; + + assign radio1_radio_rx_data = radio_rx_data_radio1; + assign radio1_radio_rx_stb = radio_rx_stb_radio1; + assign radio_rx_running_radio1 = radio1_radio_rx_running; + assign radio_tx_data_radio1 = radio1_radio_tx_data; + assign radio1_radio_tx_stb = radio_tx_stb_radio1; + assign radio_tx_running_radio1 = radio1_radio_tx_running; + // Broadcaster/Listener Connections: assign radio0_radio_time = radio_time; diff --git a/fpga/usrp3/top/x400/x410_200_rfnoc_image_core.vh b/fpga/usrp3/top/x400/x410_200_rfnoc_image_core.vh index 8d9e8af8b..df84f4e22 100644 --- a/fpga/usrp3/top/x400/x410_200_rfnoc_image_core.vh +++ b/fpga/usrp3/top/x400/x410_200_rfnoc_image_core.vh @@ -12,9 +12,9 @@ // This file was automatically generated by the RFNoC image builder tool. // Re-running that tool will overwrite this file! // -// File generated on: 2022-02-02T14:39:11.410399 -// Source: ./x410_200_rfnoc_image_core.yml -// Source SHA256: 57ca44ee7facd8ddcd6a88170463ea9665328e011511c8b5d87684fc78b43bd6 +// File generated on: 2022-03-29T22:54:34.688772 +// Source: x410_200_rfnoc_image_core.yml +// Source SHA256: 2f39eb00e4449ba15add66b6a3921d729afa21f8c34d609b82ca51d6b4ab8bec // `define CHDR_WIDTH 64 diff --git a/fpga/usrp3/top/x400/x410_400_128_rfnoc_image_core.v b/fpga/usrp3/top/x400/x410_400_128_rfnoc_image_core.v index d31cc728e..97dd45336 100644 --- a/fpga/usrp3/top/x400/x410_400_128_rfnoc_image_core.v +++ b/fpga/usrp3/top/x400/x410_400_128_rfnoc_image_core.v @@ -13,9 +13,9 @@ // This file was automatically generated by the RFNoC image builder tool. // Re-running that tool will overwrite this file! // -// File generated on: 2022-03-14T16:50:52.296419 -// Source: ./x410_400_128_rfnoc_image_core.yml -// Source SHA256: 78673c977afc0a046ef08c3070fd3600aac7ba8918ce79c698731d693678cd85 +// File generated on: 2022-03-29T22:54:35.478639 +// Source: x410_400_128_rfnoc_image_core.yml +// Source SHA256: 0e1aea15a9108fa6fbc86d91a7ee9930440a03c66e96bcd86c179ed5b6da5d53 // `default_nettype none diff --git a/fpga/usrp3/top/x400/x410_400_128_rfnoc_image_core.vh b/fpga/usrp3/top/x400/x410_400_128_rfnoc_image_core.vh index 229eeeefe..81b46ed57 100644 --- a/fpga/usrp3/top/x400/x410_400_128_rfnoc_image_core.vh +++ b/fpga/usrp3/top/x400/x410_400_128_rfnoc_image_core.vh @@ -12,9 +12,9 @@ // This file was automatically generated by the RFNoC image builder tool. // Re-running that tool will overwrite this file! // -// File generated on: 2022-03-14T16:50:52.329591 -// Source: ./x410_400_128_rfnoc_image_core.yml -// Source SHA256: 78673c977afc0a046ef08c3070fd3600aac7ba8918ce79c698731d693678cd85 +// File generated on: 2022-03-29T22:54:35.513269 +// Source: x410_400_128_rfnoc_image_core.yml +// Source SHA256: 0e1aea15a9108fa6fbc86d91a7ee9930440a03c66e96bcd86c179ed5b6da5d53 // `define CHDR_WIDTH 128 diff --git a/fpga/usrp3/top/x400/x410_400_rfnoc_image_core.v b/fpga/usrp3/top/x400/x410_400_rfnoc_image_core.v index 0d14ecc97..b0fd67b51 100644 --- a/fpga/usrp3/top/x400/x410_400_rfnoc_image_core.v +++ b/fpga/usrp3/top/x400/x410_400_rfnoc_image_core.v @@ -13,9 +13,9 @@ // This file was automatically generated by the RFNoC image builder tool. // Re-running that tool will overwrite this file! // -// File generated on: 2022-01-24T08:37:29.737428 +// File generated on: 2022-03-29T22:54:35.062926 // Source: x410_400_rfnoc_image_core.yml -// Source SHA256: aff421903b98211e4822bd2968fd02c679bf30a215ee65e906d4f9a1d79df71e +// Source SHA256: 58e375a5b646df42d81e3af066727c562580c7d98df5eb361163e0924463a466 // `default_nettype none diff --git a/fpga/usrp3/top/x400/x410_400_rfnoc_image_core.vh b/fpga/usrp3/top/x400/x410_400_rfnoc_image_core.vh index 8b6311c0f..f42109295 100644 --- a/fpga/usrp3/top/x400/x410_400_rfnoc_image_core.vh +++ b/fpga/usrp3/top/x400/x410_400_rfnoc_image_core.vh @@ -12,9 +12,9 @@ // This file was automatically generated by the RFNoC image builder tool. // Re-running that tool will overwrite this file! // -// File generated on: 2022-01-24T08:37:29.769622 +// File generated on: 2022-03-29T22:54:35.096636 // Source: x410_400_rfnoc_image_core.yml -// Source SHA256: aff421903b98211e4822bd2968fd02c679bf30a215ee65e906d4f9a1d79df71e +// Source SHA256: 58e375a5b646df42d81e3af066727c562580c7d98df5eb361163e0924463a466 // `define CHDR_WIDTH 512 |