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| author | Javier Valenzuela <javier.valenzuela@ni.com> | 2021-09-27 14:35:57 -0500 |
|---|---|---|
| committer | Wade Fife <wade.fife@ettus.com> | 2022-01-25 10:18:47 -0700 |
| commit | 4bfbb9eeec92fdd3e9d7096006f63477d4848f76 (patch) | |
| tree | 3e0351173fc281dad45ae185652983df5be276e2 /fpga/usrp3/top/x400/ip | |
| parent | 38c549d1f7672e38773fc6624539cc166285a1df (diff) | |
| download | uhd-4bfbb9eeec92fdd3e9d7096006f63477d4848f76.tar.gz uhd-4bfbb9eeec92fdd3e9d7096006f63477d4848f76.tar.bz2 uhd-4bfbb9eeec92fdd3e9d7096006f63477d4848f76.zip | |
fpga: x400: Expand PS GPIO port for DIO control
Diffstat (limited to 'fpga/usrp3/top/x400/ip')
| -rw-r--r-- | fpga/usrp3/top/x400/ip/x4xx_ps_rfdc_bd/synthstub/x4xx_ps_rfdc_bd.vhd | 8 | ||||
| -rw-r--r-- | fpga/usrp3/top/x400/ip/x4xx_ps_rfdc_bd/x4xx_ps_rfdc_bd.tcl | 4 |
2 files changed, 6 insertions, 6 deletions
diff --git a/fpga/usrp3/top/x400/ip/x4xx_ps_rfdc_bd/synthstub/x4xx_ps_rfdc_bd.vhd b/fpga/usrp3/top/x400/ip/x4xx_ps_rfdc_bd/synthstub/x4xx_ps_rfdc_bd.vhd index 2fac8ad64..fd853cd53 100644 --- a/fpga/usrp3/top/x400/ip/x4xx_ps_rfdc_bd/synthstub/x4xx_ps_rfdc_bd.vhd +++ b/fpga/usrp3/top/x400/ip/x4xx_ps_rfdc_bd/synthstub/x4xx_ps_rfdc_bd.vhd @@ -3,7 +3,7 @@ -- File: x4xx_ps_rfdc_bd.vhd -- Author: niBlockDesign::niBdExportStub -- Original Project: HwBuildTools --- Date: 03 February 2021 +-- Date: 27 September 2021 -- ------------------------------------------------------------------------------------------ -- (c) Copyright National Instruments Corporation @@ -226,9 +226,9 @@ port ( dac0_clk_clk_p : in STD_LOGIC; dac1_clk_clk_n : in STD_LOGIC; dac1_clk_clk_p : in STD_LOGIC; - gpio_0_tri_i : in STD_LOGIC_VECTOR ( 31 downto 0 ); - gpio_0_tri_o : out STD_LOGIC_VECTOR ( 31 downto 0 ); - gpio_0_tri_t : out STD_LOGIC_VECTOR ( 31 downto 0 ); + gpio_0_tri_i : in STD_LOGIC_VECTOR ( 63 downto 0 ); + gpio_0_tri_o : out STD_LOGIC_VECTOR ( 63 downto 0 ); + gpio_0_tri_t : out STD_LOGIC_VECTOR ( 63 downto 0 ); m_axi_eth_internal_awaddr : out STD_LOGIC_VECTOR ( 39 downto 0 ); m_axi_eth_internal_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 ); m_axi_eth_internal_awvalid : out STD_LOGIC_VECTOR ( 0 to 0 ); diff --git a/fpga/usrp3/top/x400/ip/x4xx_ps_rfdc_bd/x4xx_ps_rfdc_bd.tcl b/fpga/usrp3/top/x400/ip/x4xx_ps_rfdc_bd/x4xx_ps_rfdc_bd.tcl index 23eedcb0e..49ced978e 100644 --- a/fpga/usrp3/top/x400/ip/x4xx_ps_rfdc_bd/x4xx_ps_rfdc_bd.tcl +++ b/fpga/usrp3/top/x400/ip/x4xx_ps_rfdc_bd/x4xx_ps_rfdc_bd.tcl @@ -2509,9 +2509,9 @@ proc create_hier_cell_ps { parentCell nameHier } { CONFIG.PSU__GPIO1_MIO__IO {MIO 26 .. 51} \ CONFIG.PSU__GPIO1_MIO__PERIPHERAL__ENABLE {1} \ CONFIG.PSU__GPIO2_MIO__PERIPHERAL__ENABLE {0} \ - CONFIG.PSU__GPIO_EMIO_WIDTH {32} \ + CONFIG.PSU__GPIO_EMIO_WIDTH {64} \ CONFIG.PSU__GPIO_EMIO__PERIPHERAL__ENABLE {1} \ - CONFIG.PSU__GPIO_EMIO__PERIPHERAL__IO {32} \ + CONFIG.PSU__GPIO_EMIO__PERIPHERAL__IO {64} \ CONFIG.PSU__GPIO_EMIO__WIDTH {[91:0]} \ CONFIG.PSU__GPU_PP0__POWER__ON {0} \ CONFIG.PSU__GPU_PP1__POWER__ON {0} \ |