x300 fpga: updating FPGA code with latest bug fixes

6 files changed, 3432 insertions, 3411 deletions

diff --git a/fpga/usrp3/top/x300/bus_int.v b/fpga/usrp3/top/x300/bus_int.v
index 17c708f66..aa5998bd3 100644
--- a/fpga/usrp3/top/x300/bus_int.v
+++ b/fpga/usrp3/top/x300/bus_int.v
@@ -43,8 +43,8 @@ module bus_int
     inout SFPP1_RS0,
     inout SFPP1_RS1,
     //
-    input [3:0] clock_status,
-    output [5:0] clock_control,
+    input [4:0] clock_status,
+    output [6:0] clock_control,
     // ETH0
     output [63:0] eth0_tx_tdata, output [3:0] eth0_tx_tuser, output eth0_tx_tlast, output eth0_tx_tvalid, input eth0_tx_tready,
     input [63:0] eth0_rx_tdata, input [3:0] eth0_rx_tuser, input eth0_rx_tlast, input eth0_rx_tvalid, output eth0_rx_tready,
@@ -141,7 +141,7 @@ module bus_int
    localparam RB_BIST         = 8'd128;
 
 
-   localparam COMPAT_MAJOR    = 16'h0003;
+   localparam COMPAT_MAJOR    = 16'h0004;
    localparam COMPAT_MINOR    = 16'h0000;
 
    wire [31:0] 	  set_data;
@@ -295,8 +295,8 @@ module bus_int
       .strobe(set_stb), .addr(set_addr), .in(set_data),
       .out(sw_rst));
 
-   setting_reg #(.my_addr(SR_CLOCK_CTRL), .awidth(SR_AWIDTH), .width(6),
-        .at_reset(6'b100000) //bit 5 high means GPSDO on by default
+   setting_reg #(.my_addr(SR_CLOCK_CTRL), .awidth(SR_AWIDTH), .width(7),
+        .at_reset(7'b1000000) //bit 6 high means GPSDO on by default
     ) set_clk_ctrl
      (.clk(clk), .rst(reset),
       .strobe(set_stb), .addr(set_addr), .in(set_data),
@@ -341,7 +341,7 @@ module bus_int
        RB_COUNTER: rb_data = counter;
        RB_SPI_RDY: rb_data = {31'b0, spi_ready};
        RB_SPI_DATA: rb_data = rb_spi_data;
-       RB_CLK_STATUS: rb_data = {28'b0, clock_status};
+       RB_CLK_STATUS: rb_data = {27'b0, clock_status};
        // SFPP Interface pins.
        RB_SFPP_STATUS0: rb_data = {26'b0,SFPP0_ModAbs_chgd,SFPP0_TxFault_chgd,SFPP0_RxLOS_chgd,
 				  SFPP0_ModAbs_reg2,SFPP0_TxFault_reg2,SFPP0_RxLOS_reg2};
diff --git a/fpga/usrp3/top/x300/capture_ddrlvds.v b/fpga/usrp3/top/x300/capture_ddrlvds.v
index c33f78339..193caf6e1 100644
--- a/fpga/usrp3/top/x300/capture_ddrlvds.v
+++ b/fpga/usrp3/top/x300/capture_ddrlvds.v
@@ -7,7 +7,7 @@
 
 module capture_ddrlvds
   #(parameter WIDTH=7,
-    parameter B250=0)
+    parameter X300=0)
    (input clk,
     input reset,
     input ssclk_p,
@@ -20,15 +20,15 @@ module capture_ddrlvds
    wire 		   ssclk;
    wire [(2*WIDTH)-1:0]    out_pre1;
    wire 		   ssclk_bufio1, ssclk_bufio2, ssclk_bufr, ssclk_bufmr;
-   
-   IBUFGDS #(.DIFF_TERM("TRUE")) 
+
+   IBUFGDS #(.DIFF_TERM("TRUE"))
    clkbuf (.O(ssclk), .I(ssclk_p), .IB(ssclk_n));
 
    BUFMR clkbufmr (
 		   .I(ssclk),
 		   .O(ssclk_bufmr)
 		   );
-  
+
    BUFIO clkbufio1 (
 		    .I(ssclk_bufmr),
 		    .O(ssclk_bufio1)
@@ -37,22 +37,22 @@ module capture_ddrlvds
 		    .I(ssclk_bufmr),
 		    .O(ssclk_bufio2)
 		    );
-  
-   BUFR     
+
+   BUFR
      #(.SIM_DEVICE("7SERIES"),
        .BUFR_DIVIDE("BYPASS"))
    clkbufr (
 	    .I(ssclk_bufmr),
 	    .O(ssclk_bufr)
 	    );
-   
+
 
    genvar 		   i;
-   
+
    generate
       for(i = 0; i < WIDTH; i = i + 1)
 	begin : gen_lvds_pins
-	   if ((i == 10) && (B250 == 1)) begin
+	   if ((i == 10) && (X300 == 1)) begin
 	      IBUFDS #(.DIFF_TERM("FALSE")) ibufds
 		(.O(ddr_dat[i]), .I(in_p[i]), .IB(in_n[i]) );
 	      IDDR #(.DDR_CLK_EDGE("SAME_EDGE_PIPELINED")) iddr
@@ -68,12 +68,12 @@ module capture_ddrlvds
 	end
    endgenerate
 
-   
-   
+
+
    reg rd_en;
    wire full, empty, almost_empty;
-   
-   
+
+
    input_sample_fifo  input_sample_fifo_i
      (
       .rst(reset), // input rst
@@ -88,7 +88,7 @@ module capture_ddrlvds
       .almost_empty(almost_empty) // output almost_empty
       );
 
-   
+
    always @(posedge clk) begin
       if (reset)
 	rd_en <= 0;
diff --git a/fpga/usrp3/top/x300/coregen/bootram.coe b/fpga/usrp3/top/x300/coregen/bootram.coe
index 98796a4c6..c9045183a 100755
--- a/fpga/usrp3/top/x300/coregen/bootram.coe
+++ b/fpga/usrp3/top/x300/coregen/bootram.coe
@@ -2,15 +2,15 @@ memory_initialization_radix=16;
 memory_initialization_vector=
 0b0b0b0b,
 82700b0b,
-8186f40c,
+81978c0c,
 3a0b0b80,
-eef50400,
+ff8c0400,
 00000000,
 00000000,
 00000000,
 80088408,
 88080b0b,
-80efc02d,
+80ffd72d,
 880c840c,
 800c0400,
 00000000,
@@ -161,8 +161,8 @@ c4040000,
 00000000,
 00000000,
 71fc0608,
-0b0b8186,
-e0738306,
+0b0b8196,
+f8738306,
 10100508,
 060b0b0b,
 88aa0400,
@@ -170,16 +170,16 @@ e0738306,
 00000000,
 80088408,
 88087575,
-0b0b80e7,
-dd2d5050,
+0b0b80f6,
+b12d5050,
 80085688,
 0c840c80,
 0c510400,
 00000000,
 80088408,
 88087575,
-0b0b80e9,
-8f2d5050,
+0b0b80f7,
+e32d5050,
 80085688,
 0c840c80,
 0c510400,
@@ -209,7 +209,7 @@ dd2d5050,
 00000000,
 00000000,
 810b0b0b,
-8186f00c,
+8197880c,
 51040000,
 00000000,
 00000000,
@@ -257,7 +257,7 @@ dd2d5050,
 00000000,
 00000000,
 82813f80,
-e8e13f04,
+f8f83f04,
 10101010,
 10101010,
 10101010,
@@ -280,56 +280,56 @@ fc060c51,
 0a100a53,
 72ed3851,
 51535104,
-8186f008,
+81978808,
 802ea438,
-8186f408,
+81978c08,
 822ebd38,
 8380800b,
-0b0b818e,
-e80c82a0,
-800b818e,
-ec0c8290,
-800b818e,
-f00c04f8,
+0b0b819f,
+800c82a0,
+800b819f,
+840c8290,
+800b819f,
+880c04f8,
 808080a4,
 0b0b0b81,
-8ee80cf8,
+9f800cf8,
 80808280,
-0b818eec,
+0b819f84,
 0cf88080,
 84800b81,
-8ef00c04,
+9f880c04,
 80c0a880,
 8c0b0b0b,
-818ee80c,
+819f800c,
 80c0a880,
-940b818e,
-ec0c0b0b,
-80f1940b,
-818ef00c,
+940b819f,
+840c0b0b,
+8181ac0b,
+819f880c,
 04ff3d0d,
-818ef433,
+819f8c33,
 5170a738,
-8186fc08,
+81979408,
 70085252,
 70802e94,
 38841281,
-86fc0c70,
-2d8186fc,
+97940c70,
+2d819794,
 08700852,
 5270ee38,
-810b818e,
-f434833d,
+810b819f,
+8c34833d,
 0d040480,
 3d0d0b0b,
-818ee408,
+819efc08,
 802e8e38,
 0b0b0b0b,
 800b802e,
 09810685,
 38823d0d,
 040b0b81,
-8ee4510b,
+9efc510b,
 0b0bf5d4,
 3f823d0d,
 0404f93d,
@@ -354,855 +354,939 @@ b1387218,
 73833877,
 5170800c,
 893d0d04,
-ff3d0d02,
-93053352,
-83f28051,
-97863f83,
-3d0d04e2,
-3d0d8bef,
-5283fa80,
-5196e93f,
+04e23d0d,
 8bef5283,
-f2805196,
-df3f8b88,
-528051a1,
-8d3f81af,
-5280f19c,
-51a18e3f,
-80d3b993,
-c05283fc,
-80519785,
-3f80d3b9,
-93c05283,
-fe805196,
-f83f80d3,
+fa805198,
+c43f8bef,
+5283f280,
+5198ba3f,
+8b885280,
+51a2e93f,
+81af5281,
+81b451a2,
+ea3f80d3,
 b993c052,
-83f88051,
-96eb3f81,
-0b82c084,
-0c82c090,
-08558a56,
-74812e83,
-38815675,
-5280f1c8,
-51a0ca3f,
-82c09408,
-558a5674,
-812e8338,
-81567552,
-80f1e051,
-a0b33fbf,
-fc538280,
-8052818e,
-f851a1ca,
-3f818ef8,
-085280f1,
-f851a099,
-3f818ef8,
-51a68e3f,
-8d3d5b80,
-cc538187,
-80527a51,
-80dffe3f,
-825480f1,
-985380d0,
+83fc8051,
+98e03f80,
+d3b993c0,
 5283fe80,
-5197c03f,
-80cc547a,
-5380d052,
-83fe8051,
-96983f82,
+5198d33f,
+80d3b993,
+c05283f8,
+805198c6,
+3f810b82,
+c0840c82,
 c0900855,
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+813f8d3d,
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+547a5380,
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+ac115358,
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+538197b4,
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+11535855,
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+8197b415,
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+0879557a,
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+8051a6c9,
+3f841633,
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+2b720782,
+1a337098,
+2b720782,
+c1c00c7a,
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 71882b07,
-831a3370,
-902b7207,
-821c3370,
-982b7207,
-82c2800c,
-7c33811e,
-3371882b,
-0782c284,
-0c600882,
-c2880c55,
-5d525956,
-5c800b82,
-c2900c9e,
-800b82c2,
-940c800b,
-82c0840c,
-80e45180,
-c7de3f82,
-c0900855,
-74812e09,
-81068638,
-8051b4f9,
-3f82c094,
+82c1c40c,
+7f0882c1,
+c80c535d,
+5252565c,
+800b82c1,
+d00c9e80,
+0b82c1d4,
+0c76547a,
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+51a5fa3f,
+84183385,
+19337188,
+2b07831a,
+3370902b,
+7207821c,
+3370982b,
+720782c2,
+800c7c33,
+811e3371,
+882b0782,
+c2840c60,
+0882c288,
+0c555d52,
+59565c80,
+0b82c290,
+0c9e800b,
+82c2940c,
+800b82c0,
+840c80e4,
+5180c9c7,
+3f82c090,
 08557481,
 2e098106,
-86387451,
-b4e73f80,
-5580e939,
-7451a1c9,
-3f800851,
-80d4fe3f,
-80085374,
-5280f28c,
-519cee3f,
-7451a19c,
-3f800851,
-80d58c3f,
-80085374,
-5280f2a0,
-519cd63f,
-7451a3a8,
-3f800851,
-80d4f43f,
-80085374,
-5280f2b4,
-519cbe3f,
-7451a3a5,
-3f800851,
-80d4dc3f,
-80085374,
-5280f2c8,
-519ca63f,
-81157081,
-ff065155,
-b28a3f80,
-087524ff,
-8f38a03d,
-0d04f53d,
-0d7e6002,
-8805b705,
-3371545b,
-5b54a0dd,
-3f800858,
-a8557880,
-2e8338b8,
-5573902a,
+86388051,
+b6e23f82,
+c0940855,
+74812e09,
+81068638,
+7451b6d0,
+3f805580,
+e9397451,
+a3a53f80,
+085180d6,
+e73f8008,
+53745281,
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+c63f7451,
+a2f83f80,
+085180d6,
+f53f8008,
+53745281,
+82b8519e,
+ae3f7451,
+a5873f80,
+085180d6,
+dd3f8008,
+53745281,
+82cc519e,
+963f7451,
+a5843f80,
+085180d6,
+c53f8008,
+53745281,
+82e0519d,
+fe3f8115,
 7081ff06,
-70557554,
-80f2dc53,
-51579bdd,
-3f7851a0,
-a03f7482,
-2b82c080,
-11800833,
-80088105,
-3371882b,
-07720c82,
-c0841380,
-08820533,
-80088305,
-3371982b,
-71902b07,
-80088405,
-3370882b,
-72078008,
-85053371,
-07760c52,
-82c08818,
-615a5553,
-5a415252,
-5d57559f,
-bb3f8008,
-08760c82,
-c08c1502,
-840580c6,
-0522710c,
-5482c090,
-1577710c,
-5482c094,
-157a0871,
-0c5682c0,
-98150284,
-0580c205,
-22793371,
-902b7188,
-2b07811c,
-33710774,
+5155b3f3,
+3f800875,
+24ff8f38,
+a03d0d04,
+f53d0d7e,
+60028805,
+b7053371,
+545b5b54,
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+0858a855,
+78802e83,
+38b85573,
+902a7081,
+ff067055,
+75548182,
+f4535157,
+9db53f78,
+51a1fc3f,
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+c0801180,
+08338008,
+81053371,
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+0c82c084,
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+05338008,
+83053371,
+982b7190,
+2b078008,
+84053370,
+882b7207,
+80088505,
+33710776,
 0c5282c0,
-9c18821c,
-33831d33,
-71982b71,
-902b0784,
-1f337088,
-2b720760,
-85053371,
-07760c52,
-55555540,
-58595556,
-8d3d0d04,
-fb3d0d7c,
-5675802e,
-9d388416,
-08028405,
-ae052256,
-028405aa,
-05225579,
-5452029f,
-053351fd,
-e53f873d,
-0d04f23d,
-0d655a79,
-802e81b2,
-388c3d5b,
-90537952,
-7a5180d9,
-d43f668f,
-2688387b,
-82075c80,
-f4397908,
-832a7081,
-06515776,
-802eac38,
-881a0870,
-942a7081,
-06515858,
-76802e98,
-38828080,
-54805390,
-3dfc0552,
-77bfffff,
-065180c4,
-d63f8439,
-77085f79,
-08822a70,
-81065157,
-76802ead,
-38881a08,
-70942a70,
-81068c1d,
-085c5158,
-5876802e,
-95388280,
-80548053,
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+79527a51,
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+ac38881a,
+0870942a,
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+58587680,
+2e983882,
+80805480,
+53903dfc,
+055277bf,
 ffff0651,
-80c3b73f,
-84397878,
-0c790881,
-06577680,
-2e9c3890,
-567a5502,
-80ce0522,
-540280d2,
-05225361,
-520280c3,
-053351a6,
-a53f903d,
-0d048c08,
-028c0cf0,
-3d0d8c08,
-9c050802,
-84058c08,
-f8050c8c,
-08ec050c,
-800b8c08,
-fc050c8c,
-08ec0508,
-802e86d3,
-388c08a0,
-05088f26,
-8b38820b,
-8c08fc05,
-0c868839,
-8c08ec05,
-08087082,
+80c6bf3f,
+84397708,
+5f790882,
 2a708106,
-518c08d4,
-050c8c08,
-d8050c8c,
-08d40508,
-802e9138,
-80c78a3f,
-80088106,
-8c08dc05,
-0c85c539,
-8c08d805,
-08832a70,
-8106518c,
-08d4050c,
-8c08d405,
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-00000000,
-00000000,
-00000000,
-00000000,
-00000000,
-00000000,
-00000000,
-00000000,
-00000000,
-00000000,
-00000000,
-00000000,
-00000000,
-00000000,
-00000000,
-00000000,
-00000000,
-00000000,
-00000000,
-00000000,
-00000000,
-00000000,
-00000000,
-00000000,
-00000000,
-00000000,
-00000000,
-00000000,
-00000000,
-00000000,
-00000000,
-00000000,
-00000000,
-00000000,
-00000000,
-00000000,
-00000000,
-00000000,
-00000000,
-00000000,
-00000000,
-00000000,
-00000000,
-00000000,
-00000000,
-00000000,
-00000000,
-00000000,
-00000000,
-00000000,
-00000000,
-00000000,
-00000000,
-00000000,
-00000000,
-00000000,
-00000000,
-00000000,
-00000000,
-00000000,
-00000000,
-00000000,
-00000000,
-00000000,
-00000000,
-00000000,
-00000000,
-00000000,
-00000000,
-00000000,
-00000000,
-00000000,
-00000000,
-00000000,
-00000000,
-00000000,
-00000000,
-00000000,
-00000000,
-00000000,
-00000000,
-00000000,
-00000000,
-00000000,
-00000000,
-00000000,
-00000000,
-00000000,
-00000000,
-00000000,
-00000000,
-00000000,
-00000000,
-00000000,
-00000000,
-00000000,
-00000000,
-00000000,
-00000000,
-00000000,
-00000000,
-00000000,
-00000000,
-00000000,
-00000000,
-00000000,
-00000000,
-00000000,
-00000000,
-00000000,
-00000000,
-00000000,
-00000000,
-00000000,
-00000000,
-00000000,
-00000000,
-00000000,
-00000000,
-00000000,
-00000000,
-00000000,
-00000000,
-00000000,
-00000000,
-00000000,
-00000000,
-00000000,
-00000000,
-00000000,
-00000000,
-00000000,
-00000000,
-00000000,
-00000000,
-00000000,
-00000000,
-00000000,
-00000000,
-00000000,
-00000000,
-00000000,
-00000000,
-00000000,
-00000000,
-00000000,
-00000000,
-00000000,
-00000000,
-00000000,
-00000000,
-00000000,
-00000000,
-00000000,
-00000000,
-00000000,
-00000000,
-00000000,
-00000000,
-00000000,
-00000000,
-00000000,
-00000000,
-00000000,
-00000000,
-00000000,
-00000000,
-00000000,
-00000000,
-00000000,
-00000000,
-00000000,
-00000000,
-00000000,
-00000000,
-00000000,
-00000000,
-00000000,
-00000000,
-00000000,
-00000000,
-00000000,
-00000000,
-00000000,
-00000000,
-00000000,
-00000000,
-00000000,
-00000000,
-00000000,
-00000000,
-00000000,
-00000000,
-00000000,
-00000000,
-00000000,
-00000000,
-00000000,
-00000000,
-00000000,
-00000000,
-00000000,
-00000000,
-00000000,
-00000000,
-00000000,
-00000000,
-00000000,
-00000000,
-00000000,
-00000000,
-00000000,
-00000000,
-00000000,
-00000000,
-00000000,
-00000000,
-00000000,
-00000000,
-00000000,
-00000000,
-00000000,
-00000000,
-00000000,
-00000000,
-00000000,
-00000000,
-00000000,
-00000000,
-00000000,
-00000000,
-00000000,
-00000000,
-00000000,
-00000000,
-00000000,
-00000000,
-00000000,
-00000000,
-00000000,
-00000000,
-00000000,
-00000000,
-00000000,
-00000000,
-00000000,
-00000000,
 00000000;
\ No newline at end of file
diff --git a/fpga/usrp3/top/x300/coregen/ten_gig_eth_pcs_pma/example_design/ten_gig_eth_pcs_pma_x300_top.v b/fpga/usrp3/top/x300/coregen/ten_gig_eth_pcs_pma/example_design/ten_gig_eth_pcs_pma_x300_top.v
index bf430b9ea..446fb035b 100644
--- a/fpga/usrp3/top/x300/coregen/ten_gig_eth_pcs_pma/example_design/ten_gig_eth_pcs_pma_x300_top.v
+++ b/fpga/usrp3/top/x300/coregen/ten_gig_eth_pcs_pma/example_design/ten_gig_eth_pcs_pma_x300_top.v
@@ -4,13 +4,13 @@
 //-----------------------------------------------------------------------------
 // File       : ten_gig_eth_pcs_pma_example_design.v
 //-----------------------------------------------------------------------------
-// Description: This file is a wrapper for the 10GBASE-R core; it contains all 
+// Description: This file is a wrapper for the 10GBASE-R core; it contains all
 // of the clock buffers required for implementing the block level
 //-----------------------------------------------------------------------------
 // (c) Copyright 2009 - 2012 Xilinx, Inc. All rights reserved.
 //
 // This file contains confidential and proprietary information
-// of Xilinx, Inc. and is protected under U.S. and 
+// of Xilinx, Inc. and is protected under U.S. and
 // international copyright and other intellectual property
 // laws.
 //
@@ -62,7 +62,7 @@ module ten_gig_eth_pcs_pma_x300_top
 //  input           refclk_p,
 //  input           refclk_n,
   input refclk156,
-  input refclk156_buf,   
+  input refclk156_buf,
   output          clk156,
   input           reset,
   input  [63 : 0] xgmii_txd,
@@ -87,37 +87,37 @@ module ten_gig_eth_pcs_pma_x300_top
 
   // Signal declarations
   wire clk156;
-  
+
   // Sync the global reset to the relevant clocks
   reg core_reset_tx;
   reg core_reset_rx;
   reg txreset322;
   reg rxreset322;
   reg dclk_reset;
-  
+
   reg core_reset_tx_tmp;
   reg core_reset_rx_tmp;
   reg txreset322_tmp;
   reg rxreset322_tmp;
   reg dclk_reset_tmp;
-  
+
   (* KEEP = "true" *)
   wire txclk322;
   wire rxclk322;
   wire dclk;
-  
+
   wire tx_resetdone_int;
   wire rx_resetdone_int;
   reg [63:0] xgmii_txd_reg;
   reg [7:0] xgmii_txc_reg;
   wire [63:0] xgmii_rxd_int;
   wire [7:0] xgmii_rxc_int;
-  
+
   wire mdio_out_int;
   wire mdio_tri_int;
 
   assign resetdone = tx_resetdone_int && rx_resetdone_int;
-  
+
   //synthesis attribute async_reg of core_reset_tx_tmp is "true";
   //synthesis attribute async_reg of core_reset_tx is "true";
   //synthesis attribute async_reg of core_reset_rx_tmp is "true";
@@ -135,19 +135,19 @@ module ten_gig_eth_pcs_pma_x300_top
     begin
       // Hold core in reset until everything else is ready...
 // IJB. Per AR# 53443 changed these lines:
-//      core_reset_tx_tmp <= (!(tx_resetdone_int) || reset || 
+//      core_reset_tx_tmp <= (!(tx_resetdone_int) || reset ||
 //                        tx_fault || !(signal_detect) );
        core_reset_tx_tmp <= (!(tx_resetdone_int) || reset);
-       
+
       core_reset_tx <= core_reset_tx_tmp;
-//      core_reset_rx_tmp <= (!(rx_resetdone_int) || reset || 
+//      core_reset_rx_tmp <= (!(rx_resetdone_int) || reset ||
 //                        tx_fault || !(signal_detect) );
        core_reset_rx_tmp <= (!(rx_resetdone_int) || reset  || !(signal_detect));
-       
+
       core_reset_rx <= core_reset_rx_tmp;
     end
-  end     
-    
+  end
+
   //synthesis attribute async_reg of txreset322_tmp is "true";
   //synthesis attribute async_reg of txreset322 is "true";
   always @(posedge reset or posedge txclk322)
@@ -163,7 +163,7 @@ module ten_gig_eth_pcs_pma_x300_top
       txreset322 <= txreset322_tmp;
     end
   end
-  
+
   //synthesis attribute async_reg of rxreset322_tmp is "true";
   //synthesis attribute async_reg of rxreset322 is "true";
   always @(posedge reset or posedge rxclk322)
@@ -179,7 +179,7 @@ module ten_gig_eth_pcs_pma_x300_top
       rxreset322 <= rxreset322_tmp;
     end
   end
-  
+
   //synthesis attribute async_reg of dclk_reset_tmp is "true";
   //synthesis attribute async_reg of dclk_reset is "true";
   always @(posedge reset or posedge dclk)
@@ -194,28 +194,28 @@ module ten_gig_eth_pcs_pma_x300_top
       dclk_reset_tmp <= core_reset_rx;
       dclk_reset <= dclk_reset_tmp;
     end
-  end   
-   
+  end
+
   // Add a pipeline to the xmgii_tx inputs, to aid timing closure
   always @(posedge clk156)
   begin
-    xgmii_txd_reg <= xgmii_txd; 
-    xgmii_txc_reg <= xgmii_txc; 
+    xgmii_txd_reg <= xgmii_txd;
+    xgmii_txc_reg <= xgmii_txc;
   end
 
   // Add a pipeline to the xmgii_rx outputs, to aid timing closure
   always @(posedge clk156)
   begin
-    xgmii_rxd <= xgmii_rxd_int; 
-    xgmii_rxc <= xgmii_rxc_int; 
+    xgmii_rxd <= xgmii_rxd_int;
+    xgmii_rxc <= xgmii_rxc_int;
   end
 
   // Add a pipeline to the mdio outputs, to aid timing closure
   // This is safe because the mdio clock is running so slowly
   always @(posedge clk156)
   begin
-    mdio_out <= mdio_out_int; 
-    mdio_tri <= mdio_tri_int; 
+    mdio_out <= mdio_out_int;
+    mdio_tri <= mdio_tri_int;
   end
 
   // Instantiate the 10GBASE-R Block Level
@@ -256,10 +256,10 @@ module ten_gig_eth_pcs_pma_x300_top
       .signal_detect(signal_detect),
       .tx_fault(tx_fault),
       .tx_disable(tx_disable));
- 
+
  // assign core_clk156_out = clk156;
-   
-   // Not needed in B250
+
+   // Not needed in X300
 /* -----\/----- EXCLUDED -----\/-----
 
   ODDR #(.DDR_CLK_EDGE("SAME_EDGE")) rx_clk_ddr(
diff --git a/fpga/usrp3/top/x300/x300.v b/fpga/usrp3/top/x300/x300.v
index aa77d1bc7..10409c607 100644
--- a/fpga/usrp3/top/x300/x300.v
+++ b/fpga/usrp3/top/x300/x300.v
@@ -314,13 +314,13 @@ module x300
    //////////////////////////////////////////////////////////////////////
    // CPRI Clock output -- this is the dirty recovered clock from the MGT
    // This goes to the LMK04816 which locks to it and cleans it up
-   // We get the clean versions back as CPRI_CLK (for the CPRI MGT) 
+   // We get the clean versions back as CPRI_CLK (for the CPRI MGT)
    // and FPGA_CLK (for our main rfclk)
    //////////////////////////////////////////////////////////////////////
 
    wire cpri_clk_out = 1'b0; // FIXME - connect to CPRI clock recovery when implemented
    OBUFDS OBUFDS_cpri (.I(cpri_clk_out), .O(CPRI_CLK_OUT_P), .OB(CPRI_CLK_OUT_N));
-   
+
    /////////////////////////////////////////////////////////////////////
    //
    // power-on-reset logic.
@@ -365,7 +365,7 @@ module x300
    // after programming the AD9610.
    //
    ////////////////////////////////////////////////////////////////////
-   
+
    reset_sync radio_reset_sync
      (
       .clk(radio_clk),
@@ -381,8 +381,40 @@ module x300
       );
 
    ////////////////////////////////////////////////////////////////////
+   // PPS
+   // Support for internal, external, and GPSDO PPS inputs
+   // Every attempt to minimize propagation between the external PPS
+   // input and outputs to support daisy-chaining the signal.
+   ////////////////////////////////////////////////////////////////////
+
+   // Generate an internal PPS signal with a 25% duty cycle
+   reg [31:0] pps_count;
+   wire int_pps = (pps_count < 32'd2500000);
+   always @(posedge ref_clk_10mhz) begin
+      if (pps_count >= 32'd9999999)
+         pps_count <= 32'b0;
+      else
+         pps_count <= pps_count + 1'b1;
+   end
+
+   // PPS MUX - selects internal, external, or gpsdo PPS
+   reg pps;
+   wire [1:0] pps_select;
+   wire pps_out_enb;
+   always @(*) begin
+      case(pps_select)
+         2'b00  :   pps = EXT_PPS_IN;
+         2'b01  :   pps = 1'b0;
+         2'b10  :   pps = int_pps;
+         2'b11  :   pps = GPS_PPS_OUT;
+         default:   pps = 1'b0;
+      endcase
+   end
+
+   // PPS out and LED
+   assign EXT_PPS_OUT = pps & pps_out_enb;
+   assign LED_PPS = ~pps;                                  // active low LED driver
 
-   assign LED_PPS = ~(GPS_PPS_OUT | EXT_PPS_IN);
    assign LED_GPSLOCK = ~GPS_LOCK_OK;
    assign LED_REFLOCK = ~LMK_Lock;
    assign {LED_RX1_RX,LED_TXRX1_TX,LED_TXRX1_RX} = ~led0;  // active low LED driver
@@ -451,7 +483,7 @@ module x300
    // Analog diff pairs on I side of ADC are inverted for layout reasons, but data diff pairs are all swapped as well
    //  so I gets a double negative, and is unchanged.  Q must be inverted.
 
-   capture_ddrlvds #(.WIDTH(14),.B250(1)) cap_db0
+   capture_ddrlvds #(.WIDTH(14),.X300(1)) cap_db0
      (.clk(radio_clk), .reset(radio_rst), .ssclk_p(DB0_ADC_DCLK_P), .ssclk_n(DB0_ADC_DCLK_N),
       .in_p({{DB0_ADC_DA6_P, DB0_ADC_DA5_P, DB0_ADC_DA4_P, DB0_ADC_DA3_P, DB0_ADC_DA2_P, DB0_ADC_DA1_P, DB0_ADC_DA0_P},
          {DB0_ADC_DB6_P, DB0_ADC_DB5_P, DB0_ADC_DB4_P, DB0_ADC_DB3_P, DB0_ADC_DB2_P, DB0_ADC_DB1_P, DB0_ADC_DB0_P}}),
@@ -461,7 +493,7 @@ module x300
       .out({rx0_i,rx0_q_inv}));
    assign rx0[31:0] = { rx0_i, 2'b00, ~rx0_q_inv, 2'b00 };
 
-   capture_ddrlvds #(.WIDTH(14),.B250(1)) cap_db1
+   capture_ddrlvds #(.WIDTH(14),.X300(1)) cap_db1
      (.clk(radio_clk),  .reset(radio_rst), .ssclk_p(DB1_ADC_DCLK_P), .ssclk_n(DB1_ADC_DCLK_N),
       .in_p({{DB1_ADC_DA6_P, DB1_ADC_DA5_P, DB1_ADC_DA4_P, DB1_ADC_DA3_P, DB1_ADC_DA2_P, DB1_ADC_DA1_P, DB1_ADC_DA0_P},
          {DB1_ADC_DB6_P, DB1_ADC_DB5_P, DB1_ADC_DB4_P, DB1_ADC_DB3_P, DB1_ADC_DB2_P, DB1_ADC_DB1_P, DB1_ADC_DB0_P}}),
@@ -470,7 +502,7 @@ module x300
          {DB1_ADC_DB6_N, DB1_ADC_DB5_N, DB1_ADC_DB4_N, DB1_ADC_DB3_N, DB1_ADC_DB2_N, DB1_ADC_DB1_N, DB1_ADC_DB0_N}}),
       .out({rx1_i,rx1_q_inv}));
    assign rx1[31:0] = { rx1_i, 2'b00, ~rx1_q_inv, 2'b00 };
- 
+
    /////////////////////////////////////////////////////////////////////
    //
    // DAC Interface for AD9146
@@ -1756,7 +1788,7 @@ module x300
 
    ///////////////////////////////////////////////////////////////////////////////////
    //
-   // B250 Core
+   // X300 Core
    //
    ///////////////////////////////////////////////////////////////////////////////////
    x300_core x300_core
@@ -1836,10 +1868,10 @@ module x300
       .gmii_txd1(gmii_txd1), .gmii_tx_en1(gmii_tx_en1), .gmii_tx_er1(gmii_tx_er1),
       .gmii_rxd1(gmii_rxd1), .gmii_rx_dv1(gmii_rx_dv1), .gmii_rx_er1(gmii_rx_er1),
 `endif // !`ifdef
+      // Time
+      .pps(pps),.pps_select(pps_select), .pps_out_enb(pps_out_enb),
       // GPS Signals
-      .gps_pps(GPS_PPS_OUT), .ext_pps(EXT_PPS_IN),
       .gps_txd(GPS_SER_IN), .gps_rxd(GPS_SER_OUT),
-      .pps_out(EXT_PPS_OUT),
       // Debug UART
       .debug_rxd(debug_rxd), .debug_txd(debug_txd),
       // Misc.
diff --git a/fpga/usrp3/top/x300/x300_core.v b/fpga/usrp3/top/x300/x300_core.v
index c783d34ee..4c632b95d 100644
--- a/fpga/usrp3/top/x300/x300_core.v
+++ b/fpga/usrp3/top/x300/x300_core.v
@@ -104,9 +104,9 @@ module x300_core
 `endif // !`ifdef
 
    // Time
-   input gps_pps,
-   input ext_pps,
-   output reg pps_out,
+   input pps,
+   output [1:0] pps_select,
+   output pps_out_enb,
    output gps_txd,
    input gps_rxd,
    // Debug UART
@@ -369,31 +369,20 @@ module x300_core
 
 
     /////////////////////////////////////////////////////////////////////////////////
-    // PPS synchronization and generation logic
+    // PPS synchronization logic
     /////////////////////////////////////////////////////////////////////////////////
-
     //PPS input signals will be flopped in via the 10MHz reference clock.
     //Its assumed that the radio clock, which is derived from the 10MHz,
     //will be able to flop this captured PPS signal without metastability.
     //And that the relation of the radio clock to this ref clock will be
     //consistent enough across multiple units to use for this purpose.
-    reg [1:0] 	 ext_pps_del, gps_pps_del;
-    always @(posedge ext_ref_clk) ext_pps_del[1:0] <= {ext_pps_del[0], ext_pps};
-    always @(posedge ext_ref_clk) gps_pps_del[1:0] <= {gps_pps_del[0], gps_pps};
-
-    //Generate a PPS signal disciplined by the input reference PPS.
-    //The PPS signal is 25% duty cycle, and generated by the rising edge.
-    reg pps_int;
-    wire pps_out_enb, pps_select;
-    reg [31:0] pps_count;
-    wire pps_duty_high = (pps_count < 32'd2500000);
-    wire pps_edge = pps_select? (ext_pps_del == 2'b01) : (gps_pps_del == 2'b01);
+    reg [1:0] pps_del;
+    always @(posedge ext_ref_clk)  pps_del[1:0] <= {pps_del[0], pps};
+
+    //PPS detection - toggle pps_detect on each PPS rising edge.
+    reg pps_detect;
     always @(posedge ext_ref_clk) begin
-        if (pps_edge) pps_count <= 32'd3; //delay = sampling + detection + flopping out
-        else if (pps_count == 32'd9999999) pps_count <= 32'b0;
-        else pps_count <= pps_count + 1'b1;
-        pps_out <= pps_duty_high? pps_out_enb : 1'b0;
-        pps_int <= pps_duty_high? 1'b1 : 1'b0;
+        if (pps_del == 2'b01) pps_detect <= ~pps_detect;
     end
 
    /////////////////////////////////////////////////////////////////////////////////
@@ -415,8 +404,8 @@ module x300_core
       .SFPP1_ModAbs(SFPP1_ModAbs),.SFPP1_TxFault(SFPP1_TxFault),.SFPP1_RxLOS(SFPP1_RxLOS),
       .SFPP1_RS0(SFPP1_RS0), .SFPP1_RS1(SFPP1_RS1),
       //clocky locky misc
-      .clock_status({LMK_Holdover, LMK_Lock, LMK_Status}),
-      .clock_control({clock_misc_opt[1:0], pps_out_enb, pps_select, clock_ref_sel[1:0]}),
+      .clock_status({pps_detect, LMK_Holdover, LMK_Lock, LMK_Status}),
+      .clock_control({clock_misc_opt[1:0], pps_out_enb, pps_select[1:0], clock_ref_sel[1:0]}),
       // Eth0
       .eth0_tx_tdata(eth0_tx_tdata), .eth0_tx_tuser(eth0_tx_tuser), .eth0_tx_tlast(eth0_tx_tlast),
       .eth0_tx_tvalid(eth0_tx_tvalid), .eth0_tx_tready(eth0_tx_tready),
@@ -557,7 +546,7 @@ module x300_core
       .tx_tvalid_bo(r0_tx_tvalid_bo), .tx_tready_bo(r0_tx_tready_bo),
       .tx_tdata_bi(r0_tx_tdata_bi), .tx_tlast_bi(r0_tx_tlast_bi),
       .tx_tvalid_bi(r0_tx_tvalid_bi), .tx_tready_bi(r0_tx_tready_bi),
-      .pps(pps_int), .sync_dacs(sync_dacs_radio0)
+      .pps(pps_del[1]), .sync_dacs(sync_dacs_radio0)
       );
 
      always @(posedge radio_clk)
@@ -590,7 +579,7 @@ module x300_core
       .tx_tvalid_bo(r1_tx_tvalid_bo), .tx_tready_bo(r1_tx_tready_bo),
       .tx_tdata_bi(r1_tx_tdata_bi), .tx_tlast_bi(r1_tx_tlast_bi),
       .tx_tvalid_bi(r1_tx_tvalid_bi), .tx_tready_bi(r1_tx_tready_bi),
-      .pps(pps_int), .sync_dacs(sync_dacs_radio1)
+      .pps(pps_del[1]), .sync_dacs(sync_dacs_radio1)
       );
 
    always @(posedge radio_clk)
@@ -987,7 +976,7 @@ module x300_core
 	//
 	.debug()
 	);
- 
+
    axi_dram_fifo
      #(.BASE('h2000000),
        .SIZE(24),
@@ -1107,15 +1096,15 @@ module x300_core
    // Alternate smaller internal SRAM based FIFO's for Tx when DRAM not compiled into FPGA.
    // Short FIFO's added for ease of timing closure since large FIFO's spread all over die.
    //
-   wire [63:0] r0_tx_tdata_bos; wire r0_tx_tlast_bos, r0_tx_tvalid_bos, r0_tx_tready_bos;   
+   wire [63:0] r0_tx_tdata_bos; wire r0_tx_tlast_bos, r0_tx_tvalid_bos, r0_tx_tready_bos;
    wire [63:0] r0_tx_tdata_0; wire r0_tx_tlast_0, r0_tx_tvalid_0, r0_tx_tready_0;
-   wire [63:0] r0_tx_tdata_0s; wire r0_tx_tlast_0s, r0_tx_tvalid_0s, r0_tx_tready_0s;   
+   wire [63:0] r0_tx_tdata_0s; wire r0_tx_tlast_0s, r0_tx_tvalid_0s, r0_tx_tready_0s;
    wire [63:0] r0_tx_tdata_1; wire r0_tx_tlast_1, r0_tx_tvalid_1, r0_tx_tready_1;
-   wire [63:0] r0_tx_tdata_1s; wire r0_tx_tlast_1s, r0_tx_tvalid_1s, r0_tx_tready_1s;   
+   wire [63:0] r0_tx_tdata_1s; wire r0_tx_tlast_1s, r0_tx_tvalid_1s, r0_tx_tready_1s;
    wire [63:0] r0_tx_tdata_2; wire r0_tx_tlast_2, r0_tx_tvalid_2, r0_tx_tready_2;
    wire [63:0] r0_tx_tdata_2s; wire r0_tx_tlast_2s, r0_tx_tvalid_2s, r0_tx_tready_2s;
    wire [63:0] r0_tx_tdata_bis; wire r0_tx_tlast_bis, r0_tx_tvalid_bis, r0_tx_tready_bis;
-   
+
    axi_fifo_short #(.WIDTH(65)) tx_fifo0_bos
      (
       .clk(bus_clk), .reset(bus_rst), .clear(1'b0),
@@ -1137,7 +1126,7 @@ module x300_core
       .o_tdata({r0_tx_tlast_0s,r0_tx_tdata_0s}), .o_tvalid(r0_tx_tvalid_0s), .o_tready(r0_tx_tready_0s),
       .space(), .occupied()
       );
-   
+
    axi_fifo #(.WIDTH(65), .SIZE(`SRAM_FIFO_SIZE-2)) tx_fifo0_1
      (.clk(bus_clk), .reset(bus_rst), .clear(1'b0),
       .i_tdata({r0_tx_tlast_0s,r0_tx_tdata_0s}), .i_tvalid(r0_tx_tvalid_0s), .i_tready(r0_tx_tready_0s),
@@ -1151,13 +1140,13 @@ module x300_core
       .o_tdata({r0_tx_tlast_1s,r0_tx_tdata_1s}), .o_tvalid(r0_tx_tvalid_1s), .o_tready(r0_tx_tready_1s),
       .space(), .occupied()
       );
-      
+
    axi_fifo #(.WIDTH(65), .SIZE(`SRAM_FIFO_SIZE-2)) tx_fifo0_2
      (.clk(bus_clk), .reset(bus_rst), .clear(1'b0),
       .i_tdata({r0_tx_tlast_1s,r0_tx_tdata_1s}), .i_tvalid(r0_tx_tvalid_1s), .i_tready(r0_tx_tready_1s),
       .o_tdata({r0_tx_tlast_2,r0_tx_tdata_2}), .o_tvalid(r0_tx_tvalid_2), .o_tready(r0_tx_tready_2),
       .space(), .occupied());
-   
+
    axi_fifo_short #(.WIDTH(65)) tx_fifo0_2s
      (
       .clk(bus_clk), .reset(bus_rst), .clear(1'b0),
@@ -1165,13 +1154,13 @@ module x300_core
       .o_tdata({r0_tx_tlast_2s,r0_tx_tdata_2s}), .o_tvalid(r0_tx_tvalid_2s), .o_tready(r0_tx_tready_2s),
       .space(), .occupied()
       );
-   
+
    axi_fifo #(.WIDTH(65), .SIZE(`SRAM_FIFO_SIZE-2)) tx_fifo0_3
      (.clk(bus_clk), .reset(bus_rst), .clear(1'b0),
       .i_tdata({r0_tx_tlast_2s,r0_tx_tdata_2s}), .i_tvalid(r0_tx_tvalid_2s), .i_tready(r0_tx_tready_2s),
       .o_tdata({r0_tx_tlast_bis,r0_tx_tdata_bis}), .o_tvalid(r0_tx_tvalid_bis), .o_tready(r0_tx_tready_bis),
       .space(), .occupied());
-   
+
    axi_fifo_short #(.WIDTH(65)) tx_fifo0_bis
      (
       .clk(bus_clk), .reset(bus_rst), .clear(1'b0),
@@ -1180,15 +1169,15 @@ module x300_core
       .space(), .occupied()
       );
 
-   wire [63:0] r1_tx_tdata_bos; wire r1_tx_tlast_bos, r1_tx_tvalid_bos, r1_tx_tready_bos;   
+   wire [63:0] r1_tx_tdata_bos; wire r1_tx_tlast_bos, r1_tx_tvalid_bos, r1_tx_tready_bos;
    wire [63:0] r1_tx_tdata_0; wire r1_tx_tlast_0, r1_tx_tvalid_0, r1_tx_tready_0;
-   wire [63:0] r1_tx_tdata_0s; wire r1_tx_tlast_0s, r1_tx_tvalid_0s, r1_tx_tready_0s;   
+   wire [63:0] r1_tx_tdata_0s; wire r1_tx_tlast_0s, r1_tx_tvalid_0s, r1_tx_tready_0s;
    wire [63:0] r1_tx_tdata_1; wire r1_tx_tlast_1, r1_tx_tvalid_1, r1_tx_tready_1;
-   wire [63:0] r1_tx_tdata_1s; wire r1_tx_tlast_1s, r1_tx_tvalid_1s, r1_tx_tready_1s;   
+   wire [63:0] r1_tx_tdata_1s; wire r1_tx_tlast_1s, r1_tx_tvalid_1s, r1_tx_tready_1s;
    wire [63:0] r1_tx_tdata_2; wire r1_tx_tlast_2, r1_tx_tvalid_2, r1_tx_tready_2;
    wire [63:0] r1_tx_tdata_2s; wire r1_tx_tlast_2s, r1_tx_tvalid_2s, r1_tx_tready_2s;
    wire [63:0] r1_tx_tdata_bis; wire r1_tx_tlast_bis, r1_tx_tvalid_bis, r1_tx_tready_bis;
-   
+
    axi_fifo_short #(.WIDTH(65)) tx_fifo1_bos
      (
       .clk(bus_clk), .reset(bus_rst), .clear(1'b0),
@@ -1210,7 +1199,7 @@ module x300_core
       .o_tdata({r1_tx_tlast_0s,r1_tx_tdata_0s}), .o_tvalid(r1_tx_tvalid_0s), .o_tready(r1_tx_tready_0s),
       .space(), .occupied()
       );
-   
+
    axi_fifo #(.WIDTH(65), .SIZE(`SRAM_FIFO_SIZE-2)) tx_fifo1_1
      (.clk(bus_clk), .reset(bus_rst), .clear(1'b0),
       .i_tdata({r1_tx_tlast_0s,r1_tx_tdata_0s}), .i_tvalid(r1_tx_tvalid_0s), .i_tready(r1_tx_tready_0s),
@@ -1224,13 +1213,13 @@ module x300_core
       .o_tdata({r1_tx_tlast_1s,r1_tx_tdata_1s}), .o_tvalid(r1_tx_tvalid_1s), .o_tready(r1_tx_tready_1s),
       .space(), .occupied()
       );
-      
+
    axi_fifo #(.WIDTH(65), .SIZE(`SRAM_FIFO_SIZE-2)) tx_fifo1_2
      (.clk(bus_clk), .reset(bus_rst), .clear(1'b0),
       .i_tdata({r1_tx_tlast_1s,r1_tx_tdata_1s}), .i_tvalid(r1_tx_tvalid_1s), .i_tready(r1_tx_tready_1s),
       .o_tdata({r1_tx_tlast_2,r1_tx_tdata_2}), .o_tvalid(r1_tx_tvalid_2), .o_tready(r1_tx_tready_2),
       .space(), .occupied());
-   
+
    axi_fifo_short #(.WIDTH(65)) tx_fifo1_2s
      (
       .clk(bus_clk), .reset(bus_rst), .clear(1'b0),
@@ -1238,13 +1227,13 @@ module x300_core
       .o_tdata({r1_tx_tlast_2s,r1_tx_tdata_2s}), .o_tvalid(r1_tx_tvalid_2s), .o_tready(r1_tx_tready_2s),
       .space(), .occupied()
       );
-   
+
    axi_fifo #(.WIDTH(65), .SIZE(`SRAM_FIFO_SIZE-2)) tx_fifo1_3
      (.clk(bus_clk), .reset(bus_rst), .clear(1'b0),
       .i_tdata({r1_tx_tlast_2s,r1_tx_tdata_2s}), .i_tvalid(r1_tx_tvalid_2s), .i_tready(r1_tx_tready_2s),
       .o_tdata({r1_tx_tlast_bis,r1_tx_tdata_bis}), .o_tvalid(r1_tx_tvalid_bis), .o_tready(r1_tx_tready_bis),
       .space(), .occupied());
-   
+
    axi_fifo_short #(.WIDTH(65)) tx_fifo1_bis
      (
       .clk(bus_clk), .reset(bus_rst), .clear(1'b0),
@@ -1254,7 +1243,7 @@ module x300_core
       );
 
 
- 
+
 `endif //  `ifndef NO_DRAM_FIFOS
 
    //