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authorWade Fife <wade.fife@ettus.com>2021-12-09 14:30:30 -0600
committerWade Fife <wade.fife@ettus.com>2022-03-29 14:45:04 -0500
commit6f038dc2f69b38e715206b2e700fdd3a1bbc638e (patch)
tree8fb2499be9e9a7acffd5add92a59389f3e6bb2b9 /fpga/usrp3/top/x300
parent61337817eb9c617db37fdbb16fb5f598e15a29a7 (diff)
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fpga: Use PROTOVER and CHDR_W from RFNoC image builder
This updates all RFNoC devices so that they get the RFNoC protocol version and CHDR width in the same way, from the output generated by the RFNoC image builder.
Diffstat (limited to 'fpga/usrp3/top/x300')
-rw-r--r--fpga/usrp3/top/x300/Makefile.x300.inc3
-rw-r--r--fpga/usrp3/top/x300/bus_int.v14
2 files changed, 14 insertions, 3 deletions
diff --git a/fpga/usrp3/top/x300/Makefile.x300.inc b/fpga/usrp3/top/x300/Makefile.x300.inc
index 1f18cbf02..1664869b2 100644
--- a/fpga/usrp3/top/x300/Makefile.x300.inc
+++ b/fpga/usrp3/top/x300/Makefile.x300.inc
@@ -114,13 +114,14 @@ $(RFNOC_BLOCK_REPLAY_SRCS) \
$(RFNOC_OOT_SRCS)
EDGE_TBL_DEF="RFNOC_EDGE_TBL_FILE=$(call RESOLVE_PATH,$(EDGE_FILE))"
+IMAGE_CORE_DEF="RFNOC_IMAGE_CORE_HDR=$(DEFAULT_RFNOC_IMAGE_CORE_FILE:.v=.vh)"
##################################################
# Dependency Targets
##################################################
.SECONDEXPANSION:
-VERILOG_DEFS=$(EXTRA_DEFS) $(CUSTOM_DEFS) $(GIT_HASH_VERILOG_DEF) $(EDGE_TBL_DEF)
+VERILOG_DEFS=$(EXTRA_DEFS) $(CUSTOM_DEFS) $(GIT_HASH_VERILOG_DEF) $(EDGE_TBL_DEF) $(IMAGE_CORE_DEF)
# DESIGN_SRCS and VERILOG_DEFS must be defined
bin: .prereqs $$(DESIGN_SRCS) ip
diff --git a/fpga/usrp3/top/x300/bus_int.v b/fpga/usrp3/top/x300/bus_int.v
index 90f840a4c..e97ff7ef8 100644
--- a/fpga/usrp3/top/x300/bus_int.v
+++ b/fpga/usrp3/top/x300/bus_int.v
@@ -177,7 +177,16 @@ module bus_int #(
localparam COMPAT_MINOR = 16'h0000;
localparam NUM_TIMEKEEPERS = 1;
- localparam [15:0] RFNOC_PROTOVER = {8'd1, 8'd0};
+ // Include the RFNoC image core header file
+ `ifdef RFNOC_IMAGE_CORE_HDR
+ `include `"`RFNOC_IMAGE_CORE_HDR`"
+ `else
+ ERROR_RFNOC_IMAGE_CORE_HDR_not_defined();
+ `define CHDR_WIDTH 64
+ `define RFNOC_PROTOVER { 8'd1, 8'd0 }
+ `endif
+ localparam CHDR_W = `CHDR_WIDTH;
+ localparam RFNOC_PROTOVER = `RFNOC_PROTOVER;
wire [31:0] set_data;
wire [7:0] set_addr;
@@ -733,7 +742,8 @@ module bus_int #(
///////////////////////////////////////////////////////////////////////////
rfnoc_image_core #(
- .PROTOVER(RFNOC_PROTOVER)
+ .CHDR_W (CHDR_W),
+ .PROTOVER (RFNOC_PROTOVER)
) rfnoc_sandbox_i (
.chdr_aclk (clk ),
.ctrl_aclk (clk_div2 ),