fpga: Add Replay Block to RFNoC Core Image

Add the Replay RFNoC block to the RFNoC core image for x300, x310, n300,
n310, n320/n321, and e320. The Replay block is contained within its own
static connection, so previous default behavior is still supported.

Signed-off-by: mattprost <matt.prost@ni.com>

7 files changed, 918 insertions, 176 deletions

diff --git a/fpga/usrp3/top/x300/Makefile.x300.inc b/fpga/usrp3/top/x300/Makefile.x300.inc
index a1810e628..1f18cbf02 100644
--- a/fpga/usrp3/top/x300/Makefile.x300.inc
+++ b/fpga/usrp3/top/x300/Makefile.x300.inc
@@ -37,12 +37,13 @@ include $(LIB_DIR)/axi/Makefile.srcs
 include $(LIB_DIR)/io_cap_gen/Makefile.srcs
 include $(LIB_DIR)/rfnoc/Makefile.srcs
 # For sake of convenience, we include the Makefile.srcs for DRAM FIFO, DDC, and
-# DUC, and of course the radio. Any other block needs to use the
+# DUC, Replay, and of course the radio. Any other block needs to use the
 # RFNOC_OOT_MAKEFILE_SRCS variable (see below).
 include $(LIB_DIR)/rfnoc/blocks/rfnoc_block_axi_ram_fifo/Makefile.srcs
 include $(LIB_DIR)/rfnoc/blocks/rfnoc_block_radio/Makefile.srcs
 include $(LIB_DIR)/rfnoc/blocks/rfnoc_block_ddc/Makefile.srcs
 include $(LIB_DIR)/rfnoc/blocks/rfnoc_block_duc/Makefile.srcs
+include $(LIB_DIR)/rfnoc/blocks/rfnoc_block_replay/Makefile.srcs
 # If out-of-tree modules want to be compiled into this image, then they need to
 # pass in the RFNOC_OOT_MAKEFILE_SRCS as a list of Makefile.srcs files.
 # Those files need to amend the RFNOC_OOT_SRCS variable with a list of actual
@@ -109,6 +110,7 @@ $(RFNOC_SRCS) $(LIB_IP_XCI_SRCS) \
 $(RFNOC_FRAMEWORK_SRCS) \
 $(RFNOC_BLOCK_DUC_SRCS) $(RFNOC_BLOCK_DDC_SRCS) $(RFNOC_BLOCK_RADIO_SRCS) \
 $(RFNOC_BLOCK_AXI_RAM_FIFO_SRCS) \
+$(RFNOC_BLOCK_REPLAY_SRCS) \
 $(RFNOC_OOT_SRCS)
 
 EDGE_TBL_DEF="RFNOC_EDGE_TBL_FILE=$(call RESOLVE_PATH,$(EDGE_FILE))"
diff --git a/fpga/usrp3/top/x300/x300_rfnoc_image_core.v b/fpga/usrp3/top/x300/x300_rfnoc_image_core.v
index 0c0518f5e..dc6fc4708 100644
--- a/fpga/usrp3/top/x300/x300_rfnoc_image_core.v
+++ b/fpga/usrp3/top/x300/x300_rfnoc_image_core.v
@@ -1,5 +1,5 @@
 //
-// Copyright 2019 Ettus Research, A National Instruments Brand
+// Copyright 2020 Ettus Research, A National Instruments Brand
 //
 // SPDX-License-Identifier: LGPL-3.0-or-later
 //
@@ -7,9 +7,9 @@
 // Module: rfnoc_image_core (for x300)
 // This file was autogenerated by UHD's image builder tool (rfnoc_image_builder)
 // Re-running that tool will overwrite this file!
-// File generated on: 2019-11-12T07:57:49.576474
-// Source: ./x300/x300_rfnoc_image_core.yml
-// Source SHA256: 883fe3d3773daf082a166936eec214ce68c3925a5928d7442302f8a75058d989
+// File generated on: 2020-09-02T12:02:29.163114
+// Source: ./x300_rfnoc_image_core.yml
+// Source SHA256: f64f8b03f805ae93e92c29cbdf8874c497d7ad93d546947e26fa8da501df6e18
 
 module rfnoc_image_core #(
   parameter [15:0] PROTOVER = {8'd1, 8'd0}
@@ -64,50 +64,50 @@ module rfnoc_image_core #(
   output wire [  2-1:0] radio_tx_running_radio1,
 //  dram
   input  wire [  1-1:0] axi_rst,
-  output wire [  2-1:0] m_axi_awid,
-  output wire [ 64-1:0] m_axi_awaddr,
-  output wire [ 16-1:0] m_axi_awlen,
-  output wire [  6-1:0] m_axi_awsize,
-  output wire [  4-1:0] m_axi_awburst,
-  output wire [  2-1:0] m_axi_awlock,
-  output wire [  8-1:0] m_axi_awcache,
-  output wire [  6-1:0] m_axi_awprot,
-  output wire [  8-1:0] m_axi_awqos,
-  output wire [  8-1:0] m_axi_awregion,
-  output wire [  2-1:0] m_axi_awuser,
-  output wire [  2-1:0] m_axi_awvalid,
-  input  wire [  2-1:0] m_axi_awready,
-  output wire [128-1:0] m_axi_wdata,
-  output wire [ 16-1:0] m_axi_wstrb,
-  output wire [  2-1:0] m_axi_wlast,
-  output wire [  2-1:0] m_axi_wuser,
-  output wire [  2-1:0] m_axi_wvalid,
-  input  wire [  2-1:0] m_axi_wready,
-  input  wire [  2-1:0] m_axi_bid,
-  input  wire [  4-1:0] m_axi_bresp,
-  input  wire [  2-1:0] m_axi_buser,
-  input  wire [  2-1:0] m_axi_bvalid,
-  output wire [  2-1:0] m_axi_bready,
-  output wire [  2-1:0] m_axi_arid,
-  output wire [ 64-1:0] m_axi_araddr,
-  output wire [ 16-1:0] m_axi_arlen,
-  output wire [  6-1:0] m_axi_arsize,
-  output wire [  4-1:0] m_axi_arburst,
-  output wire [  2-1:0] m_axi_arlock,
-  output wire [  8-1:0] m_axi_arcache,
-  output wire [  6-1:0] m_axi_arprot,
-  output wire [  8-1:0] m_axi_arqos,
-  output wire [  8-1:0] m_axi_arregion,
-  output wire [  2-1:0] m_axi_aruser,
-  output wire [  2-1:0] m_axi_arvalid,
-  input  wire [  2-1:0] m_axi_arready,
-  input  wire [  2-1:0] m_axi_rid,
-  input  wire [128-1:0] m_axi_rdata,
-  input  wire [  4-1:0] m_axi_rresp,
-  input  wire [  2-1:0] m_axi_rlast,
-  input  wire [  2-1:0] m_axi_ruser,
-  input  wire [  2-1:0] m_axi_rvalid,
-  output wire [  2-1:0] m_axi_rready,
+  output wire [  4-1:0] m_axi_awid,
+  output wire [128-1:0] m_axi_awaddr,
+  output wire [ 32-1:0] m_axi_awlen,
+  output wire [ 12-1:0] m_axi_awsize,
+  output wire [  8-1:0] m_axi_awburst,
+  output wire [  4-1:0] m_axi_awlock,
+  output wire [ 16-1:0] m_axi_awcache,
+  output wire [ 12-1:0] m_axi_awprot,
+  output wire [ 16-1:0] m_axi_awqos,
+  output wire [ 16-1:0] m_axi_awregion,
+  output wire [  4-1:0] m_axi_awuser,
+  output wire [  4-1:0] m_axi_awvalid,
+  input  wire [  4-1:0] m_axi_awready,
+  output wire [256-1:0] m_axi_wdata,
+  output wire [ 32-1:0] m_axi_wstrb,
+  output wire [  4-1:0] m_axi_wlast,
+  output wire [  4-1:0] m_axi_wuser,
+  output wire [  4-1:0] m_axi_wvalid,
+  input  wire [  4-1:0] m_axi_wready,
+  input  wire [  4-1:0] m_axi_bid,
+  input  wire [  8-1:0] m_axi_bresp,
+  input  wire [  4-1:0] m_axi_buser,
+  input  wire [  4-1:0] m_axi_bvalid,
+  output wire [  4-1:0] m_axi_bready,
+  output wire [  4-1:0] m_axi_arid,
+  output wire [128-1:0] m_axi_araddr,
+  output wire [ 32-1:0] m_axi_arlen,
+  output wire [ 12-1:0] m_axi_arsize,
+  output wire [  8-1:0] m_axi_arburst,
+  output wire [  4-1:0] m_axi_arlock,
+  output wire [ 16-1:0] m_axi_arcache,
+  output wire [ 12-1:0] m_axi_arprot,
+  output wire [ 16-1:0] m_axi_arqos,
+  output wire [ 16-1:0] m_axi_arregion,
+  output wire [  4-1:0] m_axi_aruser,
+  output wire [  4-1:0] m_axi_arvalid,
+  input  wire [  4-1:0] m_axi_arready,
+  input  wire [  4-1:0] m_axi_rid,
+  input  wire [256-1:0] m_axi_rdata,
+  input  wire [  8-1:0] m_axi_rresp,
+  input  wire [  4-1:0] m_axi_rlast,
+  input  wire [  4-1:0] m_axi_ruser,
+  input  wire [  4-1:0] m_axi_rvalid,
+  output wire [  4-1:0] m_axi_rready,
   // Transport 0 (eth0 10G)
   input  wire [64-1:0]  s_eth0_tdata,
   input  wire         s_eth0_tlast,
@@ -179,10 +179,26 @@ module rfnoc_image_core #(
   wire              ep3_to_xb_tlast ;
   wire              ep3_to_xb_tvalid;
   wire              ep3_to_xb_tready;
+  wire [CHDR_W-1:0] xb_to_ep4_tdata ;
+  wire              xb_to_ep4_tlast ;
+  wire              xb_to_ep4_tvalid;
+  wire              xb_to_ep4_tready;
+  wire [CHDR_W-1:0] ep4_to_xb_tdata ;
+  wire              ep4_to_xb_tlast ;
+  wire              ep4_to_xb_tvalid;
+  wire              ep4_to_xb_tready;
+  wire [CHDR_W-1:0] xb_to_ep5_tdata ;
+  wire              xb_to_ep5_tlast ;
+  wire              xb_to_ep5_tvalid;
+  wire              xb_to_ep5_tready;
+  wire [CHDR_W-1:0] ep5_to_xb_tdata ;
+  wire              ep5_to_xb_tlast ;
+  wire              ep5_to_xb_tvalid;
+  wire              ep5_to_xb_tready;
 
   chdr_crossbar_nxn #(
     .CHDR_W         (CHDR_W),
-    .NPORTS         (7),
+    .NPORTS         (9),
     .DEFAULT_PORT   (0),
     .MTU            (MTU),
     .ROUTE_TBL_SIZE (6),
@@ -195,14 +211,14 @@ module rfnoc_image_core #(
     .clk            (rfnoc_chdr_clk),
     .reset          (rfnoc_chdr_rst),
     .device_id      (device_id),
-    .s_axis_tdata   ({ep3_to_xb_tdata, ep2_to_xb_tdata, ep1_to_xb_tdata, ep0_to_xb_tdata, s_pcie_tdata, s_eth1_tdata, s_eth0_tdata}),
-    .s_axis_tlast   ({ep3_to_xb_tlast, ep2_to_xb_tlast, ep1_to_xb_tlast, ep0_to_xb_tlast, s_pcie_tlast, s_eth1_tlast, s_eth0_tlast}),
-    .s_axis_tvalid  ({ep3_to_xb_tvalid, ep2_to_xb_tvalid, ep1_to_xb_tvalid, ep0_to_xb_tvalid, s_pcie_tvalid, s_eth1_tvalid, s_eth0_tvalid}),
-    .s_axis_tready  ({ep3_to_xb_tready, ep2_to_xb_tready, ep1_to_xb_tready, ep0_to_xb_tready, s_pcie_tready, s_eth1_tready, s_eth0_tready}),
-    .m_axis_tdata   ({xb_to_ep3_tdata, xb_to_ep2_tdata, xb_to_ep1_tdata, xb_to_ep0_tdata, m_pcie_tdata, m_eth1_tdata, m_eth0_tdata}),
-    .m_axis_tlast   ({xb_to_ep3_tlast, xb_to_ep2_tlast, xb_to_ep1_tlast, xb_to_ep0_tlast, m_pcie_tlast, m_eth1_tlast, m_eth0_tlast}),
-    .m_axis_tvalid  ({xb_to_ep3_tvalid, xb_to_ep2_tvalid, xb_to_ep1_tvalid, xb_to_ep0_tvalid, m_pcie_tvalid, m_eth1_tvalid, m_eth0_tvalid}),
-    .m_axis_tready  ({xb_to_ep3_tready, xb_to_ep2_tready, xb_to_ep1_tready, xb_to_ep0_tready, m_pcie_tready, m_eth1_tready, m_eth0_tready}),
+    .s_axis_tdata   ({ep5_to_xb_tdata, ep4_to_xb_tdata, ep3_to_xb_tdata, ep2_to_xb_tdata, ep1_to_xb_tdata, ep0_to_xb_tdata, s_pcie_tdata, s_eth1_tdata, s_eth0_tdata}),
+    .s_axis_tlast   ({ep5_to_xb_tlast, ep4_to_xb_tlast, ep3_to_xb_tlast, ep2_to_xb_tlast, ep1_to_xb_tlast, ep0_to_xb_tlast, s_pcie_tlast, s_eth1_tlast, s_eth0_tlast}),
+    .s_axis_tvalid  ({ep5_to_xb_tvalid, ep4_to_xb_tvalid, ep3_to_xb_tvalid, ep2_to_xb_tvalid, ep1_to_xb_tvalid, ep0_to_xb_tvalid, s_pcie_tvalid, s_eth1_tvalid, s_eth0_tvalid}),
+    .s_axis_tready  ({ep5_to_xb_tready, ep4_to_xb_tready, ep3_to_xb_tready, ep2_to_xb_tready, ep1_to_xb_tready, ep0_to_xb_tready, s_pcie_tready, s_eth1_tready, s_eth0_tready}),
+    .m_axis_tdata   ({xb_to_ep5_tdata, xb_to_ep4_tdata, xb_to_ep3_tdata, xb_to_ep2_tdata, xb_to_ep1_tdata, xb_to_ep0_tdata, m_pcie_tdata, m_eth1_tdata, m_eth0_tdata}),
+    .m_axis_tlast   ({xb_to_ep5_tlast, xb_to_ep4_tlast, xb_to_ep3_tlast, xb_to_ep2_tlast, xb_to_ep1_tlast, xb_to_ep0_tlast, m_pcie_tlast, m_eth1_tlast, m_eth0_tlast}),
+    .m_axis_tvalid  ({xb_to_ep5_tvalid, xb_to_ep4_tvalid, xb_to_ep3_tvalid, xb_to_ep2_tvalid, xb_to_ep1_tvalid, xb_to_ep0_tvalid, m_pcie_tvalid, m_eth1_tvalid, m_eth0_tvalid}),
+    .m_axis_tready  ({xb_to_ep5_tready, xb_to_ep4_tready, xb_to_ep3_tready, xb_to_ep2_tready, xb_to_ep1_tready, xb_to_ep0_tready, m_pcie_tready, m_eth1_tready, m_eth0_tready}),
     .ext_rtcfg_stb  (1'h0),
     .ext_rtcfg_addr (16'h0),
     .ext_rtcfg_data (32'h0),
@@ -457,6 +473,128 @@ module rfnoc_image_core #(
     .signal_data_err    (1'b0              )
   );
 
+  wire [CHDR_W-1:0] m_ep4_out0_tdata;
+  wire              m_ep4_out0_tlast;
+  wire              m_ep4_out0_tvalid;
+  wire              m_ep4_out0_tready;
+  wire [CHDR_W-1:0] s_ep4_in0_tdata;
+  wire              s_ep4_in0_tlast;
+  wire              s_ep4_in0_tvalid;
+  wire              s_ep4_in0_tready;
+  wire [31:0]       m_ep4_ctrl_tdata , s_ep4_ctrl_tdata ;
+  wire              m_ep4_ctrl_tlast , s_ep4_ctrl_tlast ;
+  wire              m_ep4_ctrl_tvalid, s_ep4_ctrl_tvalid;
+  wire              m_ep4_ctrl_tready, s_ep4_ctrl_tready;
+
+  chdr_stream_endpoint #(
+    .PROTOVER           (PROTOVER),
+    .CHDR_W             (CHDR_W),
+    .AXIS_CTRL_EN       (0),
+    .AXIS_DATA_EN       (1),
+    .NUM_DATA_I         (1),
+    .NUM_DATA_O         (1),
+    .INST_NUM           (4),
+    .CTRL_XBAR_PORT     (5),
+    .INGRESS_BUFF_SIZE  (12),
+    .MTU                (MTU),
+    .REPORT_STRM_ERRS   (1)
+  ) ep4_i (
+    .rfnoc_chdr_clk     (rfnoc_chdr_clk    ),
+    .rfnoc_chdr_rst     (rfnoc_chdr_rst    ),
+    .rfnoc_ctrl_clk     (rfnoc_ctrl_clk    ),
+    .rfnoc_ctrl_rst     (rfnoc_ctrl_rst    ),
+    .device_id          (device_id         ),
+    .s_axis_chdr_tdata  (xb_to_ep4_tdata  ),
+    .s_axis_chdr_tlast  (xb_to_ep4_tlast  ),
+    .s_axis_chdr_tvalid (xb_to_ep4_tvalid ),
+    .s_axis_chdr_tready (xb_to_ep4_tready ),
+    .m_axis_chdr_tdata  (ep4_to_xb_tdata  ),
+    .m_axis_chdr_tlast  (ep4_to_xb_tlast  ),
+    .m_axis_chdr_tvalid (ep4_to_xb_tvalid ),
+    .m_axis_chdr_tready (ep4_to_xb_tready ),
+    .s_axis_data_tdata  ({s_ep4_in0_tdata}),
+    .s_axis_data_tlast  ({s_ep4_in0_tlast}),
+    .s_axis_data_tvalid ({s_ep4_in0_tvalid}),
+    .s_axis_data_tready ({s_ep4_in0_tready}),
+    .m_axis_data_tdata  ({m_ep4_out0_tdata}),
+    .m_axis_data_tlast  ({m_ep4_out0_tlast}),
+    .m_axis_data_tvalid ({m_ep4_out0_tvalid}),
+    .m_axis_data_tready ({m_ep4_out0_tready}),
+    .s_axis_ctrl_tdata  (s_ep4_ctrl_tdata ),
+    .s_axis_ctrl_tlast  (s_ep4_ctrl_tlast ),
+    .s_axis_ctrl_tvalid (s_ep4_ctrl_tvalid),
+    .s_axis_ctrl_tready (s_ep4_ctrl_tready),
+    .m_axis_ctrl_tdata  (m_ep4_ctrl_tdata ),
+    .m_axis_ctrl_tlast  (m_ep4_ctrl_tlast ),
+    .m_axis_ctrl_tvalid (m_ep4_ctrl_tvalid),
+    .m_axis_ctrl_tready (m_ep4_ctrl_tready),
+    .strm_seq_err_stb   (                  ),
+    .strm_data_err_stb  (                  ),
+    .strm_route_err_stb (                  ),
+    .signal_data_err    (1'b0              )
+  );
+
+  wire [CHDR_W-1:0] m_ep5_out0_tdata;
+  wire              m_ep5_out0_tlast;
+  wire              m_ep5_out0_tvalid;
+  wire              m_ep5_out0_tready;
+  wire [CHDR_W-1:0] s_ep5_in0_tdata;
+  wire              s_ep5_in0_tlast;
+  wire              s_ep5_in0_tvalid;
+  wire              s_ep5_in0_tready;
+  wire [31:0]       m_ep5_ctrl_tdata , s_ep5_ctrl_tdata ;
+  wire              m_ep5_ctrl_tlast , s_ep5_ctrl_tlast ;
+  wire              m_ep5_ctrl_tvalid, s_ep5_ctrl_tvalid;
+  wire              m_ep5_ctrl_tready, s_ep5_ctrl_tready;
+
+  chdr_stream_endpoint #(
+    .PROTOVER           (PROTOVER),
+    .CHDR_W             (CHDR_W),
+    .AXIS_CTRL_EN       (0),
+    .AXIS_DATA_EN       (1),
+    .NUM_DATA_I         (1),
+    .NUM_DATA_O         (1),
+    .INST_NUM           (5),
+    .CTRL_XBAR_PORT     (6),
+    .INGRESS_BUFF_SIZE  (12),
+    .MTU                (MTU),
+    .REPORT_STRM_ERRS   (1)
+  ) ep5_i (
+    .rfnoc_chdr_clk     (rfnoc_chdr_clk    ),
+    .rfnoc_chdr_rst     (rfnoc_chdr_rst    ),
+    .rfnoc_ctrl_clk     (rfnoc_ctrl_clk    ),
+    .rfnoc_ctrl_rst     (rfnoc_ctrl_rst    ),
+    .device_id          (device_id         ),
+    .s_axis_chdr_tdata  (xb_to_ep5_tdata  ),
+    .s_axis_chdr_tlast  (xb_to_ep5_tlast  ),
+    .s_axis_chdr_tvalid (xb_to_ep5_tvalid ),
+    .s_axis_chdr_tready (xb_to_ep5_tready ),
+    .m_axis_chdr_tdata  (ep5_to_xb_tdata  ),
+    .m_axis_chdr_tlast  (ep5_to_xb_tlast  ),
+    .m_axis_chdr_tvalid (ep5_to_xb_tvalid ),
+    .m_axis_chdr_tready (ep5_to_xb_tready ),
+    .s_axis_data_tdata  ({s_ep5_in0_tdata}),
+    .s_axis_data_tlast  ({s_ep5_in0_tlast}),
+    .s_axis_data_tvalid ({s_ep5_in0_tvalid}),
+    .s_axis_data_tready ({s_ep5_in0_tready}),
+    .m_axis_data_tdata  ({m_ep5_out0_tdata}),
+    .m_axis_data_tlast  ({m_ep5_out0_tlast}),
+    .m_axis_data_tvalid ({m_ep5_out0_tvalid}),
+    .m_axis_data_tready ({m_ep5_out0_tready}),
+    .s_axis_ctrl_tdata  (s_ep5_ctrl_tdata ),
+    .s_axis_ctrl_tlast  (s_ep5_ctrl_tlast ),
+    .s_axis_ctrl_tvalid (s_ep5_ctrl_tvalid),
+    .s_axis_ctrl_tready (s_ep5_ctrl_tready),
+    .m_axis_ctrl_tdata  (m_ep5_ctrl_tdata ),
+    .m_axis_ctrl_tlast  (m_ep5_ctrl_tlast ),
+    .m_axis_ctrl_tvalid (m_ep5_ctrl_tvalid),
+    .m_axis_ctrl_tready (m_ep5_ctrl_tready),
+    .strm_seq_err_stb   (                  ),
+    .strm_data_err_stb  (                  ),
+    .strm_route_err_stb (                  ),
+    .signal_data_err    (1'b0              )
+  );
+
 
 
   // ----------------------------------------------------
@@ -491,10 +629,14 @@ module rfnoc_image_core #(
   wire              m_radio1_ctrl_tlast ,   s_radio1_ctrl_tlast ;
   wire              m_radio1_ctrl_tvalid,   s_radio1_ctrl_tvalid;
   wire              m_radio1_ctrl_tready,   s_radio1_ctrl_tready;
+  wire [31:0]       m_replay0_ctrl_tdata ,   s_replay0_ctrl_tdata ;
+  wire              m_replay0_ctrl_tlast ,   s_replay0_ctrl_tlast ;
+  wire              m_replay0_ctrl_tvalid,   s_replay0_ctrl_tvalid;
+  wire              m_replay0_ctrl_tready,   s_replay0_ctrl_tready;
 
   axis_ctrl_crossbar_nxn #(
     .WIDTH            (32),
-    .NPORTS           (8),
+    .NPORTS           (9),
     .TOPOLOGY         ("TORUS"),
     .INGRESS_BUFF_SIZE(5),
     .ROUTER_BUFF_SIZE (5),
@@ -503,32 +645,32 @@ module rfnoc_image_core #(
   ) ctrl_xb_i (
     .clk              (rfnoc_ctrl_clk),
     .reset            (rfnoc_ctrl_rst),
-    .s_axis_tdata     ({m_radio1_ctrl_tdata , m_ddc1_ctrl_tdata , m_duc1_ctrl_tdata , m_radio0_ctrl_tdata , m_ddc0_ctrl_tdata , m_duc0_ctrl_tdata , m_ep0_ctrl_tdata , m_core_ctrl_tdata }),
-    .s_axis_tvalid    ({m_radio1_ctrl_tvalid, m_ddc1_ctrl_tvalid, m_duc1_ctrl_tvalid, m_radio0_ctrl_tvalid, m_ddc0_ctrl_tvalid, m_duc0_ctrl_tvalid, m_ep0_ctrl_tvalid, m_core_ctrl_tvalid}),
-    .s_axis_tlast     ({m_radio1_ctrl_tlast , m_ddc1_ctrl_tlast , m_duc1_ctrl_tlast , m_radio0_ctrl_tlast , m_ddc0_ctrl_tlast , m_duc0_ctrl_tlast , m_ep0_ctrl_tlast , m_core_ctrl_tlast }),
-    .s_axis_tready    ({m_radio1_ctrl_tready, m_ddc1_ctrl_tready, m_duc1_ctrl_tready, m_radio0_ctrl_tready, m_ddc0_ctrl_tready, m_duc0_ctrl_tready, m_ep0_ctrl_tready, m_core_ctrl_tready}),
-    .m_axis_tdata     ({s_radio1_ctrl_tdata , s_ddc1_ctrl_tdata , s_duc1_ctrl_tdata , s_radio0_ctrl_tdata , s_ddc0_ctrl_tdata , s_duc0_ctrl_tdata , s_ep0_ctrl_tdata , s_core_ctrl_tdata }),
-    .m_axis_tvalid    ({s_radio1_ctrl_tvalid, s_ddc1_ctrl_tvalid, s_duc1_ctrl_tvalid, s_radio0_ctrl_tvalid, s_ddc0_ctrl_tvalid, s_duc0_ctrl_tvalid, s_ep0_ctrl_tvalid, s_core_ctrl_tvalid}),
-    .m_axis_tlast     ({s_radio1_ctrl_tlast , s_ddc1_ctrl_tlast , s_duc1_ctrl_tlast , s_radio0_ctrl_tlast , s_ddc0_ctrl_tlast , s_duc0_ctrl_tlast , s_ep0_ctrl_tlast , s_core_ctrl_tlast }),
-    .m_axis_tready    ({s_radio1_ctrl_tready, s_ddc1_ctrl_tready, s_duc1_ctrl_tready, s_radio0_ctrl_tready, s_ddc0_ctrl_tready, s_duc0_ctrl_tready, s_ep0_ctrl_tready, s_core_ctrl_tready}),
+    .s_axis_tdata     ({m_replay0_ctrl_tdata , m_radio1_ctrl_tdata , m_ddc1_ctrl_tdata , m_duc1_ctrl_tdata , m_radio0_ctrl_tdata , m_ddc0_ctrl_tdata , m_duc0_ctrl_tdata , m_ep0_ctrl_tdata , m_core_ctrl_tdata }),
+    .s_axis_tvalid    ({m_replay0_ctrl_tvalid, m_radio1_ctrl_tvalid, m_ddc1_ctrl_tvalid, m_duc1_ctrl_tvalid, m_radio0_ctrl_tvalid, m_ddc0_ctrl_tvalid, m_duc0_ctrl_tvalid, m_ep0_ctrl_tvalid, m_core_ctrl_tvalid}),
+    .s_axis_tlast     ({m_replay0_ctrl_tlast , m_radio1_ctrl_tlast , m_ddc1_ctrl_tlast , m_duc1_ctrl_tlast , m_radio0_ctrl_tlast , m_ddc0_ctrl_tlast , m_duc0_ctrl_tlast , m_ep0_ctrl_tlast , m_core_ctrl_tlast }),
+    .s_axis_tready    ({m_replay0_ctrl_tready, m_radio1_ctrl_tready, m_ddc1_ctrl_tready, m_duc1_ctrl_tready, m_radio0_ctrl_tready, m_ddc0_ctrl_tready, m_duc0_ctrl_tready, m_ep0_ctrl_tready, m_core_ctrl_tready}),
+    .m_axis_tdata     ({s_replay0_ctrl_tdata , s_radio1_ctrl_tdata , s_ddc1_ctrl_tdata , s_duc1_ctrl_tdata , s_radio0_ctrl_tdata , s_ddc0_ctrl_tdata , s_duc0_ctrl_tdata , s_ep0_ctrl_tdata , s_core_ctrl_tdata }),
+    .m_axis_tvalid    ({s_replay0_ctrl_tvalid, s_radio1_ctrl_tvalid, s_ddc1_ctrl_tvalid, s_duc1_ctrl_tvalid, s_radio0_ctrl_tvalid, s_ddc0_ctrl_tvalid, s_duc0_ctrl_tvalid, s_ep0_ctrl_tvalid, s_core_ctrl_tvalid}),
+    .m_axis_tlast     ({s_replay0_ctrl_tlast , s_radio1_ctrl_tlast , s_ddc1_ctrl_tlast , s_duc1_ctrl_tlast , s_radio0_ctrl_tlast , s_ddc0_ctrl_tlast , s_duc0_ctrl_tlast , s_ep0_ctrl_tlast , s_core_ctrl_tlast }),
+    .m_axis_tready    ({s_replay0_ctrl_tready, s_radio1_ctrl_tready, s_ddc1_ctrl_tready, s_duc1_ctrl_tready, s_radio0_ctrl_tready, s_ddc0_ctrl_tready, s_duc0_ctrl_tready, s_ep0_ctrl_tready, s_core_ctrl_tready}),
     .deadlock_detected()
   );
 
   // ----------------------------------------------------
   // RFNoC Core Kernel
   // ----------------------------------------------------
-  wire [(512*6)-1:0] rfnoc_core_config, rfnoc_core_status;
+  wire [(512*7)-1:0] rfnoc_core_config, rfnoc_core_status;
 
   rfnoc_core_kernel #(
     .PROTOVER            (PROTOVER),
     .DEVICE_TYPE         (16'hA300),
     .DEVICE_FAMILY       ("7SERIES"),
     .SAFE_START_CLKS     (0),
-    .NUM_BLOCKS          (6),
-    .NUM_STREAM_ENDPOINTS(4),
+    .NUM_BLOCKS          (7),
+    .NUM_STREAM_ENDPOINTS(6),
     .NUM_ENDPOINTS_CTRL  (1),
     .NUM_TRANSPORTS      (3),
-    .NUM_EDGES           (12),
+    .NUM_EDGES           (16),
     .CHDR_XBAR_PRESENT   (1),
     .EDGE_TBL_FILE       (EDGE_TBL_FILE)
   ) core_kernel_i (
@@ -917,6 +1059,145 @@ module rfnoc_image_core #(
 
 
   // ----------------------------------------------------
+  // replay0
+  // ----------------------------------------------------
+  wire              replay0_mem_clk;
+  wire [CHDR_W-1:0] s_replay0_in_1_tdata , s_replay0_in_0_tdata ;
+  wire              s_replay0_in_1_tlast , s_replay0_in_0_tlast ;
+  wire              s_replay0_in_1_tvalid, s_replay0_in_0_tvalid;
+  wire              s_replay0_in_1_tready, s_replay0_in_0_tready;
+  wire [CHDR_W-1:0] m_replay0_out_1_tdata , m_replay0_out_0_tdata ;
+  wire              m_replay0_out_1_tlast , m_replay0_out_0_tlast ;
+  wire              m_replay0_out_1_tvalid, m_replay0_out_0_tvalid;
+  wire              m_replay0_out_1_tready, m_replay0_out_0_tready;
+
+  //  axi_ram
+  wire [  1-1:0] replay0_axi_rst;
+  wire [  4-1:0] replay0_m_axi_awid;
+  wire [128-1:0] replay0_m_axi_awaddr;
+  wire [ 32-1:0] replay0_m_axi_awlen;
+  wire [ 12-1:0] replay0_m_axi_awsize;
+  wire [  8-1:0] replay0_m_axi_awburst;
+  wire [  4-1:0] replay0_m_axi_awlock;
+  wire [ 16-1:0] replay0_m_axi_awcache;
+  wire [ 12-1:0] replay0_m_axi_awprot;
+  wire [ 16-1:0] replay0_m_axi_awqos;
+  wire [ 16-1:0] replay0_m_axi_awregion;
+  wire [  4-1:0] replay0_m_axi_awuser;
+  wire [  4-1:0] replay0_m_axi_awvalid;
+  wire [  4-1:0] replay0_m_axi_awready;
+  wire [256-1:0] replay0_m_axi_wdata;
+  wire [ 32-1:0] replay0_m_axi_wstrb;
+  wire [  4-1:0] replay0_m_axi_wlast;
+  wire [  4-1:0] replay0_m_axi_wuser;
+  wire [  4-1:0] replay0_m_axi_wvalid;
+  wire [  4-1:0] replay0_m_axi_wready;
+  wire [  4-1:0] replay0_m_axi_bid;
+  wire [  8-1:0] replay0_m_axi_bresp;
+  wire [  4-1:0] replay0_m_axi_buser;
+  wire [  4-1:0] replay0_m_axi_bvalid;
+  wire [  4-1:0] replay0_m_axi_bready;
+  wire [  4-1:0] replay0_m_axi_arid;
+  wire [128-1:0] replay0_m_axi_araddr;
+  wire [ 32-1:0] replay0_m_axi_arlen;
+  wire [ 12-1:0] replay0_m_axi_arsize;
+  wire [  8-1:0] replay0_m_axi_arburst;
+  wire [  4-1:0] replay0_m_axi_arlock;
+  wire [ 16-1:0] replay0_m_axi_arcache;
+  wire [ 12-1:0] replay0_m_axi_arprot;
+  wire [ 16-1:0] replay0_m_axi_arqos;
+  wire [ 16-1:0] replay0_m_axi_arregion;
+  wire [  4-1:0] replay0_m_axi_aruser;
+  wire [  4-1:0] replay0_m_axi_arvalid;
+  wire [  4-1:0] replay0_m_axi_arready;
+  wire [  4-1:0] replay0_m_axi_rid;
+  wire [256-1:0] replay0_m_axi_rdata;
+  wire [  8-1:0] replay0_m_axi_rresp;
+  wire [  4-1:0] replay0_m_axi_rlast;
+  wire [  4-1:0] replay0_m_axi_ruser;
+  wire [  4-1:0] replay0_m_axi_rvalid;
+  wire [  4-1:0] replay0_m_axi_rready;
+
+  rfnoc_block_replay #(
+    .THIS_PORTID(8),
+    .CHDR_W(CHDR_W),
+    .NUM_PORTS(2),
+    .MEM_ADDR_W(30),
+    .MEM_DATA_W(64),
+    .MTU(MTU)
+  ) b_replay0_6 (
+    .rfnoc_chdr_clk     (rfnoc_chdr_clk),
+    .rfnoc_ctrl_clk     (rfnoc_ctrl_clk),
+    .mem_clk(replay0_mem_clk),
+    .rfnoc_core_config  (rfnoc_core_config[512*7-1:512*6]),
+    .rfnoc_core_status  (rfnoc_core_status[512*7-1:512*6]),
+
+    .axi_rst(replay0_axi_rst),
+    .m_axi_awid(replay0_m_axi_awid),
+    .m_axi_awaddr(replay0_m_axi_awaddr),
+    .m_axi_awlen(replay0_m_axi_awlen),
+    .m_axi_awsize(replay0_m_axi_awsize),
+    .m_axi_awburst(replay0_m_axi_awburst),
+    .m_axi_awlock(replay0_m_axi_awlock),
+    .m_axi_awcache(replay0_m_axi_awcache),
+    .m_axi_awprot(replay0_m_axi_awprot),
+    .m_axi_awqos(replay0_m_axi_awqos),
+    .m_axi_awregion(replay0_m_axi_awregion),
+    .m_axi_awuser(replay0_m_axi_awuser),
+    .m_axi_awvalid(replay0_m_axi_awvalid),
+    .m_axi_awready(replay0_m_axi_awready),
+    .m_axi_wdata(replay0_m_axi_wdata),
+    .m_axi_wstrb(replay0_m_axi_wstrb),
+    .m_axi_wlast(replay0_m_axi_wlast),
+    .m_axi_wuser(replay0_m_axi_wuser),
+    .m_axi_wvalid(replay0_m_axi_wvalid),
+    .m_axi_wready(replay0_m_axi_wready),
+    .m_axi_bid(replay0_m_axi_bid),
+    .m_axi_bresp(replay0_m_axi_bresp),
+    .m_axi_buser(replay0_m_axi_buser),
+    .m_axi_bvalid(replay0_m_axi_bvalid),
+    .m_axi_bready(replay0_m_axi_bready),
+    .m_axi_arid(replay0_m_axi_arid),
+    .m_axi_araddr(replay0_m_axi_araddr),
+    .m_axi_arlen(replay0_m_axi_arlen),
+    .m_axi_arsize(replay0_m_axi_arsize),
+    .m_axi_arburst(replay0_m_axi_arburst),
+    .m_axi_arlock(replay0_m_axi_arlock),
+    .m_axi_arcache(replay0_m_axi_arcache),
+    .m_axi_arprot(replay0_m_axi_arprot),
+    .m_axi_arqos(replay0_m_axi_arqos),
+    .m_axi_arregion(replay0_m_axi_arregion),
+    .m_axi_aruser(replay0_m_axi_aruser),
+    .m_axi_arvalid(replay0_m_axi_arvalid),
+    .m_axi_arready(replay0_m_axi_arready),
+    .m_axi_rid(replay0_m_axi_rid),
+    .m_axi_rdata(replay0_m_axi_rdata),
+    .m_axi_rresp(replay0_m_axi_rresp),
+    .m_axi_rlast(replay0_m_axi_rlast),
+    .m_axi_ruser(replay0_m_axi_ruser),
+    .m_axi_rvalid(replay0_m_axi_rvalid),
+    .m_axi_rready(replay0_m_axi_rready),
+
+    .s_rfnoc_chdr_tdata ({s_replay0_in_1_tdata , s_replay0_in_0_tdata }),
+    .s_rfnoc_chdr_tlast ({s_replay0_in_1_tlast , s_replay0_in_0_tlast }),
+    .s_rfnoc_chdr_tvalid({s_replay0_in_1_tvalid, s_replay0_in_0_tvalid}),
+    .s_rfnoc_chdr_tready({s_replay0_in_1_tready, s_replay0_in_0_tready}),
+    .m_rfnoc_chdr_tdata ({m_replay0_out_1_tdata , m_replay0_out_0_tdata }),
+    .m_rfnoc_chdr_tlast ({m_replay0_out_1_tlast , m_replay0_out_0_tlast }),
+    .m_rfnoc_chdr_tvalid({m_replay0_out_1_tvalid, m_replay0_out_0_tvalid}),
+    .m_rfnoc_chdr_tready({m_replay0_out_1_tready, m_replay0_out_0_tready}),
+    .s_rfnoc_ctrl_tdata (s_replay0_ctrl_tdata ),
+    .s_rfnoc_ctrl_tlast (s_replay0_ctrl_tlast ),
+    .s_rfnoc_ctrl_tvalid(s_replay0_ctrl_tvalid),
+    .s_rfnoc_ctrl_tready(s_replay0_ctrl_tready),
+    .m_rfnoc_ctrl_tdata (m_replay0_ctrl_tdata ),
+    .m_rfnoc_ctrl_tlast (m_replay0_ctrl_tlast ),
+    .m_rfnoc_ctrl_tvalid(m_replay0_ctrl_tvalid),
+    .m_rfnoc_ctrl_tready(m_replay0_ctrl_tready)
+  );
+
+
+  // ----------------------------------------------------
   // Static Router
   // ----------------------------------------------------
   assign s_duc0_in_0_tdata = m_ep0_out0_tdata ;
@@ -979,6 +1260,26 @@ module rfnoc_image_core #(
   assign s_ep3_in0_tvalid = m_ddc1_out_1_tvalid;
   assign m_ddc1_out_1_tready = s_ep3_in0_tready;
 
+  assign s_replay0_in_0_tdata = m_ep4_out0_tdata ;
+  assign s_replay0_in_0_tlast = m_ep4_out0_tlast ;
+  assign s_replay0_in_0_tvalid = m_ep4_out0_tvalid;
+  assign m_ep4_out0_tready = s_replay0_in_0_tready;
+
+  assign s_ep4_in0_tdata = m_replay0_out_0_tdata ;
+  assign s_ep4_in0_tlast = m_replay0_out_0_tlast ;
+  assign s_ep4_in0_tvalid = m_replay0_out_0_tvalid;
+  assign m_replay0_out_0_tready = s_ep4_in0_tready;
+
+  assign s_replay0_in_1_tdata = m_ep5_out0_tdata ;
+  assign s_replay0_in_1_tlast = m_ep5_out0_tlast ;
+  assign s_replay0_in_1_tvalid = m_ep5_out0_tvalid;
+  assign m_ep5_out0_tready = s_replay0_in_1_tready;
+
+  assign s_ep5_in0_tdata = m_replay0_out_1_tdata ;
+  assign s_ep5_in0_tlast = m_replay0_out_1_tlast ;
+  assign s_ep5_in0_tvalid = m_replay0_out_1_tvalid;
+  assign m_replay0_out_1_tready = s_ep5_in0_tready;
+
 
   // ----------------------------------------------------
   // Unused Ports
@@ -1001,6 +1302,7 @@ module rfnoc_image_core #(
   assign radio1_radio_clk = radio_clk;
   assign ddc1_ce_clk = ce_clk;
   assign duc1_ce_clk = ce_clk;
+  assign replay0_mem_clk = dram_clk;
 
 
   // ----------------------------------------------------
@@ -1029,6 +1331,52 @@ module rfnoc_image_core #(
   assign radio1_m_ctrlport_resp_status = m_ctrlport_radio1_resp_status;
   assign radio1_m_ctrlport_resp_data = m_ctrlport_radio1_resp_data;
 
+  assign replay0_axi_rst = axi_rst;
+  assign m_axi_awid = replay0_m_axi_awid;
+  assign m_axi_awaddr = replay0_m_axi_awaddr;
+  assign m_axi_awlen = replay0_m_axi_awlen;
+  assign m_axi_awsize = replay0_m_axi_awsize;
+  assign m_axi_awburst = replay0_m_axi_awburst;
+  assign m_axi_awlock = replay0_m_axi_awlock;
+  assign m_axi_awcache = replay0_m_axi_awcache;
+  assign m_axi_awprot = replay0_m_axi_awprot;
+  assign m_axi_awqos = replay0_m_axi_awqos;
+  assign m_axi_awregion = replay0_m_axi_awregion;
+  assign m_axi_awuser = replay0_m_axi_awuser;
+  assign m_axi_awvalid = replay0_m_axi_awvalid;
+  assign replay0_m_axi_awready = m_axi_awready;
+  assign m_axi_wdata = replay0_m_axi_wdata;
+  assign m_axi_wstrb = replay0_m_axi_wstrb;
+  assign m_axi_wlast = replay0_m_axi_wlast;
+  assign m_axi_wuser = replay0_m_axi_wuser;
+  assign m_axi_wvalid = replay0_m_axi_wvalid;
+  assign replay0_m_axi_wready = m_axi_wready;
+  assign replay0_m_axi_bid = m_axi_bid;
+  assign replay0_m_axi_bresp = m_axi_bresp;
+  assign replay0_m_axi_buser = m_axi_buser;
+  assign replay0_m_axi_bvalid = m_axi_bvalid;
+  assign m_axi_bready = replay0_m_axi_bready;
+  assign m_axi_arid = replay0_m_axi_arid;
+  assign m_axi_araddr = replay0_m_axi_araddr;
+  assign m_axi_arlen = replay0_m_axi_arlen;
+  assign m_axi_arsize = replay0_m_axi_arsize;
+  assign m_axi_arburst = replay0_m_axi_arburst;
+  assign m_axi_arlock = replay0_m_axi_arlock;
+  assign m_axi_arcache = replay0_m_axi_arcache;
+  assign m_axi_arprot = replay0_m_axi_arprot;
+  assign m_axi_arqos = replay0_m_axi_arqos;
+  assign m_axi_arregion = replay0_m_axi_arregion;
+  assign m_axi_aruser = replay0_m_axi_aruser;
+  assign m_axi_arvalid = replay0_m_axi_arvalid;
+  assign replay0_m_axi_arready = m_axi_arready;
+  assign replay0_m_axi_rid = m_axi_rid;
+  assign replay0_m_axi_rdata = m_axi_rdata;
+  assign replay0_m_axi_rresp = m_axi_rresp;
+  assign replay0_m_axi_rlast = m_axi_rlast;
+  assign replay0_m_axi_ruser = m_axi_ruser;
+  assign replay0_m_axi_rvalid = m_axi_rvalid;
+  assign m_axi_rready = replay0_m_axi_rready;
+
   assign radio0_radio_rx_data = radio_rx_data_radio0;
   assign radio0_radio_rx_stb = radio_rx_stb_radio0;
   assign radio_rx_running_radio0 = radio0_radio_rx_running;
diff --git a/fpga/usrp3/top/x300/x300_rfnoc_image_core.yml b/fpga/usrp3/top/x300/x300_rfnoc_image_core.yml
index 08a8e82c2..d9570b8ef 100644
--- a/fpga/usrp3/top/x300/x300_rfnoc_image_core.yml
+++ b/fpga/usrp3/top/x300/x300_rfnoc_image_core.yml
@@ -28,6 +28,14 @@ stream_endpoints:
     ctrl: False                     # Endpoint passes control traffic
     data: True                      # Endpoint passes data traffic
     buff_size: 0                    # Ingress buffer size for data
+  ep4:                       # Stream endpoint name
+    ctrl: False                     # Endpoint passes control traffic
+    data: True                      # Endpoint passes data traffic
+    buff_size: 4096                 # Ingress buffer size for data
+  ep5:                       # Stream endpoint name
+    ctrl: False                     # Endpoint passes control traffic
+    data: True                      # Endpoint passes data traffic
+    buff_size: 4096                 # Ingress buffer size for data
 
 # A list of all NoC blocks in design
 # ----------------------------------
@@ -52,6 +60,11 @@ noc_blocks:
       NUM_PORTS: 2
   radio1:
     block_desc: 'radio_2x64.yml'
+  replay0:
+    block_desc: 'replay.yml'
+    parameters:
+      NUM_PORTS: 2
+      MEM_ADDR_W: 30
 
 # A list of all static connections in design
 # ------------------------------------------
@@ -79,9 +92,18 @@ connections:
   # radio0(1) to ep3 - RFA RX
   - { srcblk: radio1, srcport: out_1, dstblk: ddc1,   dstport: in_1 }
   - { srcblk: ddc1,   srcport: out_1, dstblk: ep3,    dstport: in0  }
+  # ep4 to replay0(0)
+  - { srcblk: ep4,     srcport: out0,  dstblk: replay0, dstport: in_0 }
+  # replay0(0) to ep4
+  - { srcblk: replay0, srcport: out_0, dstblk: ep4,     dstport: in0  }
+  # ep5 to replay0(1)
+  - { srcblk: ep5,     srcport: out0,  dstblk: replay0, dstport: in_1 }
+  # replay0(1) to ep5
+  - { srcblk: replay0, srcport: out_1, dstblk: ep5,     dstport: in0  }
   # BSP Connections
   - { srcblk: radio0, srcport: ctrl_port, dstblk: _device_, dstport: ctrlport_radio0 }
   - { srcblk: radio1, srcport: ctrl_port, dstblk: _device_, dstport: ctrlport_radio1 }
+  - { srcblk: replay0, srcport: axi_ram, dstblk: _device_, dstport: dram }
   - { srcblk: _device_, srcport: x300_radio0, dstblk: radio0, dstport: x300_radio }
   - { srcblk: _device_, srcport: x300_radio1, dstblk: radio1, dstport: x300_radio }
   - { srcblk: _device_, srcport: time_keeper, dstblk: radio0, dstport: time_keeper }
@@ -101,3 +123,4 @@ clk_domains:
   - { srcblk: _device_, srcport: radio, dstblk: radio1, dstport: radio }
   - { srcblk: _device_, srcport: ce,    dstblk: ddc1,   dstport: ce    }
   - { srcblk: _device_, srcport: ce,    dstblk: duc1,   dstport: ce    }
+  - { srcblk: _device_, srcport: dram,  dstblk: replay0, dstport: mem  }
diff --git a/fpga/usrp3/top/x300/x300_static_router.hex b/fpga/usrp3/top/x300/x300_static_router.hex
index 53635706f..eb493cee8 100644
--- a/fpga/usrp3/top/x300/x300_static_router.hex
+++ b/fpga/usrp3/top/x300/x300_static_router.hex
@@ -1,13 +1,17 @@
-0000000C
-00400140
-014001c0
-01c00180
-01800040
-01c10181
-01810080
-00c00200
-02000280
-02800240
-024000c0
-02810241
-02410100
+00000010
+004001c0
+01c00240
+02400200
+02000040
+02410201
+02010080
+00c00280
+02800300
+030002c0
+02c000c0
+030102c1
+02c10100
+01400340
+03400140
+01800341
+03410180
diff --git a/fpga/usrp3/top/x300/x310_rfnoc_image_core.v b/fpga/usrp3/top/x300/x310_rfnoc_image_core.v
index 73124f119..4dc38bd11 100644
--- a/fpga/usrp3/top/x300/x310_rfnoc_image_core.v
+++ b/fpga/usrp3/top/x300/x310_rfnoc_image_core.v
@@ -1,5 +1,5 @@
 //
-// Copyright 2019 Ettus Research, A National Instruments Brand
+// Copyright 2020 Ettus Research, A National Instruments Brand
 //
 // SPDX-License-Identifier: LGPL-3.0-or-later
 //
@@ -7,9 +7,9 @@
 // Module: rfnoc_image_core (for x300)
 // This file was autogenerated by UHD's image builder tool (rfnoc_image_builder)
 // Re-running that tool will overwrite this file!
-// File generated on: 2019-11-14T12:14:56.022475
+// File generated on: 2020-09-02T12:02:33.545638
 // Source: ./x310_rfnoc_image_core.yml
-// Source SHA256: 41b259b31e2a09272ffb146ef99afe1672a44c86dd51104fa4d1821ad24d5518
+// Source SHA256: acc39ec2e56ad0a5dd482a8db6b4dbb7e9790c03074d7461a38e0b5356456a83
 
 module rfnoc_image_core #(
   parameter [15:0] PROTOVER = {8'd1, 8'd0}
@@ -64,50 +64,50 @@ module rfnoc_image_core #(
   output wire [  2-1:0] radio_tx_running_radio1,
 //  dram
   input  wire [  1-1:0] axi_rst,
-  output wire [  2-1:0] m_axi_awid,
-  output wire [ 64-1:0] m_axi_awaddr,
-  output wire [ 16-1:0] m_axi_awlen,
-  output wire [  6-1:0] m_axi_awsize,
-  output wire [  4-1:0] m_axi_awburst,
-  output wire [  2-1:0] m_axi_awlock,
-  output wire [  8-1:0] m_axi_awcache,
-  output wire [  6-1:0] m_axi_awprot,
-  output wire [  8-1:0] m_axi_awqos,
-  output wire [  8-1:0] m_axi_awregion,
-  output wire [  2-1:0] m_axi_awuser,
-  output wire [  2-1:0] m_axi_awvalid,
-  input  wire [  2-1:0] m_axi_awready,
-  output wire [128-1:0] m_axi_wdata,
-  output wire [ 16-1:0] m_axi_wstrb,
-  output wire [  2-1:0] m_axi_wlast,
-  output wire [  2-1:0] m_axi_wuser,
-  output wire [  2-1:0] m_axi_wvalid,
-  input  wire [  2-1:0] m_axi_wready,
-  input  wire [  2-1:0] m_axi_bid,
-  input  wire [  4-1:0] m_axi_bresp,
-  input  wire [  2-1:0] m_axi_buser,
-  input  wire [  2-1:0] m_axi_bvalid,
-  output wire [  2-1:0] m_axi_bready,
-  output wire [  2-1:0] m_axi_arid,
-  output wire [ 64-1:0] m_axi_araddr,
-  output wire [ 16-1:0] m_axi_arlen,
-  output wire [  6-1:0] m_axi_arsize,
-  output wire [  4-1:0] m_axi_arburst,
-  output wire [  2-1:0] m_axi_arlock,
-  output wire [  8-1:0] m_axi_arcache,
-  output wire [  6-1:0] m_axi_arprot,
-  output wire [  8-1:0] m_axi_arqos,
-  output wire [  8-1:0] m_axi_arregion,
-  output wire [  2-1:0] m_axi_aruser,
-  output wire [  2-1:0] m_axi_arvalid,
-  input  wire [  2-1:0] m_axi_arready,
-  input  wire [  2-1:0] m_axi_rid,
-  input  wire [128-1:0] m_axi_rdata,
-  input  wire [  4-1:0] m_axi_rresp,
-  input  wire [  2-1:0] m_axi_rlast,
-  input  wire [  2-1:0] m_axi_ruser,
-  input  wire [  2-1:0] m_axi_rvalid,
-  output wire [  2-1:0] m_axi_rready,
+  output wire [  4-1:0] m_axi_awid,
+  output wire [128-1:0] m_axi_awaddr,
+  output wire [ 32-1:0] m_axi_awlen,
+  output wire [ 12-1:0] m_axi_awsize,
+  output wire [  8-1:0] m_axi_awburst,
+  output wire [  4-1:0] m_axi_awlock,
+  output wire [ 16-1:0] m_axi_awcache,
+  output wire [ 12-1:0] m_axi_awprot,
+  output wire [ 16-1:0] m_axi_awqos,
+  output wire [ 16-1:0] m_axi_awregion,
+  output wire [  4-1:0] m_axi_awuser,
+  output wire [  4-1:0] m_axi_awvalid,
+  input  wire [  4-1:0] m_axi_awready,
+  output wire [256-1:0] m_axi_wdata,
+  output wire [ 32-1:0] m_axi_wstrb,
+  output wire [  4-1:0] m_axi_wlast,
+  output wire [  4-1:0] m_axi_wuser,
+  output wire [  4-1:0] m_axi_wvalid,
+  input  wire [  4-1:0] m_axi_wready,
+  input  wire [  4-1:0] m_axi_bid,
+  input  wire [  8-1:0] m_axi_bresp,
+  input  wire [  4-1:0] m_axi_buser,
+  input  wire [  4-1:0] m_axi_bvalid,
+  output wire [  4-1:0] m_axi_bready,
+  output wire [  4-1:0] m_axi_arid,
+  output wire [128-1:0] m_axi_araddr,
+  output wire [ 32-1:0] m_axi_arlen,
+  output wire [ 12-1:0] m_axi_arsize,
+  output wire [  8-1:0] m_axi_arburst,
+  output wire [  4-1:0] m_axi_arlock,
+  output wire [ 16-1:0] m_axi_arcache,
+  output wire [ 12-1:0] m_axi_arprot,
+  output wire [ 16-1:0] m_axi_arqos,
+  output wire [ 16-1:0] m_axi_arregion,
+  output wire [  4-1:0] m_axi_aruser,
+  output wire [  4-1:0] m_axi_arvalid,
+  input  wire [  4-1:0] m_axi_arready,
+  input  wire [  4-1:0] m_axi_rid,
+  input  wire [256-1:0] m_axi_rdata,
+  input  wire [  8-1:0] m_axi_rresp,
+  input  wire [  4-1:0] m_axi_rlast,
+  input  wire [  4-1:0] m_axi_ruser,
+  input  wire [  4-1:0] m_axi_rvalid,
+  output wire [  4-1:0] m_axi_rready,
   // Transport 0 (eth0 10G)
   input  wire [64-1:0]  s_eth0_tdata,
   input  wire         s_eth0_tlast,
@@ -179,10 +179,26 @@ module rfnoc_image_core #(
   wire              ep3_to_xb_tlast ;
   wire              ep3_to_xb_tvalid;
   wire              ep3_to_xb_tready;
+  wire [CHDR_W-1:0] xb_to_ep4_tdata ;
+  wire              xb_to_ep4_tlast ;
+  wire              xb_to_ep4_tvalid;
+  wire              xb_to_ep4_tready;
+  wire [CHDR_W-1:0] ep4_to_xb_tdata ;
+  wire              ep4_to_xb_tlast ;
+  wire              ep4_to_xb_tvalid;
+  wire              ep4_to_xb_tready;
+  wire [CHDR_W-1:0] xb_to_ep5_tdata ;
+  wire              xb_to_ep5_tlast ;
+  wire              xb_to_ep5_tvalid;
+  wire              xb_to_ep5_tready;
+  wire [CHDR_W-1:0] ep5_to_xb_tdata ;
+  wire              ep5_to_xb_tlast ;
+  wire              ep5_to_xb_tvalid;
+  wire              ep5_to_xb_tready;
 
   chdr_crossbar_nxn #(
     .CHDR_W         (CHDR_W),
-    .NPORTS         (7),
+    .NPORTS         (9),
     .DEFAULT_PORT   (0),
     .MTU            (MTU),
     .ROUTE_TBL_SIZE (6),
@@ -195,14 +211,14 @@ module rfnoc_image_core #(
     .clk            (rfnoc_chdr_clk),
     .reset          (rfnoc_chdr_rst),
     .device_id      (device_id),
-    .s_axis_tdata   ({ep3_to_xb_tdata, ep2_to_xb_tdata, ep1_to_xb_tdata, ep0_to_xb_tdata, s_pcie_tdata, s_eth1_tdata, s_eth0_tdata}),
-    .s_axis_tlast   ({ep3_to_xb_tlast, ep2_to_xb_tlast, ep1_to_xb_tlast, ep0_to_xb_tlast, s_pcie_tlast, s_eth1_tlast, s_eth0_tlast}),
-    .s_axis_tvalid  ({ep3_to_xb_tvalid, ep2_to_xb_tvalid, ep1_to_xb_tvalid, ep0_to_xb_tvalid, s_pcie_tvalid, s_eth1_tvalid, s_eth0_tvalid}),
-    .s_axis_tready  ({ep3_to_xb_tready, ep2_to_xb_tready, ep1_to_xb_tready, ep0_to_xb_tready, s_pcie_tready, s_eth1_tready, s_eth0_tready}),
-    .m_axis_tdata   ({xb_to_ep3_tdata, xb_to_ep2_tdata, xb_to_ep1_tdata, xb_to_ep0_tdata, m_pcie_tdata, m_eth1_tdata, m_eth0_tdata}),
-    .m_axis_tlast   ({xb_to_ep3_tlast, xb_to_ep2_tlast, xb_to_ep1_tlast, xb_to_ep0_tlast, m_pcie_tlast, m_eth1_tlast, m_eth0_tlast}),
-    .m_axis_tvalid  ({xb_to_ep3_tvalid, xb_to_ep2_tvalid, xb_to_ep1_tvalid, xb_to_ep0_tvalid, m_pcie_tvalid, m_eth1_tvalid, m_eth0_tvalid}),
-    .m_axis_tready  ({xb_to_ep3_tready, xb_to_ep2_tready, xb_to_ep1_tready, xb_to_ep0_tready, m_pcie_tready, m_eth1_tready, m_eth0_tready}),
+    .s_axis_tdata   ({ep5_to_xb_tdata, ep4_to_xb_tdata, ep3_to_xb_tdata, ep2_to_xb_tdata, ep1_to_xb_tdata, ep0_to_xb_tdata, s_pcie_tdata, s_eth1_tdata, s_eth0_tdata}),
+    .s_axis_tlast   ({ep5_to_xb_tlast, ep4_to_xb_tlast, ep3_to_xb_tlast, ep2_to_xb_tlast, ep1_to_xb_tlast, ep0_to_xb_tlast, s_pcie_tlast, s_eth1_tlast, s_eth0_tlast}),
+    .s_axis_tvalid  ({ep5_to_xb_tvalid, ep4_to_xb_tvalid, ep3_to_xb_tvalid, ep2_to_xb_tvalid, ep1_to_xb_tvalid, ep0_to_xb_tvalid, s_pcie_tvalid, s_eth1_tvalid, s_eth0_tvalid}),
+    .s_axis_tready  ({ep5_to_xb_tready, ep4_to_xb_tready, ep3_to_xb_tready, ep2_to_xb_tready, ep1_to_xb_tready, ep0_to_xb_tready, s_pcie_tready, s_eth1_tready, s_eth0_tready}),
+    .m_axis_tdata   ({xb_to_ep5_tdata, xb_to_ep4_tdata, xb_to_ep3_tdata, xb_to_ep2_tdata, xb_to_ep1_tdata, xb_to_ep0_tdata, m_pcie_tdata, m_eth1_tdata, m_eth0_tdata}),
+    .m_axis_tlast   ({xb_to_ep5_tlast, xb_to_ep4_tlast, xb_to_ep3_tlast, xb_to_ep2_tlast, xb_to_ep1_tlast, xb_to_ep0_tlast, m_pcie_tlast, m_eth1_tlast, m_eth0_tlast}),
+    .m_axis_tvalid  ({xb_to_ep5_tvalid, xb_to_ep4_tvalid, xb_to_ep3_tvalid, xb_to_ep2_tvalid, xb_to_ep1_tvalid, xb_to_ep0_tvalid, m_pcie_tvalid, m_eth1_tvalid, m_eth0_tvalid}),
+    .m_axis_tready  ({xb_to_ep5_tready, xb_to_ep4_tready, xb_to_ep3_tready, xb_to_ep2_tready, xb_to_ep1_tready, xb_to_ep0_tready, m_pcie_tready, m_eth1_tready, m_eth0_tready}),
     .ext_rtcfg_stb  (1'h0),
     .ext_rtcfg_addr (16'h0),
     .ext_rtcfg_data (32'h0),
@@ -457,6 +473,128 @@ module rfnoc_image_core #(
     .signal_data_err    (1'b0              )
   );
 
+  wire [CHDR_W-1:0] m_ep4_out0_tdata;
+  wire              m_ep4_out0_tlast;
+  wire              m_ep4_out0_tvalid;
+  wire              m_ep4_out0_tready;
+  wire [CHDR_W-1:0] s_ep4_in0_tdata;
+  wire              s_ep4_in0_tlast;
+  wire              s_ep4_in0_tvalid;
+  wire              s_ep4_in0_tready;
+  wire [31:0]       m_ep4_ctrl_tdata , s_ep4_ctrl_tdata ;
+  wire              m_ep4_ctrl_tlast , s_ep4_ctrl_tlast ;
+  wire              m_ep4_ctrl_tvalid, s_ep4_ctrl_tvalid;
+  wire              m_ep4_ctrl_tready, s_ep4_ctrl_tready;
+
+  chdr_stream_endpoint #(
+    .PROTOVER           (PROTOVER),
+    .CHDR_W             (CHDR_W),
+    .AXIS_CTRL_EN       (0),
+    .AXIS_DATA_EN       (1),
+    .NUM_DATA_I         (1),
+    .NUM_DATA_O         (1),
+    .INST_NUM           (4),
+    .CTRL_XBAR_PORT     (5),
+    .INGRESS_BUFF_SIZE  (12),
+    .MTU                (MTU),
+    .REPORT_STRM_ERRS   (1)
+  ) ep4_i (
+    .rfnoc_chdr_clk     (rfnoc_chdr_clk    ),
+    .rfnoc_chdr_rst     (rfnoc_chdr_rst    ),
+    .rfnoc_ctrl_clk     (rfnoc_ctrl_clk    ),
+    .rfnoc_ctrl_rst     (rfnoc_ctrl_rst    ),
+    .device_id          (device_id         ),
+    .s_axis_chdr_tdata  (xb_to_ep4_tdata  ),
+    .s_axis_chdr_tlast  (xb_to_ep4_tlast  ),
+    .s_axis_chdr_tvalid (xb_to_ep4_tvalid ),
+    .s_axis_chdr_tready (xb_to_ep4_tready ),
+    .m_axis_chdr_tdata  (ep4_to_xb_tdata  ),
+    .m_axis_chdr_tlast  (ep4_to_xb_tlast  ),
+    .m_axis_chdr_tvalid (ep4_to_xb_tvalid ),
+    .m_axis_chdr_tready (ep4_to_xb_tready ),
+    .s_axis_data_tdata  ({s_ep4_in0_tdata}),
+    .s_axis_data_tlast  ({s_ep4_in0_tlast}),
+    .s_axis_data_tvalid ({s_ep4_in0_tvalid}),
+    .s_axis_data_tready ({s_ep4_in0_tready}),
+    .m_axis_data_tdata  ({m_ep4_out0_tdata}),
+    .m_axis_data_tlast  ({m_ep4_out0_tlast}),
+    .m_axis_data_tvalid ({m_ep4_out0_tvalid}),
+    .m_axis_data_tready ({m_ep4_out0_tready}),
+    .s_axis_ctrl_tdata  (s_ep4_ctrl_tdata ),
+    .s_axis_ctrl_tlast  (s_ep4_ctrl_tlast ),
+    .s_axis_ctrl_tvalid (s_ep4_ctrl_tvalid),
+    .s_axis_ctrl_tready (s_ep4_ctrl_tready),
+    .m_axis_ctrl_tdata  (m_ep4_ctrl_tdata ),
+    .m_axis_ctrl_tlast  (m_ep4_ctrl_tlast ),
+    .m_axis_ctrl_tvalid (m_ep4_ctrl_tvalid),
+    .m_axis_ctrl_tready (m_ep4_ctrl_tready),
+    .strm_seq_err_stb   (                  ),
+    .strm_data_err_stb  (                  ),
+    .strm_route_err_stb (                  ),
+    .signal_data_err    (1'b0              )
+  );
+
+  wire [CHDR_W-1:0] m_ep5_out0_tdata;
+  wire              m_ep5_out0_tlast;
+  wire              m_ep5_out0_tvalid;
+  wire              m_ep5_out0_tready;
+  wire [CHDR_W-1:0] s_ep5_in0_tdata;
+  wire              s_ep5_in0_tlast;
+  wire              s_ep5_in0_tvalid;
+  wire              s_ep5_in0_tready;
+  wire [31:0]       m_ep5_ctrl_tdata , s_ep5_ctrl_tdata ;
+  wire              m_ep5_ctrl_tlast , s_ep5_ctrl_tlast ;
+  wire              m_ep5_ctrl_tvalid, s_ep5_ctrl_tvalid;
+  wire              m_ep5_ctrl_tready, s_ep5_ctrl_tready;
+
+  chdr_stream_endpoint #(
+    .PROTOVER           (PROTOVER),
+    .CHDR_W             (CHDR_W),
+    .AXIS_CTRL_EN       (0),
+    .AXIS_DATA_EN       (1),
+    .NUM_DATA_I         (1),
+    .NUM_DATA_O         (1),
+    .INST_NUM           (5),
+    .CTRL_XBAR_PORT     (6),
+    .INGRESS_BUFF_SIZE  (12),
+    .MTU                (MTU),
+    .REPORT_STRM_ERRS   (1)
+  ) ep5_i (
+    .rfnoc_chdr_clk     (rfnoc_chdr_clk    ),
+    .rfnoc_chdr_rst     (rfnoc_chdr_rst    ),
+    .rfnoc_ctrl_clk     (rfnoc_ctrl_clk    ),
+    .rfnoc_ctrl_rst     (rfnoc_ctrl_rst    ),
+    .device_id          (device_id         ),
+    .s_axis_chdr_tdata  (xb_to_ep5_tdata  ),
+    .s_axis_chdr_tlast  (xb_to_ep5_tlast  ),
+    .s_axis_chdr_tvalid (xb_to_ep5_tvalid ),
+    .s_axis_chdr_tready (xb_to_ep5_tready ),
+    .m_axis_chdr_tdata  (ep5_to_xb_tdata  ),
+    .m_axis_chdr_tlast  (ep5_to_xb_tlast  ),
+    .m_axis_chdr_tvalid (ep5_to_xb_tvalid ),
+    .m_axis_chdr_tready (ep5_to_xb_tready ),
+    .s_axis_data_tdata  ({s_ep5_in0_tdata}),
+    .s_axis_data_tlast  ({s_ep5_in0_tlast}),
+    .s_axis_data_tvalid ({s_ep5_in0_tvalid}),
+    .s_axis_data_tready ({s_ep5_in0_tready}),
+    .m_axis_data_tdata  ({m_ep5_out0_tdata}),
+    .m_axis_data_tlast  ({m_ep5_out0_tlast}),
+    .m_axis_data_tvalid ({m_ep5_out0_tvalid}),
+    .m_axis_data_tready ({m_ep5_out0_tready}),
+    .s_axis_ctrl_tdata  (s_ep5_ctrl_tdata ),
+    .s_axis_ctrl_tlast  (s_ep5_ctrl_tlast ),
+    .s_axis_ctrl_tvalid (s_ep5_ctrl_tvalid),
+    .s_axis_ctrl_tready (s_ep5_ctrl_tready),
+    .m_axis_ctrl_tdata  (m_ep5_ctrl_tdata ),
+    .m_axis_ctrl_tlast  (m_ep5_ctrl_tlast ),
+    .m_axis_ctrl_tvalid (m_ep5_ctrl_tvalid),
+    .m_axis_ctrl_tready (m_ep5_ctrl_tready),
+    .strm_seq_err_stb   (                  ),
+    .strm_data_err_stb  (                  ),
+    .strm_route_err_stb (                  ),
+    .signal_data_err    (1'b0              )
+  );
+
 
 
   // ----------------------------------------------------
@@ -491,10 +629,14 @@ module rfnoc_image_core #(
   wire              m_radio1_ctrl_tlast ,   s_radio1_ctrl_tlast ;
   wire              m_radio1_ctrl_tvalid,   s_radio1_ctrl_tvalid;
   wire              m_radio1_ctrl_tready,   s_radio1_ctrl_tready;
+  wire [31:0]       m_replay0_ctrl_tdata ,   s_replay0_ctrl_tdata ;
+  wire              m_replay0_ctrl_tlast ,   s_replay0_ctrl_tlast ;
+  wire              m_replay0_ctrl_tvalid,   s_replay0_ctrl_tvalid;
+  wire              m_replay0_ctrl_tready,   s_replay0_ctrl_tready;
 
   axis_ctrl_crossbar_nxn #(
     .WIDTH            (32),
-    .NPORTS           (8),
+    .NPORTS           (9),
     .TOPOLOGY         ("TORUS"),
     .INGRESS_BUFF_SIZE(5),
     .ROUTER_BUFF_SIZE (5),
@@ -503,32 +645,32 @@ module rfnoc_image_core #(
   ) ctrl_xb_i (
     .clk              (rfnoc_ctrl_clk),
     .reset            (rfnoc_ctrl_rst),
-    .s_axis_tdata     ({m_radio1_ctrl_tdata , m_ddc1_ctrl_tdata , m_duc1_ctrl_tdata , m_radio0_ctrl_tdata , m_ddc0_ctrl_tdata , m_duc0_ctrl_tdata , m_ep0_ctrl_tdata , m_core_ctrl_tdata }),
-    .s_axis_tvalid    ({m_radio1_ctrl_tvalid, m_ddc1_ctrl_tvalid, m_duc1_ctrl_tvalid, m_radio0_ctrl_tvalid, m_ddc0_ctrl_tvalid, m_duc0_ctrl_tvalid, m_ep0_ctrl_tvalid, m_core_ctrl_tvalid}),
-    .s_axis_tlast     ({m_radio1_ctrl_tlast , m_ddc1_ctrl_tlast , m_duc1_ctrl_tlast , m_radio0_ctrl_tlast , m_ddc0_ctrl_tlast , m_duc0_ctrl_tlast , m_ep0_ctrl_tlast , m_core_ctrl_tlast }),
-    .s_axis_tready    ({m_radio1_ctrl_tready, m_ddc1_ctrl_tready, m_duc1_ctrl_tready, m_radio0_ctrl_tready, m_ddc0_ctrl_tready, m_duc0_ctrl_tready, m_ep0_ctrl_tready, m_core_ctrl_tready}),
-    .m_axis_tdata     ({s_radio1_ctrl_tdata , s_ddc1_ctrl_tdata , s_duc1_ctrl_tdata , s_radio0_ctrl_tdata , s_ddc0_ctrl_tdata , s_duc0_ctrl_tdata , s_ep0_ctrl_tdata , s_core_ctrl_tdata }),
-    .m_axis_tvalid    ({s_radio1_ctrl_tvalid, s_ddc1_ctrl_tvalid, s_duc1_ctrl_tvalid, s_radio0_ctrl_tvalid, s_ddc0_ctrl_tvalid, s_duc0_ctrl_tvalid, s_ep0_ctrl_tvalid, s_core_ctrl_tvalid}),
-    .m_axis_tlast     ({s_radio1_ctrl_tlast , s_ddc1_ctrl_tlast , s_duc1_ctrl_tlast , s_radio0_ctrl_tlast , s_ddc0_ctrl_tlast , s_duc0_ctrl_tlast , s_ep0_ctrl_tlast , s_core_ctrl_tlast }),
-    .m_axis_tready    ({s_radio1_ctrl_tready, s_ddc1_ctrl_tready, s_duc1_ctrl_tready, s_radio0_ctrl_tready, s_ddc0_ctrl_tready, s_duc0_ctrl_tready, s_ep0_ctrl_tready, s_core_ctrl_tready}),
+    .s_axis_tdata     ({m_replay0_ctrl_tdata , m_radio1_ctrl_tdata , m_ddc1_ctrl_tdata , m_duc1_ctrl_tdata , m_radio0_ctrl_tdata , m_ddc0_ctrl_tdata , m_duc0_ctrl_tdata , m_ep0_ctrl_tdata , m_core_ctrl_tdata }),
+    .s_axis_tvalid    ({m_replay0_ctrl_tvalid, m_radio1_ctrl_tvalid, m_ddc1_ctrl_tvalid, m_duc1_ctrl_tvalid, m_radio0_ctrl_tvalid, m_ddc0_ctrl_tvalid, m_duc0_ctrl_tvalid, m_ep0_ctrl_tvalid, m_core_ctrl_tvalid}),
+    .s_axis_tlast     ({m_replay0_ctrl_tlast , m_radio1_ctrl_tlast , m_ddc1_ctrl_tlast , m_duc1_ctrl_tlast , m_radio0_ctrl_tlast , m_ddc0_ctrl_tlast , m_duc0_ctrl_tlast , m_ep0_ctrl_tlast , m_core_ctrl_tlast }),
+    .s_axis_tready    ({m_replay0_ctrl_tready, m_radio1_ctrl_tready, m_ddc1_ctrl_tready, m_duc1_ctrl_tready, m_radio0_ctrl_tready, m_ddc0_ctrl_tready, m_duc0_ctrl_tready, m_ep0_ctrl_tready, m_core_ctrl_tready}),
+    .m_axis_tdata     ({s_replay0_ctrl_tdata , s_radio1_ctrl_tdata , s_ddc1_ctrl_tdata , s_duc1_ctrl_tdata , s_radio0_ctrl_tdata , s_ddc0_ctrl_tdata , s_duc0_ctrl_tdata , s_ep0_ctrl_tdata , s_core_ctrl_tdata }),
+    .m_axis_tvalid    ({s_replay0_ctrl_tvalid, s_radio1_ctrl_tvalid, s_ddc1_ctrl_tvalid, s_duc1_ctrl_tvalid, s_radio0_ctrl_tvalid, s_ddc0_ctrl_tvalid, s_duc0_ctrl_tvalid, s_ep0_ctrl_tvalid, s_core_ctrl_tvalid}),
+    .m_axis_tlast     ({s_replay0_ctrl_tlast , s_radio1_ctrl_tlast , s_ddc1_ctrl_tlast , s_duc1_ctrl_tlast , s_radio0_ctrl_tlast , s_ddc0_ctrl_tlast , s_duc0_ctrl_tlast , s_ep0_ctrl_tlast , s_core_ctrl_tlast }),
+    .m_axis_tready    ({s_replay0_ctrl_tready, s_radio1_ctrl_tready, s_ddc1_ctrl_tready, s_duc1_ctrl_tready, s_radio0_ctrl_tready, s_ddc0_ctrl_tready, s_duc0_ctrl_tready, s_ep0_ctrl_tready, s_core_ctrl_tready}),
     .deadlock_detected()
   );
 
   // ----------------------------------------------------
   // RFNoC Core Kernel
   // ----------------------------------------------------
-  wire [(512*6)-1:0] rfnoc_core_config, rfnoc_core_status;
+  wire [(512*7)-1:0] rfnoc_core_config, rfnoc_core_status;
 
   rfnoc_core_kernel #(
     .PROTOVER            (PROTOVER),
     .DEVICE_TYPE         (16'hA300),
     .DEVICE_FAMILY       ("7SERIES"),
     .SAFE_START_CLKS     (0),
-    .NUM_BLOCKS          (6),
-    .NUM_STREAM_ENDPOINTS(4),
+    .NUM_BLOCKS          (7),
+    .NUM_STREAM_ENDPOINTS(6),
     .NUM_ENDPOINTS_CTRL  (1),
     .NUM_TRANSPORTS      (3),
-    .NUM_EDGES           (12),
+    .NUM_EDGES           (16),
     .CHDR_XBAR_PRESENT   (1),
     .EDGE_TBL_FILE       (EDGE_TBL_FILE)
   ) core_kernel_i (
@@ -917,6 +1059,145 @@ module rfnoc_image_core #(
 
 
   // ----------------------------------------------------
+  // replay0
+  // ----------------------------------------------------
+  wire              replay0_mem_clk;
+  wire [CHDR_W-1:0] s_replay0_in_1_tdata , s_replay0_in_0_tdata ;
+  wire              s_replay0_in_1_tlast , s_replay0_in_0_tlast ;
+  wire              s_replay0_in_1_tvalid, s_replay0_in_0_tvalid;
+  wire              s_replay0_in_1_tready, s_replay0_in_0_tready;
+  wire [CHDR_W-1:0] m_replay0_out_1_tdata , m_replay0_out_0_tdata ;
+  wire              m_replay0_out_1_tlast , m_replay0_out_0_tlast ;
+  wire              m_replay0_out_1_tvalid, m_replay0_out_0_tvalid;
+  wire              m_replay0_out_1_tready, m_replay0_out_0_tready;
+
+  //  axi_ram
+  wire [  1-1:0] replay0_axi_rst;
+  wire [  4-1:0] replay0_m_axi_awid;
+  wire [128-1:0] replay0_m_axi_awaddr;
+  wire [ 32-1:0] replay0_m_axi_awlen;
+  wire [ 12-1:0] replay0_m_axi_awsize;
+  wire [  8-1:0] replay0_m_axi_awburst;
+  wire [  4-1:0] replay0_m_axi_awlock;
+  wire [ 16-1:0] replay0_m_axi_awcache;
+  wire [ 12-1:0] replay0_m_axi_awprot;
+  wire [ 16-1:0] replay0_m_axi_awqos;
+  wire [ 16-1:0] replay0_m_axi_awregion;
+  wire [  4-1:0] replay0_m_axi_awuser;
+  wire [  4-1:0] replay0_m_axi_awvalid;
+  wire [  4-1:0] replay0_m_axi_awready;
+  wire [256-1:0] replay0_m_axi_wdata;
+  wire [ 32-1:0] replay0_m_axi_wstrb;
+  wire [  4-1:0] replay0_m_axi_wlast;
+  wire [  4-1:0] replay0_m_axi_wuser;
+  wire [  4-1:0] replay0_m_axi_wvalid;
+  wire [  4-1:0] replay0_m_axi_wready;
+  wire [  4-1:0] replay0_m_axi_bid;
+  wire [  8-1:0] replay0_m_axi_bresp;
+  wire [  4-1:0] replay0_m_axi_buser;
+  wire [  4-1:0] replay0_m_axi_bvalid;
+  wire [  4-1:0] replay0_m_axi_bready;
+  wire [  4-1:0] replay0_m_axi_arid;
+  wire [128-1:0] replay0_m_axi_araddr;
+  wire [ 32-1:0] replay0_m_axi_arlen;
+  wire [ 12-1:0] replay0_m_axi_arsize;
+  wire [  8-1:0] replay0_m_axi_arburst;
+  wire [  4-1:0] replay0_m_axi_arlock;
+  wire [ 16-1:0] replay0_m_axi_arcache;
+  wire [ 12-1:0] replay0_m_axi_arprot;
+  wire [ 16-1:0] replay0_m_axi_arqos;
+  wire [ 16-1:0] replay0_m_axi_arregion;
+  wire [  4-1:0] replay0_m_axi_aruser;
+  wire [  4-1:0] replay0_m_axi_arvalid;
+  wire [  4-1:0] replay0_m_axi_arready;
+  wire [  4-1:0] replay0_m_axi_rid;
+  wire [256-1:0] replay0_m_axi_rdata;
+  wire [  8-1:0] replay0_m_axi_rresp;
+  wire [  4-1:0] replay0_m_axi_rlast;
+  wire [  4-1:0] replay0_m_axi_ruser;
+  wire [  4-1:0] replay0_m_axi_rvalid;
+  wire [  4-1:0] replay0_m_axi_rready;
+
+  rfnoc_block_replay #(
+    .THIS_PORTID(8),
+    .CHDR_W(CHDR_W),
+    .NUM_PORTS(2),
+    .MEM_ADDR_W(30),
+    .MEM_DATA_W(64),
+    .MTU(MTU)
+  ) b_replay0_6 (
+    .rfnoc_chdr_clk     (rfnoc_chdr_clk),
+    .rfnoc_ctrl_clk     (rfnoc_ctrl_clk),
+    .mem_clk(replay0_mem_clk),
+    .rfnoc_core_config  (rfnoc_core_config[512*7-1:512*6]),
+    .rfnoc_core_status  (rfnoc_core_status[512*7-1:512*6]),
+
+    .axi_rst(replay0_axi_rst),
+    .m_axi_awid(replay0_m_axi_awid),
+    .m_axi_awaddr(replay0_m_axi_awaddr),
+    .m_axi_awlen(replay0_m_axi_awlen),
+    .m_axi_awsize(replay0_m_axi_awsize),
+    .m_axi_awburst(replay0_m_axi_awburst),
+    .m_axi_awlock(replay0_m_axi_awlock),
+    .m_axi_awcache(replay0_m_axi_awcache),
+    .m_axi_awprot(replay0_m_axi_awprot),
+    .m_axi_awqos(replay0_m_axi_awqos),
+    .m_axi_awregion(replay0_m_axi_awregion),
+    .m_axi_awuser(replay0_m_axi_awuser),
+    .m_axi_awvalid(replay0_m_axi_awvalid),
+    .m_axi_awready(replay0_m_axi_awready),
+    .m_axi_wdata(replay0_m_axi_wdata),
+    .m_axi_wstrb(replay0_m_axi_wstrb),
+    .m_axi_wlast(replay0_m_axi_wlast),
+    .m_axi_wuser(replay0_m_axi_wuser),
+    .m_axi_wvalid(replay0_m_axi_wvalid),
+    .m_axi_wready(replay0_m_axi_wready),
+    .m_axi_bid(replay0_m_axi_bid),
+    .m_axi_bresp(replay0_m_axi_bresp),
+    .m_axi_buser(replay0_m_axi_buser),
+    .m_axi_bvalid(replay0_m_axi_bvalid),
+    .m_axi_bready(replay0_m_axi_bready),
+    .m_axi_arid(replay0_m_axi_arid),
+    .m_axi_araddr(replay0_m_axi_araddr),
+    .m_axi_arlen(replay0_m_axi_arlen),
+    .m_axi_arsize(replay0_m_axi_arsize),
+    .m_axi_arburst(replay0_m_axi_arburst),
+    .m_axi_arlock(replay0_m_axi_arlock),
+    .m_axi_arcache(replay0_m_axi_arcache),
+    .m_axi_arprot(replay0_m_axi_arprot),
+    .m_axi_arqos(replay0_m_axi_arqos),
+    .m_axi_arregion(replay0_m_axi_arregion),
+    .m_axi_aruser(replay0_m_axi_aruser),
+    .m_axi_arvalid(replay0_m_axi_arvalid),
+    .m_axi_arready(replay0_m_axi_arready),
+    .m_axi_rid(replay0_m_axi_rid),
+    .m_axi_rdata(replay0_m_axi_rdata),
+    .m_axi_rresp(replay0_m_axi_rresp),
+    .m_axi_rlast(replay0_m_axi_rlast),
+    .m_axi_ruser(replay0_m_axi_ruser),
+    .m_axi_rvalid(replay0_m_axi_rvalid),
+    .m_axi_rready(replay0_m_axi_rready),
+
+    .s_rfnoc_chdr_tdata ({s_replay0_in_1_tdata , s_replay0_in_0_tdata }),
+    .s_rfnoc_chdr_tlast ({s_replay0_in_1_tlast , s_replay0_in_0_tlast }),
+    .s_rfnoc_chdr_tvalid({s_replay0_in_1_tvalid, s_replay0_in_0_tvalid}),
+    .s_rfnoc_chdr_tready({s_replay0_in_1_tready, s_replay0_in_0_tready}),
+    .m_rfnoc_chdr_tdata ({m_replay0_out_1_tdata , m_replay0_out_0_tdata }),
+    .m_rfnoc_chdr_tlast ({m_replay0_out_1_tlast , m_replay0_out_0_tlast }),
+    .m_rfnoc_chdr_tvalid({m_replay0_out_1_tvalid, m_replay0_out_0_tvalid}),
+    .m_rfnoc_chdr_tready({m_replay0_out_1_tready, m_replay0_out_0_tready}),
+    .s_rfnoc_ctrl_tdata (s_replay0_ctrl_tdata ),
+    .s_rfnoc_ctrl_tlast (s_replay0_ctrl_tlast ),
+    .s_rfnoc_ctrl_tvalid(s_replay0_ctrl_tvalid),
+    .s_rfnoc_ctrl_tready(s_replay0_ctrl_tready),
+    .m_rfnoc_ctrl_tdata (m_replay0_ctrl_tdata ),
+    .m_rfnoc_ctrl_tlast (m_replay0_ctrl_tlast ),
+    .m_rfnoc_ctrl_tvalid(m_replay0_ctrl_tvalid),
+    .m_rfnoc_ctrl_tready(m_replay0_ctrl_tready)
+  );
+
+
+  // ----------------------------------------------------
   // Static Router
   // ----------------------------------------------------
   assign s_duc0_in_0_tdata = m_ep0_out0_tdata ;
@@ -979,6 +1260,26 @@ module rfnoc_image_core #(
   assign s_ep3_in0_tvalid = m_ddc1_out_1_tvalid;
   assign m_ddc1_out_1_tready = s_ep3_in0_tready;
 
+  assign s_replay0_in_0_tdata = m_ep4_out0_tdata ;
+  assign s_replay0_in_0_tlast = m_ep4_out0_tlast ;
+  assign s_replay0_in_0_tvalid = m_ep4_out0_tvalid;
+  assign m_ep4_out0_tready = s_replay0_in_0_tready;
+
+  assign s_ep4_in0_tdata = m_replay0_out_0_tdata ;
+  assign s_ep4_in0_tlast = m_replay0_out_0_tlast ;
+  assign s_ep4_in0_tvalid = m_replay0_out_0_tvalid;
+  assign m_replay0_out_0_tready = s_ep4_in0_tready;
+
+  assign s_replay0_in_1_tdata = m_ep5_out0_tdata ;
+  assign s_replay0_in_1_tlast = m_ep5_out0_tlast ;
+  assign s_replay0_in_1_tvalid = m_ep5_out0_tvalid;
+  assign m_ep5_out0_tready = s_replay0_in_1_tready;
+
+  assign s_ep5_in0_tdata = m_replay0_out_1_tdata ;
+  assign s_ep5_in0_tlast = m_replay0_out_1_tlast ;
+  assign s_ep5_in0_tvalid = m_replay0_out_1_tvalid;
+  assign m_replay0_out_1_tready = s_ep5_in0_tready;
+
 
   // ----------------------------------------------------
   // Unused Ports
@@ -1001,6 +1302,7 @@ module rfnoc_image_core #(
   assign radio1_radio_clk = radio_clk;
   assign ddc1_ce_clk = ce_clk;
   assign duc1_ce_clk = ce_clk;
+  assign replay0_mem_clk = dram_clk;
 
 
   // ----------------------------------------------------
@@ -1029,6 +1331,52 @@ module rfnoc_image_core #(
   assign radio1_m_ctrlport_resp_status = m_ctrlport_radio1_resp_status;
   assign radio1_m_ctrlport_resp_data = m_ctrlport_radio1_resp_data;
 
+  assign replay0_axi_rst = axi_rst;
+  assign m_axi_awid = replay0_m_axi_awid;
+  assign m_axi_awaddr = replay0_m_axi_awaddr;
+  assign m_axi_awlen = replay0_m_axi_awlen;
+  assign m_axi_awsize = replay0_m_axi_awsize;
+  assign m_axi_awburst = replay0_m_axi_awburst;
+  assign m_axi_awlock = replay0_m_axi_awlock;
+  assign m_axi_awcache = replay0_m_axi_awcache;
+  assign m_axi_awprot = replay0_m_axi_awprot;
+  assign m_axi_awqos = replay0_m_axi_awqos;
+  assign m_axi_awregion = replay0_m_axi_awregion;
+  assign m_axi_awuser = replay0_m_axi_awuser;
+  assign m_axi_awvalid = replay0_m_axi_awvalid;
+  assign replay0_m_axi_awready = m_axi_awready;
+  assign m_axi_wdata = replay0_m_axi_wdata;
+  assign m_axi_wstrb = replay0_m_axi_wstrb;
+  assign m_axi_wlast = replay0_m_axi_wlast;
+  assign m_axi_wuser = replay0_m_axi_wuser;
+  assign m_axi_wvalid = replay0_m_axi_wvalid;
+  assign replay0_m_axi_wready = m_axi_wready;
+  assign replay0_m_axi_bid = m_axi_bid;
+  assign replay0_m_axi_bresp = m_axi_bresp;
+  assign replay0_m_axi_buser = m_axi_buser;
+  assign replay0_m_axi_bvalid = m_axi_bvalid;
+  assign m_axi_bready = replay0_m_axi_bready;
+  assign m_axi_arid = replay0_m_axi_arid;
+  assign m_axi_araddr = replay0_m_axi_araddr;
+  assign m_axi_arlen = replay0_m_axi_arlen;
+  assign m_axi_arsize = replay0_m_axi_arsize;
+  assign m_axi_arburst = replay0_m_axi_arburst;
+  assign m_axi_arlock = replay0_m_axi_arlock;
+  assign m_axi_arcache = replay0_m_axi_arcache;
+  assign m_axi_arprot = replay0_m_axi_arprot;
+  assign m_axi_arqos = replay0_m_axi_arqos;
+  assign m_axi_arregion = replay0_m_axi_arregion;
+  assign m_axi_aruser = replay0_m_axi_aruser;
+  assign m_axi_arvalid = replay0_m_axi_arvalid;
+  assign replay0_m_axi_arready = m_axi_arready;
+  assign replay0_m_axi_rid = m_axi_rid;
+  assign replay0_m_axi_rdata = m_axi_rdata;
+  assign replay0_m_axi_rresp = m_axi_rresp;
+  assign replay0_m_axi_rlast = m_axi_rlast;
+  assign replay0_m_axi_ruser = m_axi_ruser;
+  assign replay0_m_axi_rvalid = m_axi_rvalid;
+  assign m_axi_rready = replay0_m_axi_rready;
+
   assign radio0_radio_rx_data = radio_rx_data_radio0;
   assign radio0_radio_rx_stb = radio_rx_stb_radio0;
   assign radio_rx_running_radio0 = radio0_radio_rx_running;
diff --git a/fpga/usrp3/top/x300/x310_rfnoc_image_core.yml b/fpga/usrp3/top/x300/x310_rfnoc_image_core.yml
index 5d6a98c7d..84b5f0234 100644
--- a/fpga/usrp3/top/x300/x310_rfnoc_image_core.yml
+++ b/fpga/usrp3/top/x300/x310_rfnoc_image_core.yml
@@ -28,6 +28,14 @@ stream_endpoints:
     ctrl: False                     # Endpoint passes control traffic
     data: True                      # Endpoint passes data traffic
     buff_size: 0                    # Ingress buffer size for data
+  ep4:                       # Stream endpoint name
+    ctrl: False                     # Endpoint passes control traffic
+    data: True                      # Endpoint passes data traffic
+    buff_size: 4096                 # Ingress buffer size for data
+  ep5:                       # Stream endpoint name
+    ctrl: False                     # Endpoint passes control traffic
+    data: True                      # Endpoint passes data traffic
+    buff_size: 4096                 # Ingress buffer size for data
 
 # A list of all NoC blocks in design
 # ----------------------------------
@@ -52,16 +60,11 @@ noc_blocks:
       NUM_PORTS: 2
   radio1:
     block_desc: 'radio_2x64.yml'
-  # These parameters are for reference, in case a DRAM FIFO is required
-  #fifo0:
-    #block_desc: 'axi_ram_fifo_2x64.yml'
-    #parameters:
-      ## These parameters match the interface on the x300/X310
-      #MEM_DATA_W: 64
-      #MEM_ADDR_W: 30
-      #FIFO_ADDR_BASE: "{30'h02000000, 30'h00000000}"
-      #FIFO_ADDR_MASK: "{30'h01FFFFFF, 30'h01FFFFFF}"
-      #MEM_CLK_RATE: "300e6"
+  replay0:
+    block_desc: 'replay.yml'
+    parameters:
+      NUM_PORTS: 2
+      MEM_ADDR_W: 30
 
 # A list of all static connections in design
 # ------------------------------------------
@@ -89,9 +92,18 @@ connections:
   # radio1(1) to ep3 - RFB RX
   - { srcblk: radio1, srcport: out_1, dstblk: ddc1,   dstport: in_1 }
   - { srcblk: ddc1,   srcport: out_1, dstblk: ep3,    dstport: in0  }
+  # ep4 to replay0(0)
+  - { srcblk: ep4,     srcport: out0,  dstblk: replay0, dstport: in_0 }
+  # replay0(0) to ep4
+  - { srcblk: replay0, srcport: out_0, dstblk: ep4,     dstport: in0  }
+  # ep5 to replay0(1)
+  - { srcblk: ep5,     srcport: out0,  dstblk: replay0, dstport: in_1 }
+  # replay0(1) to ep5
+  - { srcblk: replay0, srcport: out_1, dstblk: ep5,     dstport: in0  }
   # BSP Connections
   - { srcblk: radio0, srcport: ctrl_port, dstblk: _device_, dstport: ctrlport_radio0 }
   - { srcblk: radio1, srcport: ctrl_port, dstblk: _device_, dstport: ctrlport_radio1 }
+  - { srcblk: replay0, srcport: axi_ram, dstblk: _device_, dstport: dram }
   - { srcblk: _device_, srcport: x300_radio0, dstblk: radio0, dstport: x300_radio }
   - { srcblk: _device_, srcport: x300_radio1, dstblk: radio1, dstport: x300_radio }
   - { srcblk: _device_, srcport: time_keeper, dstblk: radio0, dstport: time_keeper }
@@ -111,3 +123,4 @@ clk_domains:
     - { srcblk: _device_, srcport: radio, dstblk: radio1, dstport: radio }
     - { srcblk: _device_, srcport: ce,    dstblk: ddc1,   dstport: ce    }
     - { srcblk: _device_, srcport: ce,    dstblk: duc1,   dstport: ce    }
+    - { srcblk: _device_, srcport: dram,  dstblk: replay0, dstport: mem  }
diff --git a/fpga/usrp3/top/x300/x310_static_router.hex b/fpga/usrp3/top/x300/x310_static_router.hex
index 53635706f..eb493cee8 100644
--- a/fpga/usrp3/top/x300/x310_static_router.hex
+++ b/fpga/usrp3/top/x300/x310_static_router.hex
@@ -1,13 +1,17 @@
-0000000C
-00400140
-014001c0
-01c00180
-01800040
-01c10181
-01810080
-00c00200
-02000280
-02800240
-024000c0
-02810241
-02410100
+00000010
+004001c0
+01c00240
+02400200
+02000040
+02410201
+02010080
+00c00280
+02800300
+030002c0
+02c000c0
+030102c1
+02c10100
+01400340
+03400140
+01800341
+03410180