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authorBen Hilburn <ben.hilburn@ettus.com>2014-05-14 11:42:19 -0700
committerBen Hilburn <ben.hilburn@ettus.com>2014-05-14 11:42:19 -0700
commit00711ba213dde8aa0a099d2b18d3da0a33e6af79 (patch)
tree612f616ebbf8080b5dc9cb5d64a8062e9aa3a498 /fpga/usrp3/top/x300
parent5de0bfce3f03cc45a1eed93dc1b8df1b188b5040 (diff)
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fpga: updating b200 and x300 FPGA source code for latest images
Diffstat (limited to 'fpga/usrp3/top/x300')
-rw-r--r--fpga/usrp3/top/x300/Makefile125
-rw-r--r--fpga/usrp3/top/x300/bus_int.v2
-rwxr-xr-xfpga/usrp3/top/x300/coregen/bootram.coe6300
-rw-r--r--fpga/usrp3/top/x300/coregen/bootram.ngc3
-rw-r--r--fpga/usrp3/top/x300/coregen/bus_clk_gen.gise2
-rwxr-xr-xfpga/usrp3/top/x300/coregen/bus_clk_gen.ucf10
-rwxr-xr-xfpga/usrp3/top/x300/coregen/bus_clk_gen.v10
-rwxr-xr-xfpga/usrp3/top/x300/coregen/bus_clk_gen.veo4
-rw-r--r--fpga/usrp3/top/x300/coregen/bus_clk_gen.xco14
-rw-r--r--fpga/usrp3/top/x300/coregen/bus_clk_gen.xise49
-rw-r--r--fpga/usrp3/top/x300/coregen/bus_clk_gen/clk_wiz_v3_6_readme.txt7
-rw-r--r--fpga/usrp3/top/x300/coregen/bus_clk_gen/doc/clk_wiz_v3_6_readme.txt7
-rw-r--r--fpga/usrp3/top/x300/coregen/bus_clk_gen/doc/clk_wiz_v3_6_vinfo.html9
-rwxr-xr-xfpga/usrp3/top/x300/coregen/bus_clk_gen/example_design/bus_clk_gen_exdes.ucf10
-rwxr-xr-xfpga/usrp3/top/x300/coregen/bus_clk_gen/simulation/bus_clk_gen_tb.v4
-rwxr-xr-xfpga/usrp3/top/x300/coregen/bus_clk_gen/simulation/timing/bus_clk_gen_tb.v4
-rwxr-xr-xfpga/usrp3/top/x300/coregen/bus_clk_gen_xmdf.tcl12
-rw-r--r--fpga/usrp3/top/x300/x300.v394
-rw-r--r--fpga/usrp3/top/x300/x300_pcie_int.v64
-rw-r--r--fpga/usrp3/top/x300/x300_pcie_int_tb.v2
20 files changed, 3508 insertions, 3524 deletions
diff --git a/fpga/usrp3/top/x300/Makefile b/fpga/usrp3/top/x300/Makefile
index 1c47bdd82..a5a0b22c8 100644
--- a/fpga/usrp3/top/x300/Makefile
+++ b/fpga/usrp3/top/x300/Makefile
@@ -2,8 +2,6 @@
# Copyright 2012-2013 Ettus Research LLC
#
-# Uncomment following line to build with internal SRAM FIFOS instead of DRAM based FIFO's
-#OPTIONS += NO_DRAM_FIFOS=1
# Uncomment the following lines to build radio's with no DSP's
#OPTIONS += DELETE_DSP0=1
#OPTIONS += DELETE_DSP1=1
@@ -18,113 +16,84 @@ XGIGE_DEFS=ETH10G_PORT0=1 ETH10G_PORT1=1 BUILD_10G=1 $(OPTIONS)
HYBRID_SRAM_DEFS=ETH10G_PORT1=1 BUILD_1G=1 BUILD_10G=1 NO_DRAM_FIFOS=1 SRAM_FIFO_SIZE=16 $(OPTIONS)
XGIGE_SRAM_DEFS=ETH10G_PORT0=1 ETH10G_PORT1=1 BUILD_10G=1 NO_DRAM_FIFOS=1 SRAM_FIFO_SIZE=16 $(OPTIONS)
-all: X300 X310
- find -name "*.twr" | xargs grep constraint | grep met
-
-clean:
- rm -rf build*
-
-#Build X300_HGS and X300_XGS
-X300: X300_HGS X300_XGS
+X300: X300_HGS X300_HG X300_XGS X300_XG
-#Build X310_HGS and X310_XGS
-X310: X310_HGS X310_XGS
+X310: X310_HGS X310_HG X310_XGS X310_XG
-#Build DRAM Hybrid images
-DRAM: X300_HG X310_HG
+all: X300 X310
-#Build X300_HGS and X310_HGS
-HGS: X300_HGS X310_HGS
+clean:
+ rm -rf build-*_*
+ rm -rf build
+
+print_report = \
+ echo "========================================================================"; \
+ cat $(1) | grep "Design Summary:" -A 124; \
+ echo "========================================================================"; \
+ echo "Timing Summary:\n"; \
+ cat $(1) | grep constraint | grep met | grep -v "*"; \
+ echo "========================================================================";
+
+# post_build($1=Device, $2=Flavor)
+post_build = \
+ @$(call print_report,build-$(1)_$(2)/build.log) \
+ mkdir -p build; \
+ echo "Exporting bitstream files..."; \
+ cp build-$(1)_$(2)/x300.bin build/usrp_`echo $(1) | tr A-Z a-z`_fpga_$(2).bin; \
+ cp build-$(1)_$(2)/x300.bit build/usrp_`echo $(1) | tr A-Z a-z`_fpga_$(2).bit; \
+ echo "Generating LVBITX..."; \
+ $(CREATE_LVBITX) --input-bin=build-$(1)_$(2)/x300.bin --output-lvbitx=build/usrp_`echo $(1) | tr A-Z a-z`_fpga_$(2).lvbitx --device="USRP $(1)" x3x0_base.lvbitx; \
+ cp -f x3x0_base.lvbitx build/`echo $(1) | tr A-Z a-z`.lvbitx_base; \
+ echo "Exporting logs..."; \
+ cp build-$(1)_$(2)/build.log build/usrp_`echo $(1) | tr A-Z a-z`_fpga_$(2).log; \
+ cp build-$(1)_$(2)/x300.twr build/usrp_`echo $(1) | tr A-Z a-z`_fpga_$(2).twr; \
+ echo "\nDONE ... $(1)_$(2)\n";
-#Build X300_HGS and X310_HGS
-XGS: X300_XGS X310_XGS
#1Gig on both ports
X310_1G:
make -f Makefile.x300.inc bin NAME=$@ DEVICE=XC7K410T $(GIGE_DEFS) EXTRA_DEFS="$(GIGE_DEFS)"
- mkdir -p build
- cp build-X310/x300.bin build/usrp_x310_fpga_1G.bin
- cp build-X310/x300.bit build/usrp_x310_fpga_1G.bit
- $(CREATE_LVBITX) --input-bin=build-X310/x300.bin --output-lvbitx=build/usrp_x310_fpga_1G.lvbitx --device="USRP X310" x3x0_base.lvbitx
- cp -f x3x0_base.lvbitx build/x310.lvbitx_base
-
+ $(call post_build,X310,1G)
X300_1G:
make -f Makefile.x300.inc bin NAME=$@ DEVICE=XC7K325T $(GIGE_DEFS) EXTRA_DEFS="$(GIGE_DEFS)"
- mkdir -p build
- cp build-X300/x300.bin build/usrp_x300_fpga_1G.bin
- cp build-X300/x300.bit build/usrp_x300_fpga_1G.bit
- $(CREATE_LVBITX) --input-bin=build-X300/x300.bin --output-lvbitx=build/usrp_x300_fpga_1G.lvbitx --device="USRP X300" x3x0_base.lvbitx
- cp -f x3x0_base.lvbitx build/x300.lvbitx_base
+ $(call post_build,X300,1G)
#1Gig on port0, 10Gig on port1
X310_HG:
- make -f Makefile.x300.inc bin NAME=$@ DEVICE=XC7K410T $(HYBRID_DEFS) EXTRA_DEFS="$(HYBRID_DEFS)" FLOORPLAN="$(FLOORPLAN)"
- mkdir -p build
- cp build-X310_HG/x300.bin build/usrp_x310_fpga_HG.bin
- cp build-X310_HG/x300.bit build/usrp_x310_fpga_HG.bit
- $(CREATE_LVBITX) --input-bin=build-X310_HG/x300.bin --output-lvbitx=build/usrp_x310_fpga_HG.lvbitx --device="USRP X310" x3x0_base.lvbitx
- cp -f x3x0_base.lvbitx build/x310.lvbitx_base
+ make -f Makefile.x300.inc bin NAME=$@ DEVICE=XC7K410T $(HYBRID_DEFS) EXTRA_DEFS="$(HYBRID_DEFS)"
+ $(call post_build,X310,HG)
X300_HG:
- make -f Makefile.x300.inc bin NAME=$@ DEVICE=XC7K325T $(HYBRID_DEFS) EXTRA_DEFS="$(HYBRID_DEFS)" FLOORPLAN="$(FLOORPLAN)"
- mkdir -p build
- cp build-X300_HG/x300.bin build/usrp_x300_fpga_HG.bin
- cp build-X300_HG/x300.bit build/usrp_x300_fpga_HG.bit
- $(CREATE_LVBITX) --input-bin=build-X300_HG/x300.bin --output-lvbitx=build/usrp_x300_fpga_HG.lvbitx --device="USRP X300" x3x0_base.lvbitx
- cp -f x3x0_base.lvbitx build/x300.lvbitx_base
+ make -f Makefile.x300.inc bin NAME=$@ DEVICE=XC7K325T $(HYBRID_DEFS) EXTRA_DEFS="$(HYBRID_DEFS)"
+ $(call post_build,X300,HG)
#10Gig on both ports
X310_XG:
- make -f Makefile.x300.inc bin NAME=$@ DEVICE=XC7K410T $(XGIGE_DEFS) EXTRA_DEFS="$(XGIGE_DEFS)" FLOORPLAN="$(FLOORPLAN)"
- mkdir -p build
- cp build-X310_XG/x300.bin build/usrp_x310_fpga_XG.bin
- cp build-X310_XG/x300.bit build/usrp_x310_fpga_XG.bit
- $(CREATE_LVBITX) --input-bin=build-X310_XG/x300.bin --output-lvbitx=build/usrp_x310_fpga_XG.lvbitx --device="USRP X310" x3x0_base.lvbitx
- cp -f x3x0_base.lvbitx build/x310.lvbitx_base
+ make -f Makefile.x300.inc bin NAME=$@ DEVICE=XC7K410T $(XGIGE_DEFS) EXTRA_DEFS="$(XGIGE_DEFS)"
+ $(call post_build,X310,XG)
X300_XG:
- make -f Makefile.x300.inc bin NAME=$@ DEVICE=XC7K325T $(XGIGE_DEFS) EXTRA_DEFS="$(XGIGE_DEFS)" FLOORPLAN="$(FLOORPLAN)"
- mkdir -p build
- cp build-X300_XG/x300.bin build/usrp_x300_fpga_XG.bin
- cp build-X300_XG/x300.bit build/usrp_x300_fpga_XG.bit
- $(CREATE_LVBITX) --input-bin=build-X300_XG/x300.bin --output-lvbitx=build/usrp_x300_fpga_XG.lvbitx --device="USRP X300" x3x0_base.lvbitx
- cp -f x3x0_base.lvbitx build/x300.lvbitx_base
+ make -f Makefile.x300.inc bin NAME=$@ DEVICE=XC7K325T $(XGIGE_DEFS) EXTRA_DEFS="$(XGIGE_DEFS)"
+ $(call post_build,X300,XG)
# 1Gig on port0, 10Gig on port1, SRAM Tx FIFO's
X310_HGS:
- make -f Makefile.x300.inc bin NAME=$@ DEVICE=XC7K410T $(HYBRID_SRAM_DEFS) EXTRA_DEFS="$(HYBRID_SRAM_DEFS)" FLOORPLAN="$(FLOORPLAN)"
- mkdir -p build
- cp build-X310_HGS/x300.bin build/usrp_x310_fpga_HGS.bin
- cp build-X310_HGS/x300.bit build/usrp_x310_fpga_HGS.bit
- $(CREATE_LVBITX) --input-bin=build-X310_HGS/x300.bin --output-lvbitx=build/usrp_x310_fpga_HGS.lvbitx --device="USRP X310" x3x0_base.lvbitx
- cp -f x3x0_base.lvbitx build/x310.lvbitx_base
+ make -f Makefile.x300.inc bin NAME=$@ DEVICE=XC7K410T $(HYBRID_SRAM_DEFS) EXTRA_DEFS="$(HYBRID_SRAM_DEFS)"
+ $(call post_build,X310,HGS)
X300_HGS:
- make -f Makefile.x300.inc bin NAME=$@ DEVICE=XC7K325T $(HYBRID_SRAM_DEFS) EXTRA_DEFS="$(HYBRID_SRAM_DEFS)" FLOORPLAN="$(FLOORPLAN)"
- mkdir -p build
- cp build-X300_HGS/x300.bin build/usrp_x300_fpga_HGS.bin
- cp build-X300_HGS/x300.bit build/usrp_x300_fpga_HGS.bit
- $(CREATE_LVBITX) --input-bin=build-X300_HGS/x300.bin --output-lvbitx=build/usrp_x300_fpga_HGS.lvbitx --device="USRP X300" x3x0_base.lvbitx
- cp -f x3x0_base.lvbitx build/x300.lvbitx_base
+ make -f Makefile.x300.inc bin NAME=$@ DEVICE=XC7K325T $(HYBRID_SRAM_DEFS) EXTRA_DEFS="$(HYBRID_SRAM_DEFS)"
+ $(call post_build,X300,HGS)
# 1Gig on both ports, SRAM Tx FIFO's
X310_XGS:
- make -f Makefile.x300.inc bin NAME=$@ DEVICE=XC7K410T $(XGIGE_SRAM_DEFS) EXTRA_DEFS="$(XGIGE_SRAM_DEFS)" FLOORPLAN="$(FLOORPLAN)"
- mkdir -p build
- cp build-X310_XGS/x300.bin build/usrp_x310_fpga_XGS.bin
- cp build-X310_XGS/x300.bit build/usrp_x310_fpga_XGS.bit
- $(CREATE_LVBITX) --input-bin=build-X310_XGS/x300.bin --output-lvbitx=build/usrp_x310_fpga_XGS.lvbitx --device="USRP X310" x3x0_base.lvbitx
- cp -f x3x0_base.lvbitx build/x310.lvbitx_base
+ make -f Makefile.x300.inc bin NAME=$@ DEVICE=XC7K410T $(XGIGE_SRAM_DEFS) EXTRA_DEFS="$(XGIGE_SRAM_DEFS)"
+ $(call post_build,X310,XGS)
X300_XGS:
- make -f Makefile.x300.inc bin NAME=$@ DEVICE=XC7K325T $(XGIGE_SRAM_DEFS) EXTRA_DEFS="$(XGIGE_SRAM_DEFS)" FLOORPLAN="$(FLOORPLAN)"
- mkdir -p build
- cp build-X300_XGS/x300.bin build/usrp_x300_fpga_XGS.bin
- cp build-X300_XGS/x300.bit build/usrp_x300_fpga_XGS.bit
- $(CREATE_LVBITX) --input-bin=build-X300_XGS/x300.bin --output-lvbitx=build/usrp_x300_fpga_XGS.lvbitx --device="USRP X300" x3x0_base.lvbitx
- cp -f x3x0_base.lvbitx build/x300.lvbitx_base
-
+ make -f Makefile.x300.inc bin NAME=$@ DEVICE=XC7K325T $(XGIGE_SRAM_DEFS) EXTRA_DEFS="$(XGIGE_SRAM_DEFS)"
+ $(call post_build,X300,XGS)
.PHONY: all clean
diff --git a/fpga/usrp3/top/x300/bus_int.v b/fpga/usrp3/top/x300/bus_int.v
index aa5998bd3..416b327bb 100644
--- a/fpga/usrp3/top/x300/bus_int.v
+++ b/fpga/usrp3/top/x300/bus_int.v
@@ -141,7 +141,7 @@ module bus_int
localparam RB_BIST = 8'd128;
- localparam COMPAT_MAJOR = 16'h0004;
+ localparam COMPAT_MAJOR = 16'h0006;
localparam COMPAT_MINOR = 16'h0000;
wire [31:0] set_data;
diff --git a/fpga/usrp3/top/x300/coregen/bootram.coe b/fpga/usrp3/top/x300/coregen/bootram.coe
index c9045183a..b14aa4f1e 100755
--- a/fpga/usrp3/top/x300/coregen/bootram.coe
+++ b/fpga/usrp3/top/x300/coregen/bootram.coe
@@ -2,15 +2,15 @@ memory_initialization_radix=16;
memory_initialization_vector=
0b0b0b0b,
82700b0b,
-81978c0c,
+8196c80c,
3a0b0b80,
-ff8c0400,
+fec90400,
00000000,
00000000,
00000000,
80088408,
88080b0b,
-80ffd72d,
+80ff942d,
880c840c,
800c0400,
00000000,
@@ -162,7 +162,7 @@ c4040000,
00000000,
71fc0608,
0b0b8196,
-f8738306,
+b4738306,
10100508,
060b0b0b,
88aa0400,
@@ -170,8 +170,8 @@ f8738306,
00000000,
80088408,
88087575,
-0b0b80f6,
-b12d5050,
+0b0b80f5,
+ee2d5050,
80085688,
0c840c80,
0c510400,
@@ -179,7 +179,7 @@ b12d5050,
80088408,
88087575,
0b0b80f7,
-e32d5050,
+a02d5050,
80085688,
0c840c80,
0c510400,
@@ -209,7 +209,7 @@ e32d5050,
00000000,
00000000,
810b0b0b,
-8197880c,
+8196c40c,
51040000,
00000000,
00000000,
@@ -257,7 +257,7 @@ e32d5050,
00000000,
00000000,
82813f80,
-f8f83f04,
+f8b53f04,
10101010,
10101010,
10101010,
@@ -280,56 +280,56 @@ fc060c51,
0a100a53,
72ed3851,
51535104,
-81978808,
+8196c408,
802ea438,
-81978c08,
+8196c808,
822ebd38,
8380800b,
-0b0b819f,
-800c82a0,
-800b819f,
-840c8290,
-800b819f,
-880c04f8,
+0b0b819e,
+bc0c82a0,
+800b819e,
+c00c8290,
+800b819e,
+c40c04f8,
808080a4,
0b0b0b81,
-9f800cf8,
+9ebc0cf8,
80808280,
-0b819f84,
+0b819ec0,
0cf88080,
84800b81,
-9f880c04,
+9ec40c04,
80c0a880,
8c0b0b0b,
-819f800c,
+819ebc0c,
80c0a880,
-940b819f,
-840c0b0b,
-8181ac0b,
-819f880c,
+940b819e,
+c00c0b0b,
+8180e80b,
+819ec40c,
04ff3d0d,
-819f8c33,
+819ec833,
5170a738,
-81979408,
+8196d008,
70085252,
70802e94,
38841281,
-97940c70,
-2d819794,
+96d00c70,
+2d8196d0,
08700852,
5270ee38,
-810b819f,
-8c34833d,
+810b819e,
+c834833d,
0d040480,
3d0d0b0b,
-819efc08,
+819eb808,
802e8e38,
0b0b0b0b,
800b802e,
09810685,
38823d0d,
040b0b81,
-9efc510b,
+9eb8510b,
0b0bf5d4,
3f823d0d,
0404f93d,
@@ -355,59 +355,59 @@ b1387218,
5170800c,
893d0d04,
04e23d0d,
-8bef5283,
+8ba65283,
fa805198,
-c43f8bef,
+813f8ba6,
5283f280,
-5198ba3f,
+5197f73f,
8b885280,
-51a2e93f,
-81af5281,
-81b451a2,
-ea3f80d3,
-b993c052,
+51a2a63f,
+81a65281,
+80f051a2,
+a73f80cf,
+bcc3ab52,
83fc8051,
-98e03f80,
-d3b993c0,
+989d3f80,
+cfbcc3ab,
5283fe80,
-5198d33f,
-80d3b993,
-c05283f8,
-805198c6,
+5198903f,
+80cfbcc3,
+ab5283f8,
+80519883,
3f810b82,
c0840c82,
c0900855,
8a567481,
2e833881,
56755281,
-81e051a2,
-a63f82c0,
+819c51a1,
+e33f82c0,
9408558a,
5674812e,
83388156,
75528181,
-f851a28f,
+b451a1cc,
3fbffc53,
82808052,
-819f9051,
-a3a63f81,
-9f900852,
-81829051,
-a1f53f81,
-9f9051a7,
-f03f80e7,
-813f8d3d,
+819ecc51,
+a2e33f81,
+9ecc0852,
+8181cc51,
+a1b23f81,
+9ecc51a7,
+ad3f80e6,
+be3f8d3d,
5b80cc53,
-81979852,
+8196d452,
7a5180ee,
-e03f8254,
-8181b053,
+9d3f8254,
+8180ec53,
80d05283,
-fe805199,
-973f80cc,
+fe805198,
+d43f80cc,
547a5380,
d05283fe,
-805197ef,
+805197ac,
3f82c090,
08558257,
74833874,
@@ -415,36 +415,36 @@ d05283fe,
0855835c,
74833881,
5c865381,
-97a052a0,
+96dc52a0,
3dffbc05,
51fdab3f,
80085686,
-538197a8,
+538196e4,
52a03dc4,
0551fd9a,
3f800858,
84537682,
-2b8197c4,
+2b819780,
1153701c,
ac115358,
55fd833f,
80085a84,
-538197b4,
+538196f0,
15529c17,
51fcf33f,
80085984,
537b822b,
-8197c411,
+81978011,
53701cac,
11535855,
fcdc3f80,
085b8453,
-8197b415,
+8196f015,
529c1751,
fccc3f80,
0879557a,
54765357,
-8051a6c9,
+8051a686,
3f841633,
85173371,
882b0783,
@@ -464,7 +464,7 @@ d00c9e80,
0b82c1d4,
0c76547a,
53775281,
-51a5fa3f,
+51a5b73f,
84183385,
19337188,
2b07831a,
@@ -484,44 +484,44 @@ c2840c60,
82c2940c,
800b82c0,
840c80e4,
-5180c9c7,
+5180c984,
3f82c090,
08557481,
2e098106,
86388051,
-b6e23f82,
+b69f3f82,
c0940855,
74812e09,
81068638,
-7451b6d0,
+7451b68d,
3f805580,
e9397451,
-a3a53f80,
+a2e23f80,
085180d6,
-e73f8008,
+a43f8008,
53745281,
-82a4519e,
-c63f7451,
-a2f83f80,
+81e0519e,
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@@ -4837,7 +4820,7 @@ ffffff00,
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@@ -4858,12 +4841,12 @@ c0a82802,
00000000,
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@@ -4873,7 +4856,7 @@ c0a82802,
00000000,
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@@ -8191,4 +8174,21 @@ ffffffff,
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+00000000,
00000000; \ No newline at end of file
diff --git a/fpga/usrp3/top/x300/coregen/bootram.ngc b/fpga/usrp3/top/x300/coregen/bootram.ngc
deleted file mode 100644
index 0e4298a27..000000000
--- a/fpga/usrp3/top/x300/coregen/bootram.ngc
+++ /dev/null
@@ -1,3 +0,0 @@
-XILINX-XDB 0.1 STUB 0.1 ASCII
-XILINX-XDM V1.6e
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\ No newline at end of file
diff --git a/fpga/usrp3/top/x300/coregen/bus_clk_gen.gise b/fpga/usrp3/top/x300/coregen/bus_clk_gen.gise
index 70cd98ff0..28b71c6b7 100644
--- a/fpga/usrp3/top/x300/coregen/bus_clk_gen.gise
+++ b/fpga/usrp3/top/x300/coregen/bus_clk_gen.gise
@@ -15,7 +15,7 @@
<!-- -->
- <!-- Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. -->
+ <!-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. -->
<version xmlns="http://www.xilinx.com/XMLSchema">11.1</version>
diff --git a/fpga/usrp3/top/x300/coregen/bus_clk_gen.ucf b/fpga/usrp3/top/x300/coregen/bus_clk_gen.ucf
index 391b6f588..d59e8afb1 100755
--- a/fpga/usrp3/top/x300/coregen/bus_clk_gen.ucf
+++ b/fpga/usrp3/top/x300/coregen/bus_clk_gen.ucf
@@ -53,16 +53,6 @@
NET "CLK_IN1" TNM_NET = "CLK_IN1";
TIMESPEC "TS_CLK_IN1" = PERIOD "CLK_IN1" 8.000 ns HIGH 50% INPUT_JITTER 80.0ps;
-# Derived clock periods. These are commented out because they are
-# automatically propogated by the tools
-# However, if you'd like to use them for module level testing, you
-# can copy them into your module level timing checks
-#-----------------------------------------------------------------
-# NET "clk_int[1]" TNM_NET = "CLK_OUT1";
-# TIMESPEC "TS_CLK_OUT1" = PERIOD "CLK_OUT1" 175.000 MHz;
-
-# NET "clk_int[2]" TNM_NET = "CLK_OUT2";
-# TIMESPEC "TS_CLK_OUT2" = PERIOD "CLK_OUT2" 125.000 MHz;
# FALSE PATH constraints
PIN "RESET" TIG;
diff --git a/fpga/usrp3/top/x300/coregen/bus_clk_gen.v b/fpga/usrp3/top/x300/coregen/bus_clk_gen.v
index 8993f98d4..511f6fad7 100755
--- a/fpga/usrp3/top/x300/coregen/bus_clk_gen.v
+++ b/fpga/usrp3/top/x300/coregen/bus_clk_gen.v
@@ -55,8 +55,8 @@
// "Output Output Phase Duty Pk-to-Pk Phase"
// "Clock Freq (MHz) (degrees) Cycle (%) Jitter (ps) Error (ps)"
//----------------------------------------------------------------------------
-// CLK_OUT1___175.000______0.000______50.0______117.310____104.065
-// CLK_OUT2___125.000______0.000______50.0______125.031____104.065
+// CLK_OUT1___166.667______0.000______50.0______113.052_____96.948
+// CLK_OUT2___125.000______0.000______50.0______119.348_____96.948
//
//----------------------------------------------------------------------------
// "Input Clock Freq (MHz) Input Jitter (UI)"
@@ -109,12 +109,12 @@ module bus_clk_gen
#(.BANDWIDTH ("OPTIMIZED"),
.COMPENSATION ("ZHOLD"),
.DIVCLK_DIVIDE (1),
- .CLKFBOUT_MULT (7),
+ .CLKFBOUT_MULT (8),
.CLKFBOUT_PHASE (0.000),
- .CLKOUT0_DIVIDE (5),
+ .CLKOUT0_DIVIDE (6),
.CLKOUT0_PHASE (0.000),
.CLKOUT0_DUTY_CYCLE (0.500),
- .CLKOUT1_DIVIDE (7),
+ .CLKOUT1_DIVIDE (8),
.CLKOUT1_PHASE (0.000),
.CLKOUT1_DUTY_CYCLE (0.500),
.CLKIN1_PERIOD (8.000),
diff --git a/fpga/usrp3/top/x300/coregen/bus_clk_gen.veo b/fpga/usrp3/top/x300/coregen/bus_clk_gen.veo
index c2abb4741..b4b4b92d6 100755
--- a/fpga/usrp3/top/x300/coregen/bus_clk_gen.veo
+++ b/fpga/usrp3/top/x300/coregen/bus_clk_gen.veo
@@ -54,8 +54,8 @@
// "Output Output Phase Duty Pk-to-Pk Phase"
// "Clock Freq (MHz) (degrees) Cycle (%) Jitter (ps) Error (ps)"
//----------------------------------------------------------------------------
-// CLK_OUT1___175.000______0.000______50.0______117.310____104.065
-// CLK_OUT2___125.000______0.000______50.0______125.031____104.065
+// CLK_OUT1___166.667______0.000______50.0______113.052_____96.948
+// CLK_OUT2___125.000______0.000______50.0______119.348_____96.948
//
//----------------------------------------------------------------------------
// "Input Clock Freq (MHz) Input Jitter (UI)"
diff --git a/fpga/usrp3/top/x300/coregen/bus_clk_gen.xco b/fpga/usrp3/top/x300/coregen/bus_clk_gen.xco
index 5f4ee21e7..211602cb2 100644
--- a/fpga/usrp3/top/x300/coregen/bus_clk_gen.xco
+++ b/fpga/usrp3/top/x300/coregen/bus_clk_gen.xco
@@ -1,7 +1,7 @@
##############################################################
#
-# Xilinx Core Generator version 14.4
-# Date: Thu Sep 19 21:49:46 2013
+# Xilinx Core Generator version 14.6
+# Date: Mon Apr 28 17:58:14 2014
#
##############################################################
#
@@ -70,7 +70,7 @@ CSET clkin2_jitter_ps=100.0
CSET clkin2_ui_jitter=0.010
CSET clkout1_drives=BUFG
CSET clkout1_requested_duty_cycle=50.000
-CSET clkout1_requested_out_freq=175
+CSET clkout1_requested_out_freq=166.667
CSET clkout1_requested_phase=0.000
CSET clkout2_drives=BUFG
CSET clkout2_requested_duty_cycle=50.000
@@ -148,16 +148,16 @@ CSET jitter_options=UI
CSET jitter_sel=No_Jitter
CSET locked_port=LOCKED
CSET mmcm_bandwidth=OPTIMIZED
-CSET mmcm_clkfbout_mult_f=7
+CSET mmcm_clkfbout_mult_f=8
CSET mmcm_clkfbout_phase=0.000
CSET mmcm_clkfbout_use_fine_ps=false
CSET mmcm_clkin1_period=8.000
CSET mmcm_clkin2_period=10.0
-CSET mmcm_clkout0_divide_f=5
+CSET mmcm_clkout0_divide_f=6
CSET mmcm_clkout0_duty_cycle=0.500
CSET mmcm_clkout0_phase=0.000
CSET mmcm_clkout0_use_fine_ps=false
-CSET mmcm_clkout1_divide=7
+CSET mmcm_clkout1_divide=8
CSET mmcm_clkout1_duty_cycle=0.500
CSET mmcm_clkout1_phase=0.000
CSET mmcm_clkout1_use_fine_ps=false
@@ -266,4 +266,4 @@ CSET use_status=false
MISC pkg_timestamp=2012-05-10T12:44:55Z
# END Extra information
GENERATE
-# CRC: 1d4d384f
+# CRC: 215f8243
diff --git a/fpga/usrp3/top/x300/coregen/bus_clk_gen.xise b/fpga/usrp3/top/x300/coregen/bus_clk_gen.xise
index 3b95d58f1..4a3afc334 100644
--- a/fpga/usrp3/top/x300/coregen/bus_clk_gen.xise
+++ b/fpga/usrp3/top/x300/coregen/bus_clk_gen.xise
@@ -9,28 +9,21 @@
<!-- along with the project source files, is sufficient to open and -->
<!-- implement in ISE Project Navigator. -->
<!-- -->
- <!-- Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. -->
+ <!-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. -->
</header>
- <version xil_pn:ise_version="14.4" xil_pn:schema_version="2"/>
+ <version xil_pn:ise_version="14.6" xil_pn:schema_version="2"/>
<files>
- <file xil_pn:name="bus_clk_gen/example_design/bus_clk_gen_exdes.ucf" xil_pn:type="FILE_UCF">
- <association xil_pn:name="Implementation" xil_pn:seqID="1"/>
- </file>
- <file xil_pn:name="bus_clk_gen/example_design/bus_clk_gen_exdes.v" xil_pn:type="FILE_VERILOG">
- <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
+ <file xil_pn:name="bus_clk_gen.ucf" xil_pn:type="FILE_UCF">
<association xil_pn:name="Implementation" xil_pn:seqID="2"/>
- <association xil_pn:name="PostMapSimulation" xil_pn:seqID="2"/>
- <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="2"/>
- <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="2"/>
</file>
<file xil_pn:name="bus_clk_gen.v" xil_pn:type="FILE_VERILOG">
- <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="4"/>
- <association xil_pn:name="Implementation" xil_pn:seqID="4"/>
- <association xil_pn:name="PostMapSimulation" xil_pn:seqID="4"/>
- <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="4"/>
- <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="4"/>
+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="3"/>
+ <association xil_pn:name="PostMapSimulation" xil_pn:seqID="3"/>
+ <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="3"/>
+ <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="3"/>
</file>
</files>
@@ -46,7 +39,7 @@
<property xil_pn:name="Analysis Effort Level" xil_pn:value="Standard" xil_pn:valueState="default"/>
<property xil_pn:name="Asynchronous To Synchronous" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Auto Implementation Compile Order" xil_pn:value="true" xil_pn:valueState="default"/>
- <property xil_pn:name="Auto Implementation Top" xil_pn:value="true" xil_pn:valueState="default"/>
+ <property xil_pn:name="Auto Implementation Top" xil_pn:value="false" xil_pn:valueState="non-default"/>
<property xil_pn:name="Automatic BRAM Packing" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Automatically Insert glbl Module in the Netlist" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Automatically Run Generate Target PROM/ACE File" xil_pn:value="false" xil_pn:valueState="default"/>
@@ -149,9 +142,9 @@
<property xil_pn:name="Ignore User Timing Constraints Map" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Ignore User Timing Constraints Par" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Implementation Stop View" xil_pn:value="PreSynthesis" xil_pn:valueState="non-default"/>
- <property xil_pn:name="Implementation Top" xil_pn:value="Module|bus_clk_gen_exdes" xil_pn:valueState="non-default"/>
- <property xil_pn:name="Implementation Top File" xil_pn:value="bus_clk_gen/example_design/bus_clk_gen_exdes.v" xil_pn:valueState="non-default"/>
- <property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/bus_clk_gen_exdes" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="Implementation Top" xil_pn:value="Module|bus_clk_gen" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="Implementation Top File" xil_pn:value="bus_clk_gen.v" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/bus_clk_gen" xil_pn:valueState="non-default"/>
<property xil_pn:name="Include 'uselib Directive in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Include SIMPRIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Include UNISIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
@@ -205,7 +198,7 @@
<property xil_pn:name="Other XPWR Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other XST Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Output Extended Identifiers" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Output File Name" xil_pn:value="bus_clk_gen_exdes" xil_pn:valueState="default"/>
+ <property xil_pn:name="Output File Name" xil_pn:value="bus_clk_gen" xil_pn:valueState="default"/>
<property xil_pn:name="Overwrite Compiled Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Pack I/O Registers into IOBs" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Pack I/O Registers/Latches into IOBs" xil_pn:value="Off" xil_pn:valueState="default"/>
@@ -218,10 +211,10 @@
<property xil_pn:name="Placer Effort Level Map" xil_pn:value="High" xil_pn:valueState="default"/>
<property xil_pn:name="Placer Extra Effort Map" xil_pn:value="None" xil_pn:valueState="default"/>
<property xil_pn:name="Port to be used" xil_pn:value="Auto - default" xil_pn:valueState="default"/>
- <property xil_pn:name="Post Map Simulation Model Name" xil_pn:value="bus_clk_gen_exdes_map.v" xil_pn:valueState="default"/>
- <property xil_pn:name="Post Place &amp; Route Simulation Model Name" xil_pn:value="bus_clk_gen_exdes_timesim.v" xil_pn:valueState="default"/>
- <property xil_pn:name="Post Synthesis Simulation Model Name" xil_pn:value="bus_clk_gen_exdes_synthesis.v" xil_pn:valueState="default"/>
- <property xil_pn:name="Post Translate Simulation Model Name" xil_pn:value="bus_clk_gen_exdes_translate.v" xil_pn:valueState="default"/>
+ <property xil_pn:name="Post Map Simulation Model Name" xil_pn:value="bus_clk_gen_map.v" xil_pn:valueState="default"/>
+ <property xil_pn:name="Post Place &amp; Route Simulation Model Name" xil_pn:value="bus_clk_gen_timesim.v" xil_pn:valueState="default"/>
+ <property xil_pn:name="Post Synthesis Simulation Model Name" xil_pn:value="bus_clk_gen_synthesis.v" xil_pn:valueState="default"/>
+ <property xil_pn:name="Post Translate Simulation Model Name" xil_pn:value="bus_clk_gen_translate.v" xil_pn:valueState="default"/>
<property xil_pn:name="Power Down Device if Over Safe Temperature" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Power Reduction Map virtex6" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="Power Reduction Par" xil_pn:value="false" xil_pn:valueState="default"/>
@@ -345,13 +338,15 @@
<property xil_pn:name="PROP_PostSynthSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PostXlateSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PreSynthesis" xil_pn:value="PreSynthesis" xil_pn:valueState="default"/>
- <property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2013-09-19T14:50:10" xil_pn:valueState="non-default"/>
- <property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="484FFD4A79488674A3CE815213589584" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2014-04-28T10:58:39" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="864AFA86C959B32B2CD711C532A10895" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
</properties>
- <bindings/>
+ <bindings>
+ <binding xil_pn:location="/bus_clk_gen" xil_pn:name="bus_clk_gen.ucf"/>
+ </bindings>
<libraries/>
diff --git a/fpga/usrp3/top/x300/coregen/bus_clk_gen/clk_wiz_v3_6_readme.txt b/fpga/usrp3/top/x300/coregen/bus_clk_gen/clk_wiz_v3_6_readme.txt
index 19c5b73c6..91dcdd01f 100644
--- a/fpga/usrp3/top/x300/coregen/bus_clk_gen/clk_wiz_v3_6_readme.txt
+++ b/fpga/usrp3/top/x300/coregen/bus_clk_gen/clk_wiz_v3_6_readme.txt
@@ -1,6 +1,6 @@
CHANGE LOG for LogiCORE Clocking Wizard V3.6
- Release Date: July 25, 2012
+ Release Date: June 19, 2013
--------------------------------------------------------------------------------
Table of Contents
@@ -74,6 +74,8 @@ solution. For the latest core updates, see the product page at:
4.1 ISE
+ Resolved issue with example design becoming core top in planAhead
+
Resolved issue with Virtex6 MMCM instantiation for VHDL project
Please refer to AR 50719 - http://www.xilinx.com/support/answers/50719.htm
@@ -113,6 +115,7 @@ designs that do not follow specified guidelines.
Date By Version Description
================================================================================
+06/19/2013 Xilinx, Inc. 3.6(Rev3) ISE 14.6 support
10/16/2012 Xilinx, Inc. 3.6(Rev2) ISE 14.3 support
07/25/2012 Xilinx, Inc. 3.6 ISE 14.2 support
04/24/2012 Xilinx, Inc. 3.5 ISE 14.1 support
@@ -133,7 +136,7 @@ Date By Version Description
8. LEGAL DISCLAIMER
-(c) Copyright 2008 - 2012 Xilinx, Inc. All rights reserved.
+(c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
This file contains confidential and proprietary information
of Xilinx, Inc. and is protected under U.S. and
diff --git a/fpga/usrp3/top/x300/coregen/bus_clk_gen/doc/clk_wiz_v3_6_readme.txt b/fpga/usrp3/top/x300/coregen/bus_clk_gen/doc/clk_wiz_v3_6_readme.txt
index 19c5b73c6..91dcdd01f 100644
--- a/fpga/usrp3/top/x300/coregen/bus_clk_gen/doc/clk_wiz_v3_6_readme.txt
+++ b/fpga/usrp3/top/x300/coregen/bus_clk_gen/doc/clk_wiz_v3_6_readme.txt
@@ -1,6 +1,6 @@
CHANGE LOG for LogiCORE Clocking Wizard V3.6
- Release Date: July 25, 2012
+ Release Date: June 19, 2013
--------------------------------------------------------------------------------
Table of Contents
@@ -74,6 +74,8 @@ solution. For the latest core updates, see the product page at:
4.1 ISE
+ Resolved issue with example design becoming core top in planAhead
+
Resolved issue with Virtex6 MMCM instantiation for VHDL project
Please refer to AR 50719 - http://www.xilinx.com/support/answers/50719.htm
@@ -113,6 +115,7 @@ designs that do not follow specified guidelines.
Date By Version Description
================================================================================
+06/19/2013 Xilinx, Inc. 3.6(Rev3) ISE 14.6 support
10/16/2012 Xilinx, Inc. 3.6(Rev2) ISE 14.3 support
07/25/2012 Xilinx, Inc. 3.6 ISE 14.2 support
04/24/2012 Xilinx, Inc. 3.5 ISE 14.1 support
@@ -133,7 +136,7 @@ Date By Version Description
8. LEGAL DISCLAIMER
-(c) Copyright 2008 - 2012 Xilinx, Inc. All rights reserved.
+(c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
This file contains confidential and proprietary information
of Xilinx, Inc. and is protected under U.S. and
diff --git a/fpga/usrp3/top/x300/coregen/bus_clk_gen/doc/clk_wiz_v3_6_vinfo.html b/fpga/usrp3/top/x300/coregen/bus_clk_gen/doc/clk_wiz_v3_6_vinfo.html
index 7176ddb81..d6deba06c 100644
--- a/fpga/usrp3/top/x300/coregen/bus_clk_gen/doc/clk_wiz_v3_6_vinfo.html
+++ b/fpga/usrp3/top/x300/coregen/bus_clk_gen/doc/clk_wiz_v3_6_vinfo.html
@@ -7,7 +7,7 @@
<PRE><FONT face="Arial, Helvetica, sans-serif" size="-1">
CHANGE LOG for LogiCORE Clocking Wizard V3.6
- Release Date: July 25, 2012
+ Release Date: June 19, 2013
--------------------------------------------------------------------------------
Table of Contents
@@ -81,8 +81,10 @@ solution. For the latest core updates, see the product page at:
4.1 ISE
+ Resolved issue with example design becoming core top in planAhead
+
Resolved issue with Virtex6 MMCM instantiation for VHDL project
- Please refer to AR 50719 - http://www.xilinx.com/support/answers/50719.htm
+ Please refer to AR 50719 - <A HREF="http://www.xilinx.com/support/answers/50719.htm">www.xilinx.com/support/answers/50719.htm</A>
................................................................................
@@ -120,6 +122,7 @@ designs that do not follow specified guidelines.
Date By Version Description
================================================================================
+06/19/2013 Xilinx, Inc. 3.6(Rev3) ISE 14.6 support
10/16/2012 Xilinx, Inc. 3.6(Rev2) ISE 14.3 support
07/25/2012 Xilinx, Inc. 3.6 ISE 14.2 support
04/24/2012 Xilinx, Inc. 3.5 ISE 14.1 support
@@ -140,7 +143,7 @@ Date By Version Description
8. LEGAL DISCLAIMER
-(c) Copyright 2008 - 2012 Xilinx, Inc. All rights reserved.
+(c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
This file contains confidential and proprietary information
of Xilinx, Inc. and is protected under U.S. and
diff --git a/fpga/usrp3/top/x300/coregen/bus_clk_gen/example_design/bus_clk_gen_exdes.ucf b/fpga/usrp3/top/x300/coregen/bus_clk_gen/example_design/bus_clk_gen_exdes.ucf
index 433294e63..1307e8b66 100755
--- a/fpga/usrp3/top/x300/coregen/bus_clk_gen/example_design/bus_clk_gen_exdes.ucf
+++ b/fpga/usrp3/top/x300/coregen/bus_clk_gen/example_design/bus_clk_gen_exdes.ucf
@@ -53,16 +53,6 @@
NET "CLK_IN1" TNM_NET = "CLK_IN1";
TIMESPEC "TS_CLK_IN1" = PERIOD "CLK_IN1" 8.000 ns HIGH 50% INPUT_JITTER 80.0ps;
-# Derived clock periods. These are commented out because they are
-# automatically propogated by the tools
-# However, if you'd like to use them for module level testing, you
-# can copy them into your module level timing checks
-#-----------------------------------------------------------------
-# NET "clk_int[1]" TNM_NET = "CLK_OUT1";
-# TIMESPEC "TS_CLK_OUT1" = PERIOD "CLK_OUT1" 175.000 MHz;
-
-# NET "clk_int[2]" TNM_NET = "CLK_OUT2";
-# TIMESPEC "TS_CLK_OUT2" = PERIOD "CLK_OUT2" 125.000 MHz;
# FALSE PATH constraints
PIN "COUNTER_RESET" TIG;
diff --git a/fpga/usrp3/top/x300/coregen/bus_clk_gen/simulation/bus_clk_gen_tb.v b/fpga/usrp3/top/x300/coregen/bus_clk_gen/simulation/bus_clk_gen_tb.v
index 4ab770c3e..d1d1e41ac 100755
--- a/fpga/usrp3/top/x300/coregen/bus_clk_gen/simulation/bus_clk_gen_tb.v
+++ b/fpga/usrp3/top/x300/coregen/bus_clk_gen/simulation/bus_clk_gen_tb.v
@@ -88,11 +88,11 @@ wire [2:1] CLK_OUT;
//Freq Check using the M & D values setting and actual Frequency generated
real period1;
real ref_period1;
-localparam ref_period1_clkin1 = (8.000*1*5*1000/7);
+localparam ref_period1_clkin1 = (8.000*1*6*1000/8);
time prev_rise1;
real period2;
real ref_period2;
-localparam ref_period2_clkin1 = (8.000*1*7*1000/7);
+localparam ref_period2_clkin1 = (8.000*1*8*1000/8);
time prev_rise2;
diff --git a/fpga/usrp3/top/x300/coregen/bus_clk_gen/simulation/timing/bus_clk_gen_tb.v b/fpga/usrp3/top/x300/coregen/bus_clk_gen/simulation/timing/bus_clk_gen_tb.v
index 135061e05..77b12f966 100755
--- a/fpga/usrp3/top/x300/coregen/bus_clk_gen/simulation/timing/bus_clk_gen_tb.v
+++ b/fpga/usrp3/top/x300/coregen/bus_clk_gen/simulation/timing/bus_clk_gen_tb.v
@@ -88,11 +88,11 @@ wire [2:1] CLK_OUT;
//Freq Check using the M & D values setting and actual Frequency generated
real period1;
real ref_period1;
-localparam ref_period1_clkin1 = (8.000*1*5*1000/7);
+localparam ref_period1_clkin1 = (8.000*1*6*1000/8);
time prev_rise1;
real period2;
real ref_period2;
-localparam ref_period2_clkin1 = (8.000*1*7*1000/7);
+localparam ref_period2_clkin1 = (8.000*1*8*1000/8);
time prev_rise2;
reg [13:0] timeout_counter = 14'b00000000000000;
diff --git a/fpga/usrp3/top/x300/coregen/bus_clk_gen_xmdf.tcl b/fpga/usrp3/top/x300/coregen/bus_clk_gen_xmdf.tcl
index 0423faf43..9e59b4811 100755
--- a/fpga/usrp3/top/x300/coregen/bus_clk_gen_xmdf.tcl
+++ b/fpga/usrp3/top/x300/coregen/bus_clk_gen_xmdf.tcl
@@ -40,10 +40,6 @@ utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path bus_clk_gen/
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
incr fcount
-utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path bus_clk_gen/example_design/bus_clk_gen_exdes.ucf
-utilities_xmdf::xmdfSetData $instance FileSet $fcount type ucf
-incr fcount
-
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path bus_clk_gen/doc/clk_wiz_ds709.pdf
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
incr fcount
@@ -52,10 +48,6 @@ utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path bus_clk_gen/
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
incr fcount
-utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path bus_clk_gen/example_design/bus_clk_gen_exdes.v
-utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog
-incr fcount
-
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path bus_clk_gen/implement/implement.bat
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
incr fcount
@@ -120,6 +112,10 @@ utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path bus_clk_gen.
utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView
incr fcount
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path bus_clk_gen.ucf
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type ucf
+incr fcount
+
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path bus_clk_gen.v
utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog
incr fcount
diff --git a/fpga/usrp3/top/x300/x300.v b/fpga/usrp3/top/x300/x300.v
index 10409c607..e9191a481 100644
--- a/fpga/usrp3/top/x300/x300.v
+++ b/fpga/usrp3/top/x300/x300.v
@@ -285,7 +285,7 @@ module x300
bus_clk_gen bus_clk_gen (
.CLK_IN1(fpga_clk125), //Input Clock: 125MHz Clock from STC3
- .CLK_OUT1(bus_clk), //Output Clock 1: 175MHz
+ .CLK_OUT1(bus_clk), //Output Clock 1: 166.666667MHz
.CLK_OUT2(ioport2_clk), //Output Clock 2: 125MHz
.RESET(1'b0),
.LOCKED(bus_clk_locked));
@@ -547,187 +547,203 @@ module x300
//
//////////////////////////////////////////////////////////////////////
- localparam IOP2_MSG_WIDTH = 64;
- localparam DMA_STREAM_WIDTH = `LVFPGA_IFACE_DMA_CHAN_WIDTH;
- localparam DMA_COUNT_WIDTH = `LVFPGA_IFACE_DMA_SIZE_WIDTH;
- localparam NUM_TX_STREAMS = `LVFPGA_IFACE_NUM_TX_DMA_CNT;
- localparam NUM_RX_STREAMS = `LVFPGA_IFACE_NUM_RX_DMA_CNT;
- localparam TX_STREAM_START_IDX = `LVFPGA_IFACE_TX_DMA_INDEX;
- localparam RX_STREAM_START_IDX = `LVFPGA_IFACE_RX_DMA_INDEX;
-
- wire [DMA_STREAM_WIDTH-1:0] dmatx_tdata, dmarx_tdata;
- wire dmatx_tvalid, dmarx_tvalid;
- wire dmatx_tlast, dmarx_tlast;
- wire dmatx_tready, dmarx_tready;
-
- wire [IOP2_MSG_WIDTH-1:0] o_iop2_msg_tdata, i_iop2_msg_tdata;
- wire o_iop2_msg_tvalid, o_iop2_msg_tlast, o_iop2_msg_tready;
- wire i_iop2_msg_tvalid, i_iop2_msg_tlast, i_iop2_msg_tready;
-
- wire pcie_usr_reg_wr, pcie_usr_reg_rd, pcie_usr_reg_rc, pcie_usr_reg_rdy;
- wire [1:0] pcie_usr_reg_len;
- wire [19:0] pcie_usr_reg_addr;
- wire [31:0] pcie_usr_reg_data_in, pcie_usr_reg_data_out;
-
- wire chinch_reg_wr, chinch_reg_rd, chinch_reg_rc, chinch_reg_rdy;
- wire [1:0] chinch_reg_len;
- wire [19:0] chinch_reg_addr;
- wire [31:0] chinch_reg_data_out;
- wire [63:0] chinch_reg_data_in;
-
- wire [(NUM_TX_STREAMS*DMA_STREAM_WIDTH)-1:0] dmatx_tdata_iop2;
- wire [NUM_TX_STREAMS-1:0] dmatx_tvalid_iop2, dmatx_tready_iop2;
-
- wire [(NUM_RX_STREAMS*DMA_STREAM_WIDTH)-1:0] dmarx_tdata_iop2;
- wire [NUM_RX_STREAMS-1:0] dmarx_tvalid_iop2, dmarx_tready_iop2;
-
- //PCIe Express "Physical" DMA and Register logic
- LvFpga_Chinch_Interface lvfpga_chinch_inst
- (
- .aIoResetIn_n(aIoResetIn_n),
- .bBusReset(), //Output
-
- // Clocks
- .BusClk(ioport2_clk),
- .Rio40Clk(rio40_clk),
- .IDelayRefClk(ioport2_idelay_ref_clk),
- .aRioClkPllLocked(rio40_clk_locked),
- .aRioClkPllReset(rio40_clk_reset),
-
- // The IO_Port2 asynchronous handshaking pins
- .aIoReadyOut(aIoReadyOut),
- .aIoReadyIn(aIoReadyIn),
- .aIoPort2Restart(aIoPort2Restart),
-
- // The IO_Port2 high speed receiver pins
- .IoRxClock(IoRxClock),
- .IoRxClock_n(IoRxClock_n),
- .irIoRxData(irIoRxData),
- .irIoRxData_n(irIoRxData_n),
- .irIoRxHeader(irIoRxHeader),
- .irIoRxHeader_n(irIoRxHeader_n),
-
- // The IO_Port2 high speed transmitter interface pins
- .IoTxClock(IoTxClock),
- .IoTxClock_n(IoTxClock_n),
- .itIoTxData(itIoTxData),
- .itIoTxData_n(itIoTxData_n),
- .itIoTxHeader(itIoTxHeader),
- .itIoTxHeader_n(itIoTxHeader_n),
-
- // DMA TX Fifos
- .bDmaTxData(dmatx_tdata_iop2),
- .bDmaTxValid(dmatx_tvalid_iop2),
- .bDmaTxReady(dmatx_tready_iop2),
- .bDmaTxEnabled(),
- .bDmaTxFifoFullCnt(),
-
- // DMA RX Fifos
- .bDmaRxData(dmarx_tdata_iop2),
- .bDmaRxValid(dmarx_tvalid_iop2),
- .bDmaRxReady(dmarx_tready_iop2),
- .bDmaRxEnabled(),
- .bDmaRxFifoFreeCnt(),
-
- // User Register Port In
- .bUserRegPortInWt(pcie_usr_reg_wr),
- .bUserRegPortInRd(pcie_usr_reg_rd),
- .bUserRegPortInAddr(pcie_usr_reg_addr),
- .bUserRegPortInData(pcie_usr_reg_data_in),
- .bUserRegPortInSize(pcie_usr_reg_len),
-
- // User Register Port Out
- .bUserRegPortOutData(pcie_usr_reg_data_out),
- .bUserRegPortOutDataValid(pcie_usr_reg_rc),
- .bUserRegPortOutReady(pcie_usr_reg_rdy),
-
- // Chinch Register Port Out
- .bChinchRegPortOutWt(chinch_reg_wr),
- .bChinchRegPortOutRd(chinch_reg_rd),
- .bChinchRegPortOutAddr({12'h0, chinch_reg_addr}),
- .bChinchRegPortOutData({32'h0, chinch_reg_data_out}),
- .bChinchRegPortOutSize(chinch_reg_len),
-
- // User Register Port In
- .bChinchRegPortInData(chinch_reg_data_in),
- .bChinchRegPortInDataValid(chinch_reg_rc),
- .bChinchRegPortInReady(chinch_reg_rdy),
-
- // Level interrupt
- .aIrq(aIrq)
- );
+ localparam IOP2_MSG_WIDTH = 64;
+ localparam DMA_STREAM_WIDTH = `LVFPGA_IFACE_DMA_CHAN_WIDTH;
+ localparam DMA_COUNT_WIDTH = `LVFPGA_IFACE_DMA_SIZE_WIDTH;
+ localparam NUM_TX_STREAMS = `LVFPGA_IFACE_NUM_TX_DMA_CNT;
+ localparam NUM_RX_STREAMS = `LVFPGA_IFACE_NUM_RX_DMA_CNT;
+ localparam TX_STREAM_START_IDX = `LVFPGA_IFACE_TX_DMA_INDEX;
+ localparam RX_STREAM_START_IDX = `LVFPGA_IFACE_RX_DMA_INDEX;
+
+ wire [DMA_STREAM_WIDTH-1:0] dmatx_tdata, dmarx_tdata, pcii_tdata, pcio_tdata;
+ wire dmatx_tvalid, dmarx_tvalid, pcii_tvalid, pcio_tvalid;
+ wire dmatx_tlast, dmarx_tlast, pcii_tlast, pcio_tlast;
+ wire dmatx_tready, dmarx_tready, pcii_tready, pcio_tready;
+
+ wire [IOP2_MSG_WIDTH-1:0] o_iop2_msg_tdata, i_iop2_msg_tdata;
+ wire o_iop2_msg_tvalid, o_iop2_msg_tlast, o_iop2_msg_tready;
+ wire i_iop2_msg_tvalid, i_iop2_msg_tlast, i_iop2_msg_tready;
+
+ wire pcie_usr_reg_wr, pcie_usr_reg_rd, pcie_usr_reg_rc, pcie_usr_reg_rdy;
+ wire [1:0] pcie_usr_reg_len;
+ wire [19:0] pcie_usr_reg_addr;
+ wire [31:0] pcie_usr_reg_data_in, pcie_usr_reg_data_out;
+
+ wire chinch_reg_wr, chinch_reg_rd, chinch_reg_rc, chinch_reg_rdy;
+ wire [1:0] chinch_reg_len;
+ wire [19:0] chinch_reg_addr;
+ wire [31:0] chinch_reg_data_out;
+ wire [63:0] chinch_reg_data_in;
+
+ wire [(NUM_TX_STREAMS*DMA_STREAM_WIDTH)-1:0] dmatx_tdata_iop2;
+ wire [NUM_TX_STREAMS-1:0] dmatx_tvalid_iop2, dmatx_tready_iop2;
+
+ wire [(NUM_RX_STREAMS*DMA_STREAM_WIDTH)-1:0] dmarx_tdata_iop2;
+ wire [NUM_RX_STREAMS-1:0] dmarx_tvalid_iop2, dmarx_tready_iop2;
+
+ //PCIe Express "Physical" DMA and Register logic
+ LvFpga_Chinch_Interface lvfpga_chinch_inst
+ (
+ .aIoResetIn_n(aIoResetIn_n),
+ .bBusReset(), //Output
+
+ // Clocks
+ .BusClk(ioport2_clk),
+ .Rio40Clk(rio40_clk),
+ .IDelayRefClk(ioport2_idelay_ref_clk),
+ .aRioClkPllLocked(rio40_clk_locked),
+ .aRioClkPllReset(rio40_clk_reset),
+
+ // The IO_Port2 asynchronous handshaking pins
+ .aIoReadyOut(aIoReadyOut),
+ .aIoReadyIn(aIoReadyIn),
+ .aIoPort2Restart(aIoPort2Restart),
+
+ // The IO_Port2 high speed receiver pins
+ .IoRxClock(IoRxClock),
+ .IoRxClock_n(IoRxClock_n),
+ .irIoRxData(irIoRxData),
+ .irIoRxData_n(irIoRxData_n),
+ .irIoRxHeader(irIoRxHeader),
+ .irIoRxHeader_n(irIoRxHeader_n),
+
+ // The IO_Port2 high speed transmitter interface pins
+ .IoTxClock(IoTxClock),
+ .IoTxClock_n(IoTxClock_n),
+ .itIoTxData(itIoTxData),
+ .itIoTxData_n(itIoTxData_n),
+ .itIoTxHeader(itIoTxHeader),
+ .itIoTxHeader_n(itIoTxHeader_n),
+
+ // DMA TX Fifos
+ .bDmaTxData(dmatx_tdata_iop2),
+ .bDmaTxValid(dmatx_tvalid_iop2),
+ .bDmaTxReady(dmatx_tready_iop2),
+ .bDmaTxEnabled(),
+ .bDmaTxFifoFullCnt(),
+
+ // DMA RX Fifos
+ .bDmaRxData(dmarx_tdata_iop2),
+ .bDmaRxValid(dmarx_tvalid_iop2),
+ .bDmaRxReady(dmarx_tready_iop2),
+ .bDmaRxEnabled(),
+ .bDmaRxFifoFreeCnt(),
+
+ // User Register Port In
+ .bUserRegPortInWt(pcie_usr_reg_wr),
+ .bUserRegPortInRd(pcie_usr_reg_rd),
+ .bUserRegPortInAddr(pcie_usr_reg_addr),
+ .bUserRegPortInData(pcie_usr_reg_data_in),
+ .bUserRegPortInSize(pcie_usr_reg_len),
+
+ // User Register Port Out
+ .bUserRegPortOutData(pcie_usr_reg_data_out),
+ .bUserRegPortOutDataValid(pcie_usr_reg_rc),
+ .bUserRegPortOutReady(pcie_usr_reg_rdy),
+
+ // Chinch Register Port Out
+ .bChinchRegPortOutWt(chinch_reg_wr),
+ .bChinchRegPortOutRd(chinch_reg_rd),
+ .bChinchRegPortOutAddr({12'h0, chinch_reg_addr}),
+ .bChinchRegPortOutData({32'h0, chinch_reg_data_out}),
+ .bChinchRegPortOutSize(chinch_reg_len),
+
+ // User Register Port In
+ .bChinchRegPortInData(chinch_reg_data_in),
+ .bChinchRegPortInDataValid(chinch_reg_rc),
+ .bChinchRegPortInReady(chinch_reg_rdy),
+
+ // Level interrupt
+ .aIrq(aIrq)
+ );
- //PCIe Express adapter logic to link to the AXI crossbar and the WB bus
- x300_pcie_int #(
- .DMA_STREAM_WIDTH(DMA_STREAM_WIDTH),
- .NUM_TX_STREAMS(NUM_TX_STREAMS),
- .NUM_RX_STREAMS(NUM_RX_STREAMS),
- .REGPORT_ADDR_WIDTH(20),
- .REGPORT_DATA_WIDTH(32),
- .IOP2_MSG_WIDTH(IOP2_MSG_WIDTH)
- ) x300_pcie_int (
- .ioport2_clk(ioport2_clk),
- .bus_clk(bus_clk),
- .bus_rst(bus_rst),
-
- //DMA TX FIFOs (IoPort2 Clock Domain)
- .dmatx_tdata_iop2(dmatx_tdata_iop2),
- .dmatx_tvalid_iop2(dmatx_tvalid_iop2),
- .dmatx_tready_iop2(dmatx_tready_iop2),
-
- //DMA TX FIFOs (IoPort2 Clock Domain)
- .dmarx_tdata_iop2(dmarx_tdata_iop2),
- .dmarx_tvalid_iop2(dmarx_tvalid_iop2),
- .dmarx_tready_iop2(dmarx_tready_iop2),
-
- //PCIe User Regport
- .pcie_usr_reg_wr(pcie_usr_reg_wr),
- .pcie_usr_reg_rd(pcie_usr_reg_rd),
- .pcie_usr_reg_addr(pcie_usr_reg_addr),
- .pcie_usr_reg_data_in(pcie_usr_reg_data_in),
- .pcie_usr_reg_len(pcie_usr_reg_len),
- .pcie_usr_reg_data_out(pcie_usr_reg_data_out),
- .pcie_usr_reg_rc(pcie_usr_reg_rc),
- .pcie_usr_reg_rdy(pcie_usr_reg_rdy),
-
- //Chinch Regport
- .chinch_reg_wr(chinch_reg_wr),
- .chinch_reg_rd(chinch_reg_rd),
- .chinch_reg_addr(chinch_reg_addr),
- .chinch_reg_data_out(chinch_reg_data_out),
- .chinch_reg_len(chinch_reg_len),
- .chinch_reg_data_in(chinch_reg_data_in[31:0]),
- .chinch_reg_rc(chinch_reg_rc),
- .chinch_reg_rdy(chinch_reg_rdy),
-
- //DMA TX FIFO (Bus Clock Domain)
- .dmatx_tdata(dmatx_tdata),
- .dmatx_tlast(dmatx_tlast),
- .dmatx_tvalid(dmatx_tvalid),
- .dmatx_tready(dmatx_tready),
-
- //DMA RX FIFO (Bus Clock Domain)
- .dmarx_tdata(dmarx_tdata),
- .dmarx_tlast(dmarx_tlast),
- .dmarx_tvalid(dmarx_tvalid),
- .dmarx_tready(dmarx_tready),
-
- //Message FIFO Out (Bus Clock Domain)
- .rego_tdata(o_iop2_msg_tdata),
- .rego_tvalid(o_iop2_msg_tvalid),
- .rego_tlast(o_iop2_msg_tlast),
- .rego_tready(o_iop2_msg_tready),
-
- //Message FIFO In (Bus Clock Domain)
- .regi_tdata(i_iop2_msg_tdata),
- .regi_tvalid(i_iop2_msg_tvalid),
- .regi_tlast(i_iop2_msg_tlast),
- .regi_tready(i_iop2_msg_tready),
-
- //Misc
- .misc_status({31'h0, aStc3Gpio7}),
- .debug()
- );
+ //PCIe Express adapter logic to link to the AXI crossbar and the WB bus
+ x300_pcie_int #(
+ .DMA_STREAM_WIDTH(DMA_STREAM_WIDTH),
+ .NUM_TX_STREAMS(NUM_TX_STREAMS),
+ .NUM_RX_STREAMS(NUM_RX_STREAMS),
+ .REGPORT_ADDR_WIDTH(20),
+ .REGPORT_DATA_WIDTH(32),
+ .IOP2_MSG_WIDTH(IOP2_MSG_WIDTH)
+ ) x300_pcie_int (
+ .ioport2_clk(ioport2_clk),
+ .bus_clk(bus_clk),
+ .bus_rst(bus_rst),
+
+ //DMA TX FIFOs (IoPort2 Clock Domain)
+ .dmatx_tdata_iop2(dmatx_tdata_iop2),
+ .dmatx_tvalid_iop2(dmatx_tvalid_iop2),
+ .dmatx_tready_iop2(dmatx_tready_iop2),
+
+ //DMA TX FIFOs (IoPort2 Clock Domain)
+ .dmarx_tdata_iop2(dmarx_tdata_iop2),
+ .dmarx_tvalid_iop2(dmarx_tvalid_iop2),
+ .dmarx_tready_iop2(dmarx_tready_iop2),
+
+ //PCIe User Regport
+ .pcie_usr_reg_wr(pcie_usr_reg_wr),
+ .pcie_usr_reg_rd(pcie_usr_reg_rd),
+ .pcie_usr_reg_addr(pcie_usr_reg_addr),
+ .pcie_usr_reg_data_in(pcie_usr_reg_data_in),
+ .pcie_usr_reg_len(pcie_usr_reg_len),
+ .pcie_usr_reg_data_out(pcie_usr_reg_data_out),
+ .pcie_usr_reg_rc(pcie_usr_reg_rc),
+ .pcie_usr_reg_rdy(pcie_usr_reg_rdy),
+
+ //Chinch Regport
+ .chinch_reg_wr(chinch_reg_wr),
+ .chinch_reg_rd(chinch_reg_rd),
+ .chinch_reg_addr(chinch_reg_addr),
+ .chinch_reg_data_out(chinch_reg_data_out),
+ .chinch_reg_len(chinch_reg_len),
+ .chinch_reg_data_in(chinch_reg_data_in[31:0]),
+ .chinch_reg_rc(chinch_reg_rc),
+ .chinch_reg_rdy(chinch_reg_rdy),
+
+ //DMA TX FIFO (Bus Clock Domain)
+ .dmatx_tdata(dmatx_tdata),
+ .dmatx_tlast(dmatx_tlast),
+ .dmatx_tvalid(dmatx_tvalid),
+ .dmatx_tready(dmatx_tready),
+
+ //DMA RX FIFO (Bus Clock Domain)
+ .dmarx_tdata(dmarx_tdata),
+ .dmarx_tlast(dmarx_tlast),
+ .dmarx_tvalid(dmarx_tvalid),
+ .dmarx_tready(dmarx_tready),
+
+ //Message FIFO Out (Bus Clock Domain)
+ .rego_tdata(o_iop2_msg_tdata),
+ .rego_tvalid(o_iop2_msg_tvalid),
+ .rego_tlast(o_iop2_msg_tlast),
+ .rego_tready(o_iop2_msg_tready),
+
+ //Message FIFO In (Bus Clock Domain)
+ .regi_tdata(i_iop2_msg_tdata),
+ .regi_tvalid(i_iop2_msg_tvalid),
+ .regi_tlast(i_iop2_msg_tlast),
+ .regi_tready(i_iop2_msg_tready),
+
+ //Misc
+ .misc_status({15'h0, aStc3Gpio7}),
+ .debug()
+ );
+
+ // The PCIe logic will tend to stay close to the physical IoPort2 pins
+ // so add an additional stage of pipelining to give the tool more routing
+ // slack. This is significantly help timing closure.
+
+ axi_fifo_short #(.WIDTH(DMA_STREAM_WIDTH+1)) pcii_pipeline_srl (
+ .clk(bus_clk), .reset(bus_rst), .clear(1'b0),
+ .i_tdata({dmatx_tlast, dmatx_tdata}), .i_tvalid(dmatx_tvalid), .i_tready(dmatx_tready),
+ .o_tdata({pcii_tlast, pcii_tdata}), .o_tvalid(pcii_tvalid), .o_tready(pcii_tready),
+ .space(), .occupied());
+
+ axi_fifo_short #(.WIDTH(DMA_STREAM_WIDTH+1)) pcio_pipeline_srl (
+ .clk(bus_clk), .reset(bus_rst), .clear(1'b0),
+ .i_tdata({pcio_tlast, pcio_tdata}), .i_tvalid(pcio_tvalid), .i_tready(pcio_tready),
+ .o_tdata({dmarx_tlast, dmarx_tdata}), .o_tvalid(dmarx_tvalid), .o_tready(dmarx_tready),
+ .space(), .occupied());
//////////////////////////////////////////////////////////////////////
//
@@ -1936,14 +1952,14 @@ module x300
.i_iop2_msg_tlast (i_iop2_msg_tlast),
.i_iop2_msg_tready (i_iop2_msg_tready),
// PCIe DMA Data
- .pcio_tdata (dmarx_tdata),
- .pcio_tlast (dmarx_tlast),
- .pcio_tvalid (dmarx_tvalid),
- .pcio_tready (dmarx_tready),
- .pcii_tdata (dmatx_tdata),
- .pcii_tlast (dmatx_tlast),
- .pcii_tvalid (dmatx_tvalid),
- .pcii_tready (dmatx_tready)
+ .pcio_tdata (pcio_tdata),
+ .pcio_tlast (pcio_tlast),
+ .pcio_tvalid (pcio_tvalid),
+ .pcio_tready (pcio_tready),
+ .pcii_tdata (pcii_tdata),
+ .pcii_tlast (pcii_tlast),
+ .pcii_tvalid (pcii_tvalid),
+ .pcii_tready (pcii_tready)
);
diff --git a/fpga/usrp3/top/x300/x300_pcie_int.v b/fpga/usrp3/top/x300/x300_pcie_int.v
index 441ab9813..7b067f387 100644
--- a/fpga/usrp3/top/x300/x300_pcie_int.v
+++ b/fpga/usrp3/top/x300/x300_pcie_int.v
@@ -86,7 +86,7 @@ module x300_pcie_int #(
//---------------------------------------------------------
// Misc
//---------------------------------------------------------
- input [31:0] misc_status,
+ input [15:0] misc_status,
output [127:0] debug
);
@@ -143,11 +143,13 @@ module x300_pcie_int #(
//
//*******************************************************************************
- wire [NUM_TX_STREAMS-1:0] dmatx_clear, dmatx_samp_stb, dmatx_pkt_stb, dmatx_error;
+ wire [NUM_TX_STREAMS-1:0] dmatx_clear, dmatx_enabled;
+ wire [NUM_TX_STREAMS-1:0] dmatx_samp_stb, dmatx_pkt_stb, dmatx_busy, dmatx_error;
wire [(NUM_TX_STREAMS*DMA_FRAME_SIZE_WIDTH)-1:0] dmatx_frame_size;
wire [(NUM_TX_STREAMS*3)-1:0] dmatx_swap;
- wire [NUM_RX_STREAMS-1:0] dmarx_clear, dmarx_samp_stb, dmarx_pkt_stb, dmarx_error;
+ wire [NUM_RX_STREAMS-1:0] dmarx_clear, dmarx_enabled;
+ wire [NUM_RX_STREAMS-1:0] dmarx_samp_stb, dmarx_pkt_stb, dmarx_busy, dmarx_error;
wire [(NUM_RX_STREAMS*DMA_FRAME_SIZE_WIDTH)-1:0] dmarx_frame_size;
wire [(NUM_TX_STREAMS*3)-1:0] dmarx_swap;
wire [DMA_STREAM_WIDTH-1:0] dmarx_header;
@@ -188,12 +190,18 @@ module x300_pcie_int #(
.e3_rego_tdata(rego_tdata), .e3_rego_tvalid(rego_tvalid), .e3_rego_tready(rego_tready)
);
assign regi_tlast = regi_tvalid;
+
+ wire [15:0] fpga_status;
+ assign fpga_status[7:0] = {|(dmatx_error), 1'b0, dmatx_enabled};
+ assign fpga_status[15:8] = {|(dmarx_error), 1'b0, dmarx_enabled};
- pcie_basic_regs basic_regs (
+ pcie_basic_regs #(
+ .SIGNATURE(32'h58333030 /*ASCII:"X300"*/), .CLK_FREQ(32'd166666667 /*bus_clk = 166.666667MHz*/)
+ ) basic_regs (
.clk(bus_clk), .reset(bus_rst),
.regi_tdata(basic_regi_tdata), .regi_tvalid(basic_regi_tvalid), .regi_tready(basic_regi_tready),
.rego_tdata(basic_rego_tdata), .rego_tvalid(basic_rego_tvalid), .rego_tready(basic_rego_tready),
- .misc_status(misc_status)
+ .misc_status({fpga_status, misc_status})
);
pcie_dma_ctrl #(
@@ -203,8 +211,9 @@ module x300_pcie_int #(
.clk(bus_clk), .reset(bus_rst),
.regi_tdata(dmatx_regi_tdata), .regi_tvalid(dmatx_regi_tvalid), .regi_tready(dmatx_regi_tready),
.rego_tdata(dmatx_rego_tdata), .rego_tvalid(dmatx_rego_tvalid), .rego_tready(dmatx_rego_tready),
- .set_clear(dmatx_clear), .set_frame_size(dmatx_frame_size), .sample_stb(dmatx_samp_stb), .packet_stb(dmatx_pkt_stb),
- .swap_lanes(dmatx_swap), .stream_err(dmatx_error), .rtr_sid(8'h00), .rtr_dst()
+ .set_enabled(dmatx_enabled), .set_clear(dmatx_clear), .set_frame_size(dmatx_frame_size),
+ .sample_stb(dmatx_samp_stb), .packet_stb(dmatx_pkt_stb),
+ .swap_lanes(dmatx_swap), .stream_busy(dmatx_busy), .stream_err(dmatx_error), .rtr_sid(8'h00), .rtr_dst()
);
pcie_dma_ctrl #(
@@ -214,8 +223,9 @@ module x300_pcie_int #(
.clk(bus_clk), .reset(bus_rst),
.regi_tdata(dmarx_regi_tdata), .regi_tvalid(dmarx_regi_tvalid), .regi_tready(dmarx_regi_tready),
.rego_tdata(dmarx_rego_tdata), .rego_tvalid(dmarx_rego_tvalid), .rego_tready(dmarx_rego_tready),
- .set_clear(dmarx_clear), .set_frame_size(dmarx_frame_size), .sample_stb(dmarx_samp_stb), .packet_stb(dmarx_pkt_stb),
- .swap_lanes(dmarx_swap), .stream_err(dmarx_error), .rtr_sid(dmarx_header[7:0]), .rtr_dst(dmarx_pkt_dest)
+ .set_enabled(dmarx_enabled), .set_clear(dmarx_clear), .set_frame_size(dmarx_frame_size),
+ .sample_stb(dmarx_samp_stb), .packet_stb(dmarx_pkt_stb),
+ .swap_lanes(dmarx_swap), .stream_busy(dmarx_busy), .stream_err(dmarx_error), .rtr_sid(dmarx_header[7:0]), .rtr_dst(dmarx_pkt_dest)
);
//
//*******************************************************************************
@@ -223,10 +233,10 @@ module x300_pcie_int #(
//*******************************************************************************
// TX DMA Datapath
//
- wire [(NUM_TX_STREAMS*DMA_STREAM_WIDTH)-1:0] dmatx_tdata_bclk, dmatx_tdata_trun, dmatx_tdata_gt, dmatx_tdata_swap;
- wire [NUM_TX_STREAMS-1:0] dmatx_tvalid_bclk, dmatx_tvalid_trun, dmatx_tvalid_gt;
- wire [NUM_TX_STREAMS-1:0] dmatx_tready_bclk, dmatx_tready_trun, dmatx_tready_gt;
- wire [NUM_TX_STREAMS-1:0] dmatx_tlast_trun, dmatx_tlast_gt;
+ wire [(NUM_TX_STREAMS*DMA_STREAM_WIDTH)-1:0] dmatx_tdata_bclk, dmatx_tdata_in, dmatx_tdata_trun, dmatx_tdata_gt, dmatx_tdata_swap;
+ wire [NUM_TX_STREAMS-1:0] dmatx_tvalid_bclk, dmatx_tvalid_in, dmatx_tvalid_trun, dmatx_tvalid_gt;
+ wire [NUM_TX_STREAMS-1:0] dmatx_tready_bclk, dmatx_tready_in, dmatx_tready_trun, dmatx_tready_gt;
+ wire [NUM_TX_STREAMS-1:0] dmatx_tlast_trun, dmatx_tlast_gt;
wire [DMA_STREAM_WIDTH-1:0] dmatx_tdata_mux;
wire dmatx_tvalid_mux, dmatx_tlast_mux, dmatx_tready_mux;
@@ -240,13 +250,19 @@ module x300_pcie_int #(
.o_aclk(bus_clk), .o_tdata(`GET_DMA_BUS(dmatx_tdata_bclk,i)), .o_tvalid(dmatx_tvalid_bclk[i]), .o_tready(dmatx_tready_bclk[i])
);
+ pcie_lossy_samp_gate tx_samp_gate (
+ .i_tdata(`GET_DMA_BUS(dmatx_tdata_bclk,i)), .i_tvalid(dmatx_tvalid_bclk[i]), .i_tready(dmatx_tready_bclk[i]),
+ .o_tdata(`GET_DMA_BUS(dmatx_tdata_in,i)), .o_tvalid(dmatx_tvalid_in[i]), .o_tready(dmatx_tready_in[i]),
+ .drop(~dmatx_enabled[i]), .dropping(dmatx_busy[i])
+ );
+
data_swapper_64 tx_data_swapper (
- .swap_lanes(`GET_SWAP_BUS(dmatx_swap,i)), .i_tdata(`GET_DMA_BUS(dmatx_tdata_bclk,i)), .o_tdata(`GET_DMA_BUS(dmatx_tdata_swap,i))
+ .swap_lanes(`GET_SWAP_BUS(dmatx_swap,i)), .i_tdata(`GET_DMA_BUS(dmatx_tdata_in,i)), .o_tdata(`GET_DMA_BUS(dmatx_tdata_swap,i))
);
cvita_dechunker tx_dma_dechunker (
.clk(bus_clk), .reset(bus_rst), .clear(dmatx_clear[i]), .frame_size(`GET_FSIZE_BUS(dmatx_frame_size, i)),
- .i_tdata(`GET_DMA_BUS(dmatx_tdata_swap,i)), .i_tvalid(dmatx_tvalid_bclk[i]), .i_tready(dmatx_tready_bclk[i]),
+ .i_tdata(`GET_DMA_BUS(dmatx_tdata_swap,i)), .i_tvalid(dmatx_tvalid_in[i]), .i_tready(dmatx_tready_in[i]),
.o_tdata(`GET_DMA_BUS(dmatx_tdata_trun,i)), .o_tlast(dmatx_tlast_trun[i]), .o_tvalid(dmatx_tvalid_trun[i]), .o_tready(dmatx_tready_trun[i]),
.error(dmatx_error[i])
);
@@ -286,10 +302,10 @@ module x300_pcie_int #(
//*******************************************************************************
// RX DMA Datapath
//
- wire [(NUM_RX_STREAMS*DMA_STREAM_WIDTH)-1:0] dmarx_tdata_bclk, dmarx_tdata_pad, dmarx_tdata_swap;
- wire [NUM_RX_STREAMS-1:0] dmarx_tvalid_bclk, dmarx_tvalid_pad;
- wire [NUM_RX_STREAMS-1:0] dmarx_tready_bclk, dmarx_tready_pad;
- wire [NUM_RX_STREAMS-1:0] dmarx_tlast_bclk, dmarx_tlast_pad;
+ wire [(NUM_RX_STREAMS*DMA_STREAM_WIDTH)-1:0] dmarx_tdata_bclk, dmarx_tdata_pad, dmarx_tdata_swap, dmarx_tdata_out;
+ wire [NUM_RX_STREAMS-1:0] dmarx_tvalid_bclk, dmarx_tvalid_pad, dmarx_tvalid_out;
+ wire [NUM_RX_STREAMS-1:0] dmarx_tready_bclk, dmarx_tready_pad, dmarx_tready_out;
+ wire [NUM_RX_STREAMS-1:0] dmarx_tlast_bclk, dmarx_tlast_pad, dmarx_tlast_out;
wire [DMA_STREAM_WIDTH-1:0] dmarx_tdata_mux;
wire dmarx_tvalid_mux, dmarx_tlast_mux, dmarx_tready_mux;
@@ -331,16 +347,22 @@ module x300_pcie_int #(
.swap_lanes(`GET_SWAP_BUS(dmarx_swap,j)), .i_tdata(`GET_DMA_BUS(dmarx_tdata_pad,j)), .o_tdata(`GET_DMA_BUS(dmarx_tdata_swap,j))
);
+ pcie_lossy_samp_gate rx_samp_gate (
+ .i_tdata(`GET_DMA_BUS(dmarx_tdata_swap,j)), .i_tvalid(dmarx_tvalid_pad[j]), .i_tready(dmarx_tready_pad[j]),
+ .o_tdata(`GET_DMA_BUS(dmarx_tdata_out,j)), .o_tvalid(dmarx_tvalid_out[j]), .o_tready(dmarx_tready_out[j]),
+ .drop(~dmarx_enabled[j]), .dropping(dmarx_busy[j])
+ );
+
axi_fifo_2clk #(.WIDTH(DMA_STREAM_WIDTH), .SIZE(DMA_CLK_XING_FIFO_SIZE)) rx_dma_clock_crossing_fifo (
.reset(bus_rst),
- .i_aclk(bus_clk), .i_tdata(`GET_DMA_BUS(dmarx_tdata_swap,j)), .i_tvalid(dmarx_tvalid_pad[j]), .i_tready(dmarx_tready_pad[j]),
+ .i_aclk(bus_clk), .i_tdata(`GET_DMA_BUS(dmarx_tdata_out,j)), .i_tvalid(dmarx_tvalid_out[j]), .i_tready(dmarx_tready_out[j]),
.o_aclk(ioport2_clk), .o_tdata(`GET_DMA_BUS(dmarx_tdata_iop2,j)), .o_tvalid(dmarx_tvalid_iop2[j]), .o_tready(dmarx_tready_iop2[j])
);
end
endgenerate
//
//*******************************************************************************
-
+
endmodule
`undef GET_DMA_BUS
diff --git a/fpga/usrp3/top/x300/x300_pcie_int_tb.v b/fpga/usrp3/top/x300/x300_pcie_int_tb.v
index 0dff7cc65..ed47c2192 100644
--- a/fpga/usrp3/top/x300/x300_pcie_int_tb.v
+++ b/fpga/usrp3/top/x300/x300_pcie_int_tb.v
@@ -215,7 +215,7 @@ module x300_pcie_int_tb();
TEST_CASE();
usr_regport_request(READ, 20'hC, 32'h0);
usr_regport_response();
- `CHECK_TRUE((pcie_usr_data == 175000000), "Verify counter frequency register");
+ `CHECK_TRUE((pcie_usr_data == 166666667), "Verify counter frequency register");
TEST_CASE();
usr_regport_request(WRITE, 20'h10, 32'hDEAD);