fpga: Update all RFNoC images

4 files changed, 109 insertions, 101 deletions

diff --git a/fpga/usrp3/top/x300/x300_rfnoc_image_core.v b/fpga/usrp3/top/x300/x300_rfnoc_image_core.v
index dced3c4cb..a0f69c38c 100644
--- a/fpga/usrp3/top/x300/x300_rfnoc_image_core.v
+++ b/fpga/usrp3/top/x300/x300_rfnoc_image_core.v
@@ -1,5 +1,5 @@
 //
-// Copyright 2021 Ettus Research, A National Instruments Brand
+// Copyright 2022 Ettus Research, A National Instruments Brand
 //
 // SPDX-License-Identifier: LGPL-3.0-or-later
 //
@@ -13,9 +13,9 @@
 //   This file was automatically generated by the RFNoC image builder tool.
 //   Re-running that tool will overwrite this file!
 //
-// File generated on: 2021-05-03T08:51:06.967425
+// File generated on: 2022-03-29T22:54:32.588967
 // Source: x300_rfnoc_image_core.yml
-// Source SHA256: 32a28be8a0bcbe6bb9a5df0058b3c813741fa80c1faafd11270d8b500d7d9b85
+// Source SHA256: 320ab21201cdeaa19e38979dd05012652dec06a89593d17b611d029e6b83d0e5
 //
 
 `default_nettype none
@@ -61,26 +61,26 @@ module rfnoc_image_core #(
   input  wire [   0:0] m_ctrlport_radio1_resp_ack,
   input  wire [   1:0] m_ctrlport_radio1_resp_status,
   input  wire [  31:0] m_ctrlport_radio1_resp_data,
-  // time_keeper
+  // time
   input  wire [  63:0] radio_time,
-  // x300_radio0
-  input  wire [  63:0] radio_rx_data_radio0,
-  input  wire [   1:0] radio_rx_stb_radio0,
-  output wire [   1:0] radio_rx_running_radio0,
-  output wire [  63:0] radio_tx_data_radio0,
-  input  wire [   1:0] radio_tx_stb_radio0,
-  output wire [   1:0] radio_tx_running_radio0,
-  // x300_radio1
-  input  wire [  63:0] radio_rx_data_radio1,
-  input  wire [   1:0] radio_rx_stb_radio1,
-  output wire [   1:0] radio_rx_running_radio1,
-  output wire [  63:0] radio_tx_data_radio1,
-  input  wire [   1:0] radio_tx_stb_radio1,
-  output wire [   1:0] radio_tx_running_radio1,
+  // radio0
+  input  wire [ 255:0] radio_rx_data_radio0,
+  input  wire [   7:0] radio_rx_stb_radio0,
+  output wire [   7:0] radio_rx_running_radio0,
+  output wire [ 255:0] radio_tx_data_radio0,
+  input  wire [   7:0] radio_tx_stb_radio0,
+  output wire [   7:0] radio_tx_running_radio0,
+  // radio1
+  input  wire [ 255:0] radio_rx_data_radio1,
+  input  wire [   7:0] radio_rx_stb_radio1,
+  output wire [   7:0] radio_rx_running_radio1,
+  output wire [ 255:0] radio_tx_data_radio1,
+  input  wire [   7:0] radio_tx_stb_radio1,
+  output wire [   7:0] radio_tx_running_radio1,
   // dram
   input  wire [   0:0] axi_rst,
   output wire [   3:0] m_axi_awid,
-  output wire [ 127:0] m_axi_awaddr,
+  output wire [ 191:0] m_axi_awaddr,
   output wire [  31:0] m_axi_awlen,
   output wire [  11:0] m_axi_awsize,
   output wire [   7:0] m_axi_awburst,
@@ -92,8 +92,8 @@ module rfnoc_image_core #(
   output wire [   3:0] m_axi_awuser,
   output wire [   3:0] m_axi_awvalid,
   input  wire [   3:0] m_axi_awready,
-  output wire [ 255:0] m_axi_wdata,
-  output wire [  31:0] m_axi_wstrb,
+  output wire [2047:0] m_axi_wdata,
+  output wire [ 255:0] m_axi_wstrb,
   output wire [   3:0] m_axi_wlast,
   output wire [   3:0] m_axi_wuser,
   output wire [   3:0] m_axi_wvalid,
@@ -104,7 +104,7 @@ module rfnoc_image_core #(
   input  wire [   3:0] m_axi_bvalid,
   output wire [   3:0] m_axi_bready,
   output wire [   3:0] m_axi_arid,
-  output wire [ 127:0] m_axi_araddr,
+  output wire [ 191:0] m_axi_araddr,
   output wire [  31:0] m_axi_arlen,
   output wire [  11:0] m_axi_arsize,
   output wire [   7:0] m_axi_arburst,
@@ -117,7 +117,7 @@ module rfnoc_image_core #(
   output wire [   3:0] m_axi_arvalid,
   input  wire [   3:0] m_axi_arready,
   input  wire [   3:0] m_axi_rid,
-  input  wire [ 255:0] m_axi_rdata,
+  input  wire [2047:0] m_axi_rdata,
   input  wire [   7:0] m_axi_rresp,
   input  wire [   3:0] m_axi_rlast,
   input  wire [   3:0] m_axi_ruser,
@@ -873,7 +873,7 @@ module rfnoc_image_core #(
   wire              m_radio0_out_1_tvalid, m_radio0_out_0_tvalid;
   wire              m_radio0_out_1_tready, m_radio0_out_0_tready;
 
-  // ctrl_port
+  // ctrlport
   wire [   0:0] radio0_m_ctrlport_req_wr;
   wire [   0:0] radio0_m_ctrlport_req_rd;
   wire [  19:0] radio0_m_ctrlport_req_addr;
@@ -884,20 +884,22 @@ module rfnoc_image_core #(
   wire [   0:0] radio0_m_ctrlport_resp_ack;
   wire [   1:0] radio0_m_ctrlport_resp_status;
   wire [  31:0] radio0_m_ctrlport_resp_data;
-  // time_keeper
+  // time
   wire [  63:0] radio0_radio_time;
-  // x300_radio
-  wire [  63:0] radio0_radio_rx_data;
-  wire [   1:0] radio0_radio_rx_stb;
-  wire [   1:0] radio0_radio_rx_running;
-  wire [  63:0] radio0_radio_tx_data;
-  wire [   1:0] radio0_radio_tx_stb;
-  wire [   1:0] radio0_radio_tx_running;
+  // radio
+  wire [ 255:0] radio0_radio_rx_data;
+  wire [   7:0] radio0_radio_rx_stb;
+  wire [   7:0] radio0_radio_rx_running;
+  wire [ 255:0] radio0_radio_tx_data;
+  wire [   7:0] radio0_radio_tx_stb;
+  wire [   7:0] radio0_radio_tx_running;
 
   rfnoc_block_radio #(
     .THIS_PORTID         (4),
     .CHDR_W              (CHDR_W),
     .NUM_PORTS           (2),
+    .NIPC                (1),
+    .ITEM_W              (32),
     .MTU                 (MTU)
   ) b_radio0_2 (
     .rfnoc_chdr_clk      (rfnoc_chdr_clk),
@@ -1044,7 +1046,7 @@ module rfnoc_image_core #(
   wire              m_radio1_out_1_tvalid, m_radio1_out_0_tvalid;
   wire              m_radio1_out_1_tready, m_radio1_out_0_tready;
 
-  // ctrl_port
+  // ctrlport
   wire [   0:0] radio1_m_ctrlport_req_wr;
   wire [   0:0] radio1_m_ctrlport_req_rd;
   wire [  19:0] radio1_m_ctrlport_req_addr;
@@ -1055,20 +1057,22 @@ module rfnoc_image_core #(
   wire [   0:0] radio1_m_ctrlport_resp_ack;
   wire [   1:0] radio1_m_ctrlport_resp_status;
   wire [  31:0] radio1_m_ctrlport_resp_data;
-  // time_keeper
+  // time
   wire [  63:0] radio1_radio_time;
-  // x300_radio
-  wire [  63:0] radio1_radio_rx_data;
-  wire [   1:0] radio1_radio_rx_stb;
-  wire [   1:0] radio1_radio_rx_running;
-  wire [  63:0] radio1_radio_tx_data;
-  wire [   1:0] radio1_radio_tx_stb;
-  wire [   1:0] radio1_radio_tx_running;
+  // radio
+  wire [ 255:0] radio1_radio_rx_data;
+  wire [   7:0] radio1_radio_rx_stb;
+  wire [   7:0] radio1_radio_rx_running;
+  wire [ 255:0] radio1_radio_tx_data;
+  wire [   7:0] radio1_radio_tx_stb;
+  wire [   7:0] radio1_radio_tx_running;
 
   rfnoc_block_radio #(
     .THIS_PORTID         (7),
     .CHDR_W              (CHDR_W),
     .NUM_PORTS           (2),
+    .NIPC                (1),
+    .ITEM_W              (32),
     .MTU                 (MTU)
   ) b_radio1_5 (
     .rfnoc_chdr_clk      (rfnoc_chdr_clk),
@@ -1128,7 +1132,7 @@ module rfnoc_image_core #(
   // axi_ram
   wire [   0:0] replay0_axi_rst;
   wire [   3:0] replay0_m_axi_awid;
-  wire [ 127:0] replay0_m_axi_awaddr;
+  wire [ 191:0] replay0_m_axi_awaddr;
   wire [  31:0] replay0_m_axi_awlen;
   wire [  11:0] replay0_m_axi_awsize;
   wire [   7:0] replay0_m_axi_awburst;
@@ -1140,8 +1144,8 @@ module rfnoc_image_core #(
   wire [   3:0] replay0_m_axi_awuser;
   wire [   3:0] replay0_m_axi_awvalid;
   wire [   3:0] replay0_m_axi_awready;
-  wire [ 255:0] replay0_m_axi_wdata;
-  wire [  31:0] replay0_m_axi_wstrb;
+  wire [2047:0] replay0_m_axi_wdata;
+  wire [ 255:0] replay0_m_axi_wstrb;
   wire [   3:0] replay0_m_axi_wlast;
   wire [   3:0] replay0_m_axi_wuser;
   wire [   3:0] replay0_m_axi_wvalid;
@@ -1152,7 +1156,7 @@ module rfnoc_image_core #(
   wire [   3:0] replay0_m_axi_bvalid;
   wire [   3:0] replay0_m_axi_bready;
   wire [   3:0] replay0_m_axi_arid;
-  wire [ 127:0] replay0_m_axi_araddr;
+  wire [ 191:0] replay0_m_axi_araddr;
   wire [  31:0] replay0_m_axi_arlen;
   wire [  11:0] replay0_m_axi_arsize;
   wire [   7:0] replay0_m_axi_arburst;
@@ -1165,7 +1169,7 @@ module rfnoc_image_core #(
   wire [   3:0] replay0_m_axi_arvalid;
   wire [   3:0] replay0_m_axi_arready;
   wire [   3:0] replay0_m_axi_rid;
-  wire [ 255:0] replay0_m_axi_rdata;
+  wire [2047:0] replay0_m_axi_rdata;
   wire [   7:0] replay0_m_axi_rresp;
   wire [   3:0] replay0_m_axi_rlast;
   wire [   3:0] replay0_m_axi_ruser;
diff --git a/fpga/usrp3/top/x300/x300_rfnoc_image_core.vh b/fpga/usrp3/top/x300/x300_rfnoc_image_core.vh
index a651f32d1..069a66171 100644
--- a/fpga/usrp3/top/x300/x300_rfnoc_image_core.vh
+++ b/fpga/usrp3/top/x300/x300_rfnoc_image_core.vh
@@ -1,5 +1,5 @@
 //
-// Copyright 2021 Ettus Research, A National Instruments Brand
+// Copyright 2022 Ettus Research, A National Instruments Brand
 //
 // SPDX-License-Identifier: LGPL-3.0-or-later
 //
@@ -12,9 +12,9 @@
 //   This file was automatically generated by the RFNoC image builder tool.
 //   Re-running that tool will overwrite this file!
 //
-// File generated on: 2021-05-03T08:51:07.013471
+// File generated on: 2022-03-29T22:54:32.623216
 // Source: x300_rfnoc_image_core.yml
-// Source SHA256: 32a28be8a0bcbe6bb9a5df0058b3c813741fa80c1faafd11270d8b500d7d9b85
+// Source SHA256: 320ab21201cdeaa19e38979dd05012652dec06a89593d17b611d029e6b83d0e5
 //
 
 `define CHDR_WIDTH     64
diff --git a/fpga/usrp3/top/x300/x310_rfnoc_image_core.v b/fpga/usrp3/top/x300/x310_rfnoc_image_core.v
index 45588a7b0..43914f464 100644
--- a/fpga/usrp3/top/x300/x310_rfnoc_image_core.v
+++ b/fpga/usrp3/top/x300/x310_rfnoc_image_core.v
@@ -1,9 +1,9 @@
 //
-// Copyright 2021 Ettus Research, A National Instruments Brand
+// Copyright 2022 Ettus Research, A National Instruments Brand
 //
 // SPDX-License-Identifier: LGPL-3.0-or-later
 //
-// Module: rfnoc_image_core (for x300)
+// Module: rfnoc_image_core (for x310)
 //
 // Description:
 //
@@ -13,9 +13,9 @@
 //   This file was automatically generated by the RFNoC image builder tool.
 //   Re-running that tool will overwrite this file!
 //
-// File generated on: 2021-05-03T08:51:07.732667
+// File generated on: 2022-03-29T22:54:33.009325
 // Source: x310_rfnoc_image_core.yml
-// Source SHA256: 7a01e3b4aa95b9e5b59f627d5a7d3f27c16afb4bb6bdad1f7fb9a624fb4b9647
+// Source SHA256: 0b0f8a65bb28bcc85d7f926712074af71994564ef9dea213fbbe2313a3bfd26d
 //
 
 `default_nettype none
@@ -61,26 +61,26 @@ module rfnoc_image_core #(
   input  wire [   0:0] m_ctrlport_radio1_resp_ack,
   input  wire [   1:0] m_ctrlport_radio1_resp_status,
   input  wire [  31:0] m_ctrlport_radio1_resp_data,
-  // time_keeper
+  // time
   input  wire [  63:0] radio_time,
-  // x300_radio0
-  input  wire [  63:0] radio_rx_data_radio0,
-  input  wire [   1:0] radio_rx_stb_radio0,
-  output wire [   1:0] radio_rx_running_radio0,
-  output wire [  63:0] radio_tx_data_radio0,
-  input  wire [   1:0] radio_tx_stb_radio0,
-  output wire [   1:0] radio_tx_running_radio0,
-  // x300_radio1
-  input  wire [  63:0] radio_rx_data_radio1,
-  input  wire [   1:0] radio_rx_stb_radio1,
-  output wire [   1:0] radio_rx_running_radio1,
-  output wire [  63:0] radio_tx_data_radio1,
-  input  wire [   1:0] radio_tx_stb_radio1,
-  output wire [   1:0] radio_tx_running_radio1,
+  // radio0
+  input  wire [ 255:0] radio_rx_data_radio0,
+  input  wire [   7:0] radio_rx_stb_radio0,
+  output wire [   7:0] radio_rx_running_radio0,
+  output wire [ 255:0] radio_tx_data_radio0,
+  input  wire [   7:0] radio_tx_stb_radio0,
+  output wire [   7:0] radio_tx_running_radio0,
+  // radio1
+  input  wire [ 255:0] radio_rx_data_radio1,
+  input  wire [   7:0] radio_rx_stb_radio1,
+  output wire [   7:0] radio_rx_running_radio1,
+  output wire [ 255:0] radio_tx_data_radio1,
+  input  wire [   7:0] radio_tx_stb_radio1,
+  output wire [   7:0] radio_tx_running_radio1,
   // dram
   input  wire [   0:0] axi_rst,
   output wire [   3:0] m_axi_awid,
-  output wire [ 127:0] m_axi_awaddr,
+  output wire [ 191:0] m_axi_awaddr,
   output wire [  31:0] m_axi_awlen,
   output wire [  11:0] m_axi_awsize,
   output wire [   7:0] m_axi_awburst,
@@ -92,8 +92,8 @@ module rfnoc_image_core #(
   output wire [   3:0] m_axi_awuser,
   output wire [   3:0] m_axi_awvalid,
   input  wire [   3:0] m_axi_awready,
-  output wire [ 255:0] m_axi_wdata,
-  output wire [  31:0] m_axi_wstrb,
+  output wire [2047:0] m_axi_wdata,
+  output wire [ 255:0] m_axi_wstrb,
   output wire [   3:0] m_axi_wlast,
   output wire [   3:0] m_axi_wuser,
   output wire [   3:0] m_axi_wvalid,
@@ -104,7 +104,7 @@ module rfnoc_image_core #(
   input  wire [   3:0] m_axi_bvalid,
   output wire [   3:0] m_axi_bready,
   output wire [   3:0] m_axi_arid,
-  output wire [ 127:0] m_axi_araddr,
+  output wire [ 191:0] m_axi_araddr,
   output wire [  31:0] m_axi_arlen,
   output wire [  11:0] m_axi_arsize,
   output wire [   7:0] m_axi_arburst,
@@ -117,7 +117,7 @@ module rfnoc_image_core #(
   output wire [   3:0] m_axi_arvalid,
   input  wire [   3:0] m_axi_arready,
   input  wire [   3:0] m_axi_rid,
-  input  wire [ 255:0] m_axi_rdata,
+  input  wire [2047:0] m_axi_rdata,
   input  wire [   7:0] m_axi_rresp,
   input  wire [   3:0] m_axi_rlast,
   input  wire [   3:0] m_axi_ruser,
@@ -873,7 +873,7 @@ module rfnoc_image_core #(
   wire              m_radio0_out_1_tvalid, m_radio0_out_0_tvalid;
   wire              m_radio0_out_1_tready, m_radio0_out_0_tready;
 
-  // ctrl_port
+  // ctrlport
   wire [   0:0] radio0_m_ctrlport_req_wr;
   wire [   0:0] radio0_m_ctrlport_req_rd;
   wire [  19:0] radio0_m_ctrlport_req_addr;
@@ -884,20 +884,22 @@ module rfnoc_image_core #(
   wire [   0:0] radio0_m_ctrlport_resp_ack;
   wire [   1:0] radio0_m_ctrlport_resp_status;
   wire [  31:0] radio0_m_ctrlport_resp_data;
-  // time_keeper
+  // time
   wire [  63:0] radio0_radio_time;
-  // x300_radio
-  wire [  63:0] radio0_radio_rx_data;
-  wire [   1:0] radio0_radio_rx_stb;
-  wire [   1:0] radio0_radio_rx_running;
-  wire [  63:0] radio0_radio_tx_data;
-  wire [   1:0] radio0_radio_tx_stb;
-  wire [   1:0] radio0_radio_tx_running;
+  // radio
+  wire [ 255:0] radio0_radio_rx_data;
+  wire [   7:0] radio0_radio_rx_stb;
+  wire [   7:0] radio0_radio_rx_running;
+  wire [ 255:0] radio0_radio_tx_data;
+  wire [   7:0] radio0_radio_tx_stb;
+  wire [   7:0] radio0_radio_tx_running;
 
   rfnoc_block_radio #(
     .THIS_PORTID         (4),
     .CHDR_W              (CHDR_W),
     .NUM_PORTS           (2),
+    .NIPC                (1),
+    .ITEM_W              (32),
     .MTU                 (MTU)
   ) b_radio0_2 (
     .rfnoc_chdr_clk      (rfnoc_chdr_clk),
@@ -1044,7 +1046,7 @@ module rfnoc_image_core #(
   wire              m_radio1_out_1_tvalid, m_radio1_out_0_tvalid;
   wire              m_radio1_out_1_tready, m_radio1_out_0_tready;
 
-  // ctrl_port
+  // ctrlport
   wire [   0:0] radio1_m_ctrlport_req_wr;
   wire [   0:0] radio1_m_ctrlport_req_rd;
   wire [  19:0] radio1_m_ctrlport_req_addr;
@@ -1055,20 +1057,22 @@ module rfnoc_image_core #(
   wire [   0:0] radio1_m_ctrlport_resp_ack;
   wire [   1:0] radio1_m_ctrlport_resp_status;
   wire [  31:0] radio1_m_ctrlport_resp_data;
-  // time_keeper
+  // time
   wire [  63:0] radio1_radio_time;
-  // x300_radio
-  wire [  63:0] radio1_radio_rx_data;
-  wire [   1:0] radio1_radio_rx_stb;
-  wire [   1:0] radio1_radio_rx_running;
-  wire [  63:0] radio1_radio_tx_data;
-  wire [   1:0] radio1_radio_tx_stb;
-  wire [   1:0] radio1_radio_tx_running;
+  // radio
+  wire [ 255:0] radio1_radio_rx_data;
+  wire [   7:0] radio1_radio_rx_stb;
+  wire [   7:0] radio1_radio_rx_running;
+  wire [ 255:0] radio1_radio_tx_data;
+  wire [   7:0] radio1_radio_tx_stb;
+  wire [   7:0] radio1_radio_tx_running;
 
   rfnoc_block_radio #(
     .THIS_PORTID         (7),
     .CHDR_W              (CHDR_W),
     .NUM_PORTS           (2),
+    .NIPC                (1),
+    .ITEM_W              (32),
     .MTU                 (MTU)
   ) b_radio1_5 (
     .rfnoc_chdr_clk      (rfnoc_chdr_clk),
@@ -1128,7 +1132,7 @@ module rfnoc_image_core #(
   // axi_ram
   wire [   0:0] replay0_axi_rst;
   wire [   3:0] replay0_m_axi_awid;
-  wire [ 127:0] replay0_m_axi_awaddr;
+  wire [ 191:0] replay0_m_axi_awaddr;
   wire [  31:0] replay0_m_axi_awlen;
   wire [  11:0] replay0_m_axi_awsize;
   wire [   7:0] replay0_m_axi_awburst;
@@ -1140,8 +1144,8 @@ module rfnoc_image_core #(
   wire [   3:0] replay0_m_axi_awuser;
   wire [   3:0] replay0_m_axi_awvalid;
   wire [   3:0] replay0_m_axi_awready;
-  wire [ 255:0] replay0_m_axi_wdata;
-  wire [  31:0] replay0_m_axi_wstrb;
+  wire [2047:0] replay0_m_axi_wdata;
+  wire [ 255:0] replay0_m_axi_wstrb;
   wire [   3:0] replay0_m_axi_wlast;
   wire [   3:0] replay0_m_axi_wuser;
   wire [   3:0] replay0_m_axi_wvalid;
@@ -1152,7 +1156,7 @@ module rfnoc_image_core #(
   wire [   3:0] replay0_m_axi_bvalid;
   wire [   3:0] replay0_m_axi_bready;
   wire [   3:0] replay0_m_axi_arid;
-  wire [ 127:0] replay0_m_axi_araddr;
+  wire [ 191:0] replay0_m_axi_araddr;
   wire [  31:0] replay0_m_axi_arlen;
   wire [  11:0] replay0_m_axi_arsize;
   wire [   7:0] replay0_m_axi_arburst;
@@ -1165,7 +1169,7 @@ module rfnoc_image_core #(
   wire [   3:0] replay0_m_axi_arvalid;
   wire [   3:0] replay0_m_axi_arready;
   wire [   3:0] replay0_m_axi_rid;
-  wire [ 255:0] replay0_m_axi_rdata;
+  wire [2047:0] replay0_m_axi_rdata;
   wire [   7:0] replay0_m_axi_rresp;
   wire [   3:0] replay0_m_axi_rlast;
   wire [   3:0] replay0_m_axi_ruser;
@@ -1176,8 +1180,8 @@ module rfnoc_image_core #(
     .THIS_PORTID         (8),
     .CHDR_W              (CHDR_W),
     .NUM_PORTS           (2),
-    .MEM_ADDR_W          (30),
     .MEM_DATA_W          (64),
+    .MEM_ADDR_W          (30),
     .MTU                 (MTU)
   ) b_replay0_6 (
     .rfnoc_chdr_clk      (rfnoc_chdr_clk),
diff --git a/fpga/usrp3/top/x300/x310_rfnoc_image_core.vh b/fpga/usrp3/top/x300/x310_rfnoc_image_core.vh
index 977751101..261b08aec 100644
--- a/fpga/usrp3/top/x300/x310_rfnoc_image_core.vh
+++ b/fpga/usrp3/top/x300/x310_rfnoc_image_core.vh
@@ -1,9 +1,9 @@
 //
-// Copyright 2021 Ettus Research, A National Instruments Brand
+// Copyright 2022 Ettus Research, A National Instruments Brand
 //
 // SPDX-License-Identifier: LGPL-3.0-or-later
 //
-// Header: rfnoc_image_core.vh (for x300)
+// Header: rfnoc_image_core.vh (for x310)
 //
 // Description:
 //
@@ -12,9 +12,9 @@
 //   This file was automatically generated by the RFNoC image builder tool.
 //   Re-running that tool will overwrite this file!
 //
-// File generated on: 2021-05-03T08:51:07.779170
+// File generated on: 2022-03-29T22:54:33.044163
 // Source: x310_rfnoc_image_core.yml
-// Source SHA256: 7a01e3b4aa95b9e5b59f627d5a7d3f27c16afb4bb6bdad1f7fb9a624fb4b9647
+// Source SHA256: 0b0f8a65bb28bcc85d7f926712074af71994564ef9dea213fbbe2313a3bfd26d
 //
 
 `define CHDR_WIDTH     64