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| author | Ashish Chaudhari <ashish@ettus.com> | 2014-09-24 18:45:31 -0700 |
|---|---|---|
| committer | Ashish Chaudhari <ashish@ettus.com> | 2014-09-24 18:45:31 -0700 |
| commit | 64d71dcbc5fa6790385b288de25224d386b047b0 (patch) | |
| tree | 05d1048d44f5347f39b4036163a758e0a75d1ea3 /fpga/usrp3/top/x300/x300.ucf | |
| parent | ecdd34c08b79117c4f739b336daeb4b9d2bc8df3 (diff) | |
| download | uhd-64d71dcbc5fa6790385b288de25224d386b047b0.tar.gz uhd-64d71dcbc5fa6790385b288de25224d386b047b0.tar.bz2 uhd-64d71dcbc5fa6790385b288de25224d386b047b0.zip | |
fpga: Multiple X300 FPGA bugfixes and enhancements
- Fixed 10GigE firmware communication issues and sequence errors for TX
- Multiple changes to help ease timing closure
- Cleaned up build scripts
- Switched to Xilinx ISE 14.7 as the default build tool for X300
Diffstat (limited to 'fpga/usrp3/top/x300/x300.ucf')
| -rw-r--r-- | fpga/usrp3/top/x300/x300.ucf | 18 |
1 files changed, 9 insertions, 9 deletions
diff --git a/fpga/usrp3/top/x300/x300.ucf b/fpga/usrp3/top/x300/x300.ucf index ab7c65c98..e73c58e20 100644 --- a/fpga/usrp3/top/x300/x300.ucf +++ b/fpga/usrp3/top/x300/x300.ucf @@ -7,15 +7,15 @@ ## SFP Lanes # SFP clock pins now come from their own ucf files. See _10ge.ucf, _1ge.ucf, and _cpri.ucf -NET SFP0_RX_n LOC = AA3; #IJB. NOTE this signal prefixed SFP1 on schematics -NET SFP0_RX_p LOC = AA4; #IJB. NOTE this signal prefixed SFP1 on schematics -NET SFP0_TX_n LOC = Y1; #IJB. NOTE this signal prefixed SFP1 on schematics -NET SFP0_TX_p LOC = Y2; #IJB. NOTE this signal prefixed SFP1 on schematics -NET SFP1_RX_n LOC = T5; #IJB. NOTE this signal prefixed SFP2 on schematics -NET SFP1_RX_p LOC = T6; #IJB. NOTE this signal prefixed SFP2 on schematics -NET SFP1_TX_n LOC = P1; #IJB. NOTE this signal prefixed SFP2 on schematics -NET SFP1_TX_p LOC = P2; #IJB. NOTE this signal prefixed SFP2 on schematics - +# NOTE: In the schematic SFP0 signals are prefixed SFP1 and SFP1 signals are prefixed SFP2 +NET SFP0_RX_n IOSTANDARD = LVDS | LOC = AA3; +NET SFP0_RX_p IOSTANDARD = LVDS | LOC = AA4; +NET SFP0_TX_n IOSTANDARD = LVDS | LOC = Y1; +NET SFP0_TX_p IOSTANDARD = LVDS | LOC = Y2; +NET SFP1_RX_n IOSTANDARD = LVDS | LOC = T5; +NET SFP1_RX_p IOSTANDARD = LVDS | LOC = T6; +NET SFP1_TX_n IOSTANDARD = LVDS | LOC = P1; +NET SFP1_TX_p IOSTANDARD = LVDS | LOC = P2; ## ADC 0 NET DB0_ADC_DA0_N IOSTANDARD = LVDS_25 | LOC = L27; |