diff options
| author | Ashish Chaudhari <ashish@ettus.com> | 2014-08-19 12:05:46 -0700 |
|---|---|---|
| committer | Ashish Chaudhari <ashish@ettus.com> | 2014-08-19 12:05:46 -0700 |
| commit | 3347e831f002da769632dfe0c70ea17c2d749a8a (patch) | |
| tree | 2f0709264061d440cf24c8060478f0344e41c1a1 /fpga/usrp3/top/x300/timing.ucf | |
| parent | a38fee789d66b87b9e25edcfcf47247fe11f8371 (diff) | |
| download | uhd-3347e831f002da769632dfe0c70ea17c2d749a8a.tar.gz uhd-3347e831f002da769632dfe0c70ea17c2d749a8a.tar.bz2 uhd-3347e831f002da769632dfe0c70ea17c2d749a8a.zip | |
fpga: Added FPGA code for X300 MIMO alignment bugfix
Diffstat (limited to 'fpga/usrp3/top/x300/timing.ucf')
| -rw-r--r-- | fpga/usrp3/top/x300/timing.ucf | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/fpga/usrp3/top/x300/timing.ucf b/fpga/usrp3/top/x300/timing.ucf index a84a92a63..b638b2c99 100644 --- a/fpga/usrp3/top/x300/timing.ucf +++ b/fpga/usrp3/top/x300/timing.ucf @@ -34,3 +34,8 @@ TIMESPEC TS_IOPORT2_CLK_TO_BUS_CLK_FALEPATH = FROM ioport2_clk_grp TO bus_clk_gr TIMESPEC TS_IOPORT2_CLK_TO_RIO40_CLK_FALEPATH = FROM ioport2_clk_grp TO rio40_clk_grp TIG; TIMESPEC TS_RIO40_CLK_TO_IOPORT2_CLK_FALEPATH = FROM rio40_clk_grp TO ioport2_clk_grp TIG; +# FPGA_CLK_p/n is externally phase shifted to allow for crossing from the ADC clock domain +# to the radio_clk (aka FPGA_CLK_p/n) clock domain. To ensure this timing is consistent, +# lock the locations of the MMCM and BUFG to generate radio_clk. +INST "radio_clk_gen/mmcm_adv_inst" LOC = MMCME2_ADV_X0Y0; +INST "radio_clk_gen/clkout1_buf" LOC = BUFGCTRL_X0Y8;
\ No newline at end of file |