fpga: Update rfnoc_image_core for all targets

Update rfnoc_image_core.v to take into account the new image_core_name
fields and version strings. Add new rfnoc_image_core.vh. Update YAML
where needed.

3 files changed, 261 insertions, 196 deletions

diff --git a/fpga/usrp3/top/e31x/e310_rfnoc_image_core.v b/fpga/usrp3/top/e31x/e310_rfnoc_image_core.v
index 9b288ad16..5d3e47f35 100644
--- a/fpga/usrp3/top/e31x/e310_rfnoc_image_core.v
+++ b/fpga/usrp3/top/e31x/e310_rfnoc_image_core.v
@@ -1,68 +1,86 @@
 //
-// Copyright 2020 Ettus Research, A National Instruments Brand
+// Copyright 2021 Ettus Research, A National Instruments Brand
 //
 // SPDX-License-Identifier: LGPL-3.0-or-later
 //
-
 // Module: rfnoc_image_core (for e31x)
-// This file was autogenerated by UHD's image builder tool (rfnoc_image_builder)
-// Re-running that tool will overwrite this file!
-// File generated on: 2020-09-08T10:54:16.062742
+//
+// Description:
+//
+//   The RFNoC Image Core contains the Verilog description of the RFNoC design
+//   to be loaded onto the FPGA.
+//
+//   This file was automatically generated by the RFNoC image builder tool.
+//   Re-running that tool will overwrite this file!
+//
+// File generated on: 2021-05-03T08:51:11.395850
 // Source: e310_rfnoc_image_core.yml
-// Source SHA256: 00908abb846aaf175d1f8f2e75c6d39a3cd4958b326ab3125f4a1023c7b78b39
+// Source SHA256: 7fef622f1ae280dd7573abd823c7a6bbecf51921a74cea948e6bfb9f8f65e2cc
+//
+
+`default_nettype none
+
 
 module rfnoc_image_core #(
-  parameter [15:0] PROTOVER = {8'd1, 8'd0}
-)(
+  parameter        CHDR_W     = 64,
+  parameter        MTU        = 10,
+  parameter [15:0] PROTOVER   = {8'd1, 8'd0},
+  parameter        RADIO_NIPC = 1
+) (
   // Clocks
   input  wire         chdr_aclk,
   input  wire         ctrl_aclk,
   input  wire         core_arst,
   input  wire         radio_clk,
   // Basic
-  input  wire [15:0]  device_id,
-//// IO ports //////////////////////////////////
-//  ctrlport_radio
-  output wire [  1-1:0] m_ctrlport_req_wr,
-  output wire [  1-1:0] m_ctrlport_req_rd,
-  output wire [ 20-1:0] m_ctrlport_req_addr,
-  output wire [ 32-1:0] m_ctrlport_req_data,
-  output wire [  4-1:0] m_ctrlport_req_byte_en,
-  output wire [  1-1:0] m_ctrlport_req_has_time,
-  output wire [ 64-1:0] m_ctrlport_req_time,
-  input  wire [  1-1:0] m_ctrlport_resp_ack,
-  input  wire [  2-1:0] m_ctrlport_resp_status,
-  input  wire [ 32-1:0] m_ctrlport_resp_data,
-//  time_keeper
-  input  wire [ 64-1:0] radio_time,
-//  x300_radio
-  input  wire [ 64-1:0] radio_rx_data,
-  input  wire [  2-1:0] radio_rx_stb,
-  output wire [  2-1:0] radio_rx_running,
-  output wire [ 64-1:0] radio_tx_data,
-  input  wire [  2-1:0] radio_tx_stb,
-  output wire [  2-1:0] radio_tx_running,
-  // Transport 0 (dma dma)
-  input  wire [64-1:0]  s_dma_tdata,
-  input  wire         s_dma_tlast,
-  input  wire         s_dma_tvalid,
-  output wire         s_dma_tready,
-  output wire [64-1:0]  m_dma_tdata,
-  output wire         m_dma_tlast,
-  output wire         m_dma_tvalid,
-  input  wire         m_dma_tready
+  input  wire [  15:0] device_id,
+
+  // IO ports /////////////////////////
+
+  // ctrlport_radio
+  output wire [   0:0] m_ctrlport_req_wr,
+  output wire [   0:0] m_ctrlport_req_rd,
+  output wire [  19:0] m_ctrlport_req_addr,
+  output wire [  31:0] m_ctrlport_req_data,
+  output wire [   3:0] m_ctrlport_req_byte_en,
+  output wire [   0:0] m_ctrlport_req_has_time,
+  output wire [  63:0] m_ctrlport_req_time,
+  input  wire [   0:0] m_ctrlport_resp_ack,
+  input  wire [   1:0] m_ctrlport_resp_status,
+  input  wire [  31:0] m_ctrlport_resp_data,
+  // time_keeper
+  input  wire [  63:0] radio_time,
+  // x300_radio
+  input  wire [  63:0] radio_rx_data,
+  input  wire [   1:0] radio_rx_stb,
+  output wire [   1:0] radio_rx_running,
+  output wire [  63:0] radio_tx_data,
+  input  wire [   1:0] radio_tx_stb,
+  output wire [   1:0] radio_tx_running,
+
+  // Transport Adapters ///////////////
+
+  // Transport 0 (dma)
+  input  wire [CHDR_W-1:0] s_dma_tdata,
+  input  wire              s_dma_tlast,
+  input  wire              s_dma_tvalid,
+  output wire              s_dma_tready,
+  output wire [CHDR_W-1:0] m_dma_tdata,
+  output wire              m_dma_tlast,
+  output wire              m_dma_tvalid,
+  input  wire              m_dma_tready
 );
 
-  localparam CHDR_W = 64;
-  localparam MTU    = 10;
   localparam EDGE_TBL_FILE = `"`RFNOC_EDGE_TBL_FILE`";
 
   wire rfnoc_chdr_clk, rfnoc_chdr_rst;
   wire rfnoc_ctrl_clk, rfnoc_ctrl_rst;
 
-  // ----------------------------------------------------
+
+  //---------------------------------------------------------------------------
   // CHDR Crossbar
-  // ----------------------------------------------------
+  //---------------------------------------------------------------------------
+
   wire [CHDR_W-1:0] xb_to_ep0_tdata ;
   wire              xb_to_ep0_tlast ;
   wire              xb_to_ep0_tvalid;
@@ -95,12 +113,12 @@ module rfnoc_image_core #(
     .clk            (rfnoc_chdr_clk),
     .reset          (rfnoc_chdr_rst),
     .device_id      (device_id),
-    .s_axis_tdata   ({ep1_to_xb_tdata, ep0_to_xb_tdata, s_dma_tdata}),
-    .s_axis_tlast   ({ep1_to_xb_tlast, ep0_to_xb_tlast, s_dma_tlast}),
+    .s_axis_tdata   ({ep1_to_xb_tdata , ep0_to_xb_tdata , s_dma_tdata }),
+    .s_axis_tlast   ({ep1_to_xb_tlast , ep0_to_xb_tlast , s_dma_tlast }),
     .s_axis_tvalid  ({ep1_to_xb_tvalid, ep0_to_xb_tvalid, s_dma_tvalid}),
     .s_axis_tready  ({ep1_to_xb_tready, ep0_to_xb_tready, s_dma_tready}),
-    .m_axis_tdata   ({xb_to_ep1_tdata, xb_to_ep0_tdata, m_dma_tdata}),
-    .m_axis_tlast   ({xb_to_ep1_tlast, xb_to_ep0_tlast, m_dma_tlast}),
+    .m_axis_tdata   ({xb_to_ep1_tdata , xb_to_ep0_tdata , m_dma_tdata }),
+    .m_axis_tlast   ({xb_to_ep1_tlast , xb_to_ep0_tlast , m_dma_tlast }),
     .m_axis_tvalid  ({xb_to_ep1_tvalid, xb_to_ep0_tvalid, m_dma_tvalid}),
     .m_axis_tready  ({xb_to_ep1_tready, xb_to_ep0_tready, m_dma_tready}),
     .ext_rtcfg_stb  (1'h0),
@@ -109,9 +127,18 @@ module rfnoc_image_core #(
     .ext_rtcfg_ack  ()
   );
 
-  // ----------------------------------------------------
+
+  //---------------------------------------------------------------------------
   // Stream Endpoints
-  // ----------------------------------------------------
+  //---------------------------------------------------------------------------
+
+  // If requested buffer size is 0, use the minimum SRL-based FIFO size.
+  // Otherwise, make sure it's at least two MTU-sized packets.
+  localparam REQ_BUFF_SIZE_EP0 = 16384;
+  localparam INGRESS_BUFF_SIZE_EP0 =
+    REQ_BUFF_SIZE_EP0 == 0         ? 5     :
+    REQ_BUFF_SIZE_EP0 < 2*(2**MTU) ? MTU+1 :
+    $clog2(REQ_BUFF_SIZE_EP0);
 
   wire [CHDR_W-1:0] m_ep0_out0_tdata;
   wire              m_ep0_out0_tlast;
@@ -121,8 +148,8 @@ module rfnoc_image_core #(
   wire              s_ep0_in0_tlast;
   wire              s_ep0_in0_tvalid;
   wire              s_ep0_in0_tready;
-  wire [31:0]       m_ep0_ctrl_tdata , s_ep0_ctrl_tdata ;
-  wire              m_ep0_ctrl_tlast , s_ep0_ctrl_tlast ;
+  wire [      31:0] m_ep0_ctrl_tdata,  s_ep0_ctrl_tdata;
+  wire              m_ep0_ctrl_tlast,  s_ep0_ctrl_tlast;
   wire              m_ep0_ctrl_tvalid, s_ep0_ctrl_tvalid;
   wire              m_ep0_ctrl_tready, s_ep0_ctrl_tready;
 
@@ -135,23 +162,23 @@ module rfnoc_image_core #(
     .NUM_DATA_O         (1),
     .INST_NUM           (0),
     .CTRL_XBAR_PORT     (1),
-    .INGRESS_BUFF_SIZE  (14),
+    .INGRESS_BUFF_SIZE  (INGRESS_BUFF_SIZE_EP0),
     .MTU                (MTU),
     .REPORT_STRM_ERRS   (1)
   ) ep0_i (
-    .rfnoc_chdr_clk     (rfnoc_chdr_clk    ),
-    .rfnoc_chdr_rst     (rfnoc_chdr_rst    ),
-    .rfnoc_ctrl_clk     (rfnoc_ctrl_clk    ),
-    .rfnoc_ctrl_rst     (rfnoc_ctrl_rst    ),
-    .device_id          (device_id         ),
-    .s_axis_chdr_tdata  (xb_to_ep0_tdata  ),
-    .s_axis_chdr_tlast  (xb_to_ep0_tlast  ),
-    .s_axis_chdr_tvalid (xb_to_ep0_tvalid ),
-    .s_axis_chdr_tready (xb_to_ep0_tready ),
-    .m_axis_chdr_tdata  (ep0_to_xb_tdata  ),
-    .m_axis_chdr_tlast  (ep0_to_xb_tlast  ),
-    .m_axis_chdr_tvalid (ep0_to_xb_tvalid ),
-    .m_axis_chdr_tready (ep0_to_xb_tready ),
+    .rfnoc_chdr_clk     (rfnoc_chdr_clk),
+    .rfnoc_chdr_rst     (rfnoc_chdr_rst),
+    .rfnoc_ctrl_clk     (rfnoc_ctrl_clk),
+    .rfnoc_ctrl_rst     (rfnoc_ctrl_rst),
+    .device_id          (device_id),
+    .s_axis_chdr_tdata  (xb_to_ep0_tdata),
+    .s_axis_chdr_tlast  (xb_to_ep0_tlast),
+    .s_axis_chdr_tvalid (xb_to_ep0_tvalid),
+    .s_axis_chdr_tready (xb_to_ep0_tready),
+    .m_axis_chdr_tdata  (ep0_to_xb_tdata),
+    .m_axis_chdr_tlast  (ep0_to_xb_tlast),
+    .m_axis_chdr_tvalid (ep0_to_xb_tvalid),
+    .m_axis_chdr_tready (ep0_to_xb_tready),
     .s_axis_data_tdata  ({s_ep0_in0_tdata}),
     .s_axis_data_tlast  ({s_ep0_in0_tlast}),
     .s_axis_data_tvalid ({s_ep0_in0_tvalid}),
@@ -160,20 +187,28 @@ module rfnoc_image_core #(
     .m_axis_data_tlast  ({m_ep0_out0_tlast}),
     .m_axis_data_tvalid ({m_ep0_out0_tvalid}),
     .m_axis_data_tready ({m_ep0_out0_tready}),
-    .s_axis_ctrl_tdata  (s_ep0_ctrl_tdata ),
-    .s_axis_ctrl_tlast  (s_ep0_ctrl_tlast ),
+    .s_axis_ctrl_tdata  (s_ep0_ctrl_tdata),
+    .s_axis_ctrl_tlast  (s_ep0_ctrl_tlast),
     .s_axis_ctrl_tvalid (s_ep0_ctrl_tvalid),
     .s_axis_ctrl_tready (s_ep0_ctrl_tready),
-    .m_axis_ctrl_tdata  (m_ep0_ctrl_tdata ),
-    .m_axis_ctrl_tlast  (m_ep0_ctrl_tlast ),
+    .m_axis_ctrl_tdata  (m_ep0_ctrl_tdata),
+    .m_axis_ctrl_tlast  (m_ep0_ctrl_tlast),
     .m_axis_ctrl_tvalid (m_ep0_ctrl_tvalid),
     .m_axis_ctrl_tready (m_ep0_ctrl_tready),
-    .strm_seq_err_stb   (                  ),
-    .strm_data_err_stb  (                  ),
-    .strm_route_err_stb (                  ),
-    .signal_data_err    (1'b0              )
+    .strm_seq_err_stb   (),
+    .strm_data_err_stb  (),
+    .strm_route_err_stb (),
+    .signal_data_err    (1'b0)
   );
 
+  // If requested buffer size is 0, use the minimum SRL-based FIFO size.
+  // Otherwise, make sure it's at least two MTU-sized packets.
+  localparam REQ_BUFF_SIZE_EP1 = 16384;
+  localparam INGRESS_BUFF_SIZE_EP1 =
+    REQ_BUFF_SIZE_EP1 == 0         ? 5     :
+    REQ_BUFF_SIZE_EP1 < 2*(2**MTU) ? MTU+1 :
+    $clog2(REQ_BUFF_SIZE_EP1);
+
   wire [CHDR_W-1:0] m_ep1_out0_tdata;
   wire              m_ep1_out0_tlast;
   wire              m_ep1_out0_tvalid;
@@ -182,8 +217,8 @@ module rfnoc_image_core #(
   wire              s_ep1_in0_tlast;
   wire              s_ep1_in0_tvalid;
   wire              s_ep1_in0_tready;
-  wire [31:0]       m_ep1_ctrl_tdata , s_ep1_ctrl_tdata ;
-  wire              m_ep1_ctrl_tlast , s_ep1_ctrl_tlast ;
+  wire [      31:0] m_ep1_ctrl_tdata,  s_ep1_ctrl_tdata;
+  wire              m_ep1_ctrl_tlast,  s_ep1_ctrl_tlast;
   wire              m_ep1_ctrl_tvalid, s_ep1_ctrl_tvalid;
   wire              m_ep1_ctrl_tready, s_ep1_ctrl_tready;
 
@@ -196,23 +231,23 @@ module rfnoc_image_core #(
     .NUM_DATA_O         (1),
     .INST_NUM           (1),
     .CTRL_XBAR_PORT     (2),
-    .INGRESS_BUFF_SIZE  (14),
+    .INGRESS_BUFF_SIZE  (INGRESS_BUFF_SIZE_EP1),
     .MTU                (MTU),
     .REPORT_STRM_ERRS   (1)
   ) ep1_i (
-    .rfnoc_chdr_clk     (rfnoc_chdr_clk    ),
-    .rfnoc_chdr_rst     (rfnoc_chdr_rst    ),
-    .rfnoc_ctrl_clk     (rfnoc_ctrl_clk    ),
-    .rfnoc_ctrl_rst     (rfnoc_ctrl_rst    ),
-    .device_id          (device_id         ),
-    .s_axis_chdr_tdata  (xb_to_ep1_tdata  ),
-    .s_axis_chdr_tlast  (xb_to_ep1_tlast  ),
-    .s_axis_chdr_tvalid (xb_to_ep1_tvalid ),
-    .s_axis_chdr_tready (xb_to_ep1_tready ),
-    .m_axis_chdr_tdata  (ep1_to_xb_tdata  ),
-    .m_axis_chdr_tlast  (ep1_to_xb_tlast  ),
-    .m_axis_chdr_tvalid (ep1_to_xb_tvalid ),
-    .m_axis_chdr_tready (ep1_to_xb_tready ),
+    .rfnoc_chdr_clk     (rfnoc_chdr_clk),
+    .rfnoc_chdr_rst     (rfnoc_chdr_rst),
+    .rfnoc_ctrl_clk     (rfnoc_ctrl_clk),
+    .rfnoc_ctrl_rst     (rfnoc_ctrl_rst),
+    .device_id          (device_id),
+    .s_axis_chdr_tdata  (xb_to_ep1_tdata),
+    .s_axis_chdr_tlast  (xb_to_ep1_tlast),
+    .s_axis_chdr_tvalid (xb_to_ep1_tvalid),
+    .s_axis_chdr_tready (xb_to_ep1_tready),
+    .m_axis_chdr_tdata  (ep1_to_xb_tdata),
+    .m_axis_chdr_tlast  (ep1_to_xb_tlast),
+    .m_axis_chdr_tvalid (ep1_to_xb_tvalid),
+    .m_axis_chdr_tready (ep1_to_xb_tready),
     .s_axis_data_tdata  ({s_ep1_in0_tdata}),
     .s_axis_data_tlast  ({s_ep1_in0_tlast}),
     .s_axis_data_tvalid ({s_ep1_in0_tvalid}),
@@ -221,34 +256,33 @@ module rfnoc_image_core #(
     .m_axis_data_tlast  ({m_ep1_out0_tlast}),
     .m_axis_data_tvalid ({m_ep1_out0_tvalid}),
     .m_axis_data_tready ({m_ep1_out0_tready}),
-    .s_axis_ctrl_tdata  (s_ep1_ctrl_tdata ),
-    .s_axis_ctrl_tlast  (s_ep1_ctrl_tlast ),
+    .s_axis_ctrl_tdata  (s_ep1_ctrl_tdata),
+    .s_axis_ctrl_tlast  (s_ep1_ctrl_tlast),
     .s_axis_ctrl_tvalid (s_ep1_ctrl_tvalid),
     .s_axis_ctrl_tready (s_ep1_ctrl_tready),
-    .m_axis_ctrl_tdata  (m_ep1_ctrl_tdata ),
-    .m_axis_ctrl_tlast  (m_ep1_ctrl_tlast ),
+    .m_axis_ctrl_tdata  (m_ep1_ctrl_tdata),
+    .m_axis_ctrl_tlast  (m_ep1_ctrl_tlast),
     .m_axis_ctrl_tvalid (m_ep1_ctrl_tvalid),
     .m_axis_ctrl_tready (m_ep1_ctrl_tready),
-    .strm_seq_err_stb   (                  ),
-    .strm_data_err_stb  (                  ),
-    .strm_route_err_stb (                  ),
-    .signal_data_err    (1'b0              )
+    .strm_seq_err_stb   (),
+    .strm_data_err_stb  (),
+    .strm_route_err_stb (),
+    .signal_data_err    (1'b0)
   );
 
 
-
-  // ----------------------------------------------------
+  //---------------------------------------------------------------------------
   // Control Crossbar
-  // ----------------------------------------------------
+  //---------------------------------------------------------------------------
 
-  wire [31:0]       m_core_ctrl_tdata , s_core_ctrl_tdata ;
-  wire              m_core_ctrl_tlast , s_core_ctrl_tlast ;
-  wire              m_core_ctrl_tvalid, s_core_ctrl_tvalid;
-  wire              m_core_ctrl_tready, s_core_ctrl_tready;
-  wire [31:0]       m_radio0_ctrl_tdata ,   s_radio0_ctrl_tdata ;
-  wire              m_radio0_ctrl_tlast ,   s_radio0_ctrl_tlast ;
-  wire              m_radio0_ctrl_tvalid,   s_radio0_ctrl_tvalid;
-  wire              m_radio0_ctrl_tready,   s_radio0_ctrl_tready;
+  wire [31:0] m_core_ctrl_tdata,  s_core_ctrl_tdata;
+  wire        m_core_ctrl_tlast,  s_core_ctrl_tlast;
+  wire        m_core_ctrl_tvalid, s_core_ctrl_tvalid;
+  wire        m_core_ctrl_tready, s_core_ctrl_tready;
+  wire [31:0] m_radio0_ctrl_tdata,  s_radio0_ctrl_tdata;
+  wire        m_radio0_ctrl_tlast,  s_radio0_ctrl_tlast;
+  wire        m_radio0_ctrl_tvalid, s_radio0_ctrl_tvalid;
+  wire        m_radio0_ctrl_tready, s_radio0_ctrl_tready;
 
   axis_ctrl_crossbar_nxn #(
     .WIDTH            (32),
@@ -272,9 +306,11 @@ module rfnoc_image_core #(
     .deadlock_detected()
   );
 
-  // ----------------------------------------------------
+
+  //---------------------------------------------------------------------------
   // RFNoC Core Kernel
-  // ----------------------------------------------------
+  //---------------------------------------------------------------------------
+
   wire [(512*1)-1:0] rfnoc_core_config, rfnoc_core_status;
 
   rfnoc_core_kernel #(
@@ -299,12 +335,12 @@ module rfnoc_image_core #(
     .core_chdr_rst      (rfnoc_chdr_rst),
     .core_ctrl_clk      (rfnoc_ctrl_clk),
     .core_ctrl_rst      (rfnoc_ctrl_rst),
-    .s_axis_ctrl_tdata  (s_core_ctrl_tdata ),
-    .s_axis_ctrl_tlast  (s_core_ctrl_tlast ),
+    .s_axis_ctrl_tdata  (s_core_ctrl_tdata),
+    .s_axis_ctrl_tlast  (s_core_ctrl_tlast),
     .s_axis_ctrl_tvalid (s_core_ctrl_tvalid),
     .s_axis_ctrl_tready (s_core_ctrl_tready),
-    .m_axis_ctrl_tdata  (m_core_ctrl_tdata ),
-    .m_axis_ctrl_tlast  (m_core_ctrl_tlast ),
+    .m_axis_ctrl_tdata  (m_core_ctrl_tdata),
+    .m_axis_ctrl_tlast  (m_core_ctrl_tlast),
     .m_axis_ctrl_tvalid (m_core_ctrl_tvalid),
     .m_axis_ctrl_tready (m_core_ctrl_tready),
     .device_id          (device_id),
@@ -312,13 +348,15 @@ module rfnoc_image_core #(
     .rfnoc_core_status  (rfnoc_core_status)
   );
 
-  // ----------------------------------------------------
+
+  //---------------------------------------------------------------------------
   // Blocks
-  // ----------------------------------------------------
+  //---------------------------------------------------------------------------
 
-  // ----------------------------------------------------
+  //-----------------------------------
   // radio0
-  // ----------------------------------------------------
+  //-----------------------------------
+
   wire              radio0_radio_clk;
   wire [CHDR_W-1:0] s_radio0_in_1_tdata , s_radio0_in_0_tdata ;
   wire              s_radio0_in_1_tlast , s_radio0_in_0_tlast ;
@@ -329,113 +367,115 @@ module rfnoc_image_core #(
   wire              m_radio0_out_1_tvalid, m_radio0_out_0_tvalid;
   wire              m_radio0_out_1_tready, m_radio0_out_0_tready;
 
-  //  ctrl_port
-  wire [  1-1:0] radio0_m_ctrlport_req_wr;
-  wire [  1-1:0] radio0_m_ctrlport_req_rd;
-  wire [ 20-1:0] radio0_m_ctrlport_req_addr;
-  wire [ 32-1:0] radio0_m_ctrlport_req_data;
-  wire [  4-1:0] radio0_m_ctrlport_req_byte_en;
-  wire [  1-1:0] radio0_m_ctrlport_req_has_time;
-  wire [ 64-1:0] radio0_m_ctrlport_req_time;
-  wire [  1-1:0] radio0_m_ctrlport_resp_ack;
-  wire [  2-1:0] radio0_m_ctrlport_resp_status;
-  wire [ 32-1:0] radio0_m_ctrlport_resp_data;
-  //  time_keeper
-  wire [ 64-1:0] radio0_radio_time;
-  //  x300_radio
-  wire [ 64-1:0] radio0_radio_rx_data;
-  wire [  2-1:0] radio0_radio_rx_stb;
-  wire [  2-1:0] radio0_radio_rx_running;
-  wire [ 64-1:0] radio0_radio_tx_data;
-  wire [  2-1:0] radio0_radio_tx_stb;
-  wire [  2-1:0] radio0_radio_tx_running;
+  // ctrl_port
+  wire [   0:0] radio0_m_ctrlport_req_wr;
+  wire [   0:0] radio0_m_ctrlport_req_rd;
+  wire [  19:0] radio0_m_ctrlport_req_addr;
+  wire [  31:0] radio0_m_ctrlport_req_data;
+  wire [   3:0] radio0_m_ctrlport_req_byte_en;
+  wire [   0:0] radio0_m_ctrlport_req_has_time;
+  wire [  63:0] radio0_m_ctrlport_req_time;
+  wire [   0:0] radio0_m_ctrlport_resp_ack;
+  wire [   1:0] radio0_m_ctrlport_resp_status;
+  wire [  31:0] radio0_m_ctrlport_resp_data;
+  // time_keeper
+  wire [  63:0] radio0_radio_time;
+  // x300_radio
+  wire [  63:0] radio0_radio_rx_data;
+  wire [   1:0] radio0_radio_rx_stb;
+  wire [   1:0] radio0_radio_rx_running;
+  wire [  63:0] radio0_radio_tx_data;
+  wire [   1:0] radio0_radio_tx_stb;
+  wire [   1:0] radio0_radio_tx_running;
 
   rfnoc_block_radio #(
-    .THIS_PORTID(2),
-    .CHDR_W(CHDR_W),
-    .NUM_PORTS(2),
-    .MTU(MTU)
+    .THIS_PORTID         (2),
+    .CHDR_W              (CHDR_W),
+    .NUM_PORTS           (2),
+    .MTU                 (MTU)
   ) b_radio0_0 (
-    .rfnoc_chdr_clk     (rfnoc_chdr_clk),
-    .rfnoc_ctrl_clk     (rfnoc_ctrl_clk),
-    .radio_clk(radio0_radio_clk),
-    .rfnoc_core_config  (rfnoc_core_config[512*1-1:512*0]),
-    .rfnoc_core_status  (rfnoc_core_status[512*1-1:512*0]),
-
-    .m_ctrlport_req_wr(radio0_m_ctrlport_req_wr),
-    .m_ctrlport_req_rd(radio0_m_ctrlport_req_rd),
-    .m_ctrlport_req_addr(radio0_m_ctrlport_req_addr),
-    .m_ctrlport_req_data(radio0_m_ctrlport_req_data),
+    .rfnoc_chdr_clk      (rfnoc_chdr_clk),
+    .rfnoc_ctrl_clk      (rfnoc_ctrl_clk),
+    .radio_clk           (radio0_radio_clk),
+    .rfnoc_core_config   (rfnoc_core_config[512*1-1:512*0]),
+    .rfnoc_core_status   (rfnoc_core_status[512*1-1:512*0]),
+    .m_ctrlport_req_wr   (radio0_m_ctrlport_req_wr),
+    .m_ctrlport_req_rd   (radio0_m_ctrlport_req_rd),
+    .m_ctrlport_req_addr (radio0_m_ctrlport_req_addr),
+    .m_ctrlport_req_data (radio0_m_ctrlport_req_data),
     .m_ctrlport_req_byte_en(radio0_m_ctrlport_req_byte_en),
     .m_ctrlport_req_has_time(radio0_m_ctrlport_req_has_time),
-    .m_ctrlport_req_time(radio0_m_ctrlport_req_time),
-    .m_ctrlport_resp_ack(radio0_m_ctrlport_resp_ack),
+    .m_ctrlport_req_time (radio0_m_ctrlport_req_time),
+    .m_ctrlport_resp_ack (radio0_m_ctrlport_resp_ack),
     .m_ctrlport_resp_status(radio0_m_ctrlport_resp_status),
     .m_ctrlport_resp_data(radio0_m_ctrlport_resp_data),
-    .radio_time(radio0_radio_time),
-    .radio_rx_data(radio0_radio_rx_data),
-    .radio_rx_stb(radio0_radio_rx_stb),
-    .radio_rx_running(radio0_radio_rx_running),
-    .radio_tx_data(radio0_radio_tx_data),
-    .radio_tx_stb(radio0_radio_tx_stb),
-    .radio_tx_running(radio0_radio_tx_running),
-
-    .s_rfnoc_chdr_tdata ({s_radio0_in_1_tdata , s_radio0_in_0_tdata }),
-    .s_rfnoc_chdr_tlast ({s_radio0_in_1_tlast , s_radio0_in_0_tlast }),
-    .s_rfnoc_chdr_tvalid({s_radio0_in_1_tvalid, s_radio0_in_0_tvalid}),
-    .s_rfnoc_chdr_tready({s_radio0_in_1_tready, s_radio0_in_0_tready}),
-    .m_rfnoc_chdr_tdata ({m_radio0_out_1_tdata , m_radio0_out_0_tdata }),
-    .m_rfnoc_chdr_tlast ({m_radio0_out_1_tlast , m_radio0_out_0_tlast }),
-    .m_rfnoc_chdr_tvalid({m_radio0_out_1_tvalid, m_radio0_out_0_tvalid}),
-    .m_rfnoc_chdr_tready({m_radio0_out_1_tready, m_radio0_out_0_tready}),
-    .s_rfnoc_ctrl_tdata (s_radio0_ctrl_tdata ),
-    .s_rfnoc_ctrl_tlast (s_radio0_ctrl_tlast ),
-    .s_rfnoc_ctrl_tvalid(s_radio0_ctrl_tvalid),
-    .s_rfnoc_ctrl_tready(s_radio0_ctrl_tready),
-    .m_rfnoc_ctrl_tdata (m_radio0_ctrl_tdata ),
-    .m_rfnoc_ctrl_tlast (m_radio0_ctrl_tlast ),
-    .m_rfnoc_ctrl_tvalid(m_radio0_ctrl_tvalid),
-    .m_rfnoc_ctrl_tready(m_radio0_ctrl_tready)
+    .radio_time          (radio0_radio_time),
+    .radio_rx_data       (radio0_radio_rx_data),
+    .radio_rx_stb        (radio0_radio_rx_stb),
+    .radio_rx_running    (radio0_radio_rx_running),
+    .radio_tx_data       (radio0_radio_tx_data),
+    .radio_tx_stb        (radio0_radio_tx_stb),
+    .radio_tx_running    (radio0_radio_tx_running),
+    .s_rfnoc_chdr_tdata  ({s_radio0_in_1_tdata , s_radio0_in_0_tdata }),
+    .s_rfnoc_chdr_tlast  ({s_radio0_in_1_tlast , s_radio0_in_0_tlast }),
+    .s_rfnoc_chdr_tvalid ({s_radio0_in_1_tvalid, s_radio0_in_0_tvalid}),
+    .s_rfnoc_chdr_tready ({s_radio0_in_1_tready, s_radio0_in_0_tready}),
+    .m_rfnoc_chdr_tdata  ({m_radio0_out_1_tdata , m_radio0_out_0_tdata }),
+    .m_rfnoc_chdr_tlast  ({m_radio0_out_1_tlast , m_radio0_out_0_tlast }),
+    .m_rfnoc_chdr_tvalid ({m_radio0_out_1_tvalid, m_radio0_out_0_tvalid}),
+    .m_rfnoc_chdr_tready ({m_radio0_out_1_tready, m_radio0_out_0_tready}),
+    .s_rfnoc_ctrl_tdata  (s_radio0_ctrl_tdata),
+    .s_rfnoc_ctrl_tlast  (s_radio0_ctrl_tlast),
+    .s_rfnoc_ctrl_tvalid (s_radio0_ctrl_tvalid),
+    .s_rfnoc_ctrl_tready (s_radio0_ctrl_tready),
+    .m_rfnoc_ctrl_tdata  (m_radio0_ctrl_tdata),
+    .m_rfnoc_ctrl_tlast  (m_radio0_ctrl_tlast),
+    .m_rfnoc_ctrl_tvalid (m_radio0_ctrl_tvalid),
+    .m_rfnoc_ctrl_tready (m_radio0_ctrl_tready)
   );
 
-
-  // ----------------------------------------------------
+  //---------------------------------------------------------------------------
   // Static Router
-  // ----------------------------------------------------
-  assign s_radio0_in_0_tdata = m_ep0_out0_tdata ;
-  assign s_radio0_in_0_tlast = m_ep0_out0_tlast ;
+  //---------------------------------------------------------------------------
+
+  assign s_radio0_in_0_tdata = m_ep0_out0_tdata;
+  assign s_radio0_in_0_tlast = m_ep0_out0_tlast;
   assign s_radio0_in_0_tvalid = m_ep0_out0_tvalid;
   assign m_ep0_out0_tready = s_radio0_in_0_tready;
 
-  assign s_radio0_in_1_tdata = m_ep1_out0_tdata ;
-  assign s_radio0_in_1_tlast = m_ep1_out0_tlast ;
+  assign s_radio0_in_1_tdata = m_ep1_out0_tdata;
+  assign s_radio0_in_1_tlast = m_ep1_out0_tlast;
   assign s_radio0_in_1_tvalid = m_ep1_out0_tvalid;
   assign m_ep1_out0_tready = s_radio0_in_1_tready;
 
-  assign s_ep0_in0_tdata = m_radio0_out_0_tdata ;
-  assign s_ep0_in0_tlast = m_radio0_out_0_tlast ;
+  assign s_ep0_in0_tdata = m_radio0_out_0_tdata;
+  assign s_ep0_in0_tlast = m_radio0_out_0_tlast;
   assign s_ep0_in0_tvalid = m_radio0_out_0_tvalid;
   assign m_radio0_out_0_tready = s_ep0_in0_tready;
 
-  assign s_ep1_in0_tdata = m_radio0_out_1_tdata ;
-  assign s_ep1_in0_tlast = m_radio0_out_1_tlast ;
+  assign s_ep1_in0_tdata = m_radio0_out_1_tdata;
+  assign s_ep1_in0_tlast = m_radio0_out_1_tlast;
   assign s_ep1_in0_tvalid = m_radio0_out_1_tvalid;
   assign m_radio0_out_1_tready = s_ep1_in0_tready;
 
 
-  // ----------------------------------------------------
+  //---------------------------------------------------------------------------
   // Unused Ports
-  // ----------------------------------------------------
+  //---------------------------------------------------------------------------
+
+
 
-  // ----------------------------------------------------
+  //---------------------------------------------------------------------------
   // Clock Domains
-  // ----------------------------------------------------
+  //---------------------------------------------------------------------------
+
   assign radio0_radio_clk = radio_clk;
 
 
-  // ----------------------------------------------------
+  //---------------------------------------------------------------------------
   // IO Port Connection
-  // ----------------------------------------------------
+  //---------------------------------------------------------------------------
+
   // Master/Slave Connections:
   assign m_ctrlport_req_wr = radio0_m_ctrlport_req_wr;
   assign m_ctrlport_req_rd = radio0_m_ctrlport_req_rd;
@@ -459,3 +499,6 @@ module rfnoc_image_core #(
   assign radio0_radio_time = radio_time;
 
 endmodule
+
+
+`default_nettype wire
diff --git a/fpga/usrp3/top/e31x/e310_rfnoc_image_core.vh b/fpga/usrp3/top/e31x/e310_rfnoc_image_core.vh
new file mode 100644
index 000000000..83ff8378c
--- /dev/null
+++ b/fpga/usrp3/top/e31x/e310_rfnoc_image_core.vh
@@ -0,0 +1,21 @@
+//
+// Copyright 2021 Ettus Research, A National Instruments Brand
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+// Header: rfnoc_image_core.vh (for e31x)
+//
+// Description:
+//
+//   This is the header file for the RFNoC Image Core.
+//
+//   This file was automatically generated by the RFNoC image builder tool.
+//   Re-running that tool will overwrite this file!
+//
+// File generated on: 2021-05-03T08:51:11.441866
+// Source: e310_rfnoc_image_core.yml
+// Source SHA256: 7fef622f1ae280dd7573abd823c7a6bbecf51921a74cea948e6bfb9f8f65e2cc
+//
+
+`define CHDR_WIDTH     64
+`define RFNOC_PROTOVER { 8'd1, 8'd0 }
diff --git a/fpga/usrp3/top/e31x/e310_rfnoc_image_core.yml b/fpga/usrp3/top/e31x/e310_rfnoc_image_core.yml
index f23dfa152..9ce36c66b 100644
--- a/fpga/usrp3/top/e31x/e310_rfnoc_image_core.yml
+++ b/fpga/usrp3/top/e31x/e310_rfnoc_image_core.yml
@@ -6,7 +6,8 @@ license: 'SPDX-License-Identifier: LGPL-3.0-or-later' # License information used
 version: '1.0'                          # File version
 rfnoc_version: '1.0'                    # RFNoC protocol version
 chdr_width: 64                          # Bit width of the CHDR bus for this image
-device: 'e310'
+device: 'e310'                          # USRP type
+image_core_name: 'e310'                 # Name to use for the RFNoC Image Core files
 default_target: 'E310_SG3'
 
 # A list of all stream endpoints in design