fpga: e31x: Add DRAM support

This adds DRAM support to E31x devices. Due to the size of the DDR3
memory controller, it is not enabled by default. You can include the
memory controller IP in the build by adding the DRAM environment
variable to your build. For example:

DRAM=1 make E310_SG3

8 files changed, 775 insertions, 40 deletions

diff --git a/fpga/usrp3/top/e31x/ip/Makefile.inc b/fpga/usrp3/top/e31x/ip/Makefile.inc
index 76bec9cdd..f2ddd05f2 100644
--- a/fpga/usrp3/top/e31x/ip/Makefile.inc
+++ b/fpga/usrp3/top/e31x/ip/Makefile.inc
@@ -16,10 +16,11 @@ include $(IP_DIR)/fifo_short_2clk/Makefile.inc
 #include $(IP_DIR)/axi4_to_axi3_protocol_converter_32/Makefile.inc
 #include $(IP_DIR)/axi4_to_axi3_protocol_converter_64/Makefile.inc
 include $(IP_DIR)/e31x_ps_bd/Makefile.inc
-include $(IP_DIR)/mig_7series_0/Makefile.inc
+include $(IP_DIR)/ddr3_16bit/Makefile.inc
+include $(IP_DIR)/axi_inter_2x64_128_bd/Makefile.inc
 
 BD_SRCS = \
-$(IP_AXI_INTERCON_4X64_256_BD_SRCS) \
+$(IP_AXI_INTER_2X64_128_BD_SRCS) \
 $(IP_E31X_PS_BD_SRCS)
 
 IP_XCI_SRCS = \
@@ -36,7 +37,7 @@ $(IP_FIFO_4K_2CLK_SRCS) \
 #$(IP_MISC_CLOCK_GEN_SRCS) \
 
 IP_DRAM_XCI_SRCS = \
-$(IP_DDR3_32BIT_SRCS)
+$(IP_DDR3_16BIT_SRCS)
 
 ## Currently unused
 ## $(IP_INPUT_SAMPLE_FIFO_SRCS) \
@@ -55,7 +56,7 @@ $(IP_MIG_7SERIES_0_OUTS) \
 #$(IP_AXIS_FIFO_TO_AXI4LITE_OUTS) \
 
 BD_OUTPUTS = \
-$(IP_AXI_INTERCON_4X64_256_BD_OUTS) \
+$(IP_AXI_INTER_2X64_128_BD_OUTS) \
 $(IP_E31X_PS_BD_OUTS)
 
 # Currently unused
diff --git a/fpga/usrp3/top/e31x/ip/axi_inter_2x64_128_bd/Makefile.inc b/fpga/usrp3/top/e31x/ip/axi_inter_2x64_128_bd/Makefile.inc
new file mode 100644
index 000000000..bc8038e68
--- /dev/null
+++ b/fpga/usrp3/top/e31x/ip/axi_inter_2x64_128_bd/Makefile.inc
@@ -0,0 +1,26 @@
+#
+# Copyright 2022 Ettus Research, a National Instruments Brand
+#
+# SPDX-License-Identifier: LGPL-3.0-or-later
+#
+
+IP_AXI_INTER_2X64_128_ORIG_SRCS = $(addprefix $(IP_DIR)/axi_inter_2x64_128_bd/, \
+axi_inter_2x64_128_bd.tcl \
+)
+
+IP_AXI_INTER_2X64_128_BDTCL_SRCS = $(addprefix $(IP_BUILD_DIR)/axi_inter_2x64_128_bd/, \
+axi_inter_2x64_128_bd.tcl \
+)
+
+IP_AXI_INTER_2X64_128_BD_SRCS = $(addprefix $(IP_BUILD_DIR)/axi_inter_2x64_128_bd/, \
+axi_inter_2x64_128_bd/axi_inter_2x64_128_bd.bd \
+)
+
+BD_AXI_INTER_2X64_128_BD_OUTS = $(addprefix $(IP_BUILD_DIR)/axi_inter_2x64_128_bd/, \
+axi_inter_2x64_128_bd.bd.out \
+axi_inter_2x64_128_bd/axi_inter_2x64_128_bd_ooc.xdc \
+axi_inter_2x64_128_bd/synth/axi_inter_2x64_128_bd.v \
+)
+
+$(IP_AXI_INTER_2X64_128_BD_SRCS) $(BD_AXI_INTER_2X64_128_BD_OUTS) $(IP_AXI_INTER_2X64_128_BDTCL_SRCS): $(IP_AXI_INTER_2X64_128_ORIG_SRCS)
+	$(call BUILD_VIVADO_BDTCL,axi_inter_2x64_128_bd,$(ARCH),$(PART_ID),$(IP_DIR),$(IP_BUILD_DIR),$(LIB_DIR)/vivado_ipi)
diff --git a/fpga/usrp3/top/e31x/ip/axi_inter_2x64_128_bd/axi_inter_2x64_128_bd.tcl b/fpga/usrp3/top/e31x/ip/axi_inter_2x64_128_bd/axi_inter_2x64_128_bd.tcl
new file mode 100644
index 000000000..e0eb550d1
--- /dev/null
+++ b/fpga/usrp3/top/e31x/ip/axi_inter_2x64_128_bd/axi_inter_2x64_128_bd.tcl
@@ -0,0 +1,707 @@
+
+################################################################
+# This is a generated script based on design: axi_inter_2x64_128_bd
+#
+# Though there are limitations about the generated script,
+# the main purpose of this utility is to make learning
+# IP Integrator Tcl commands easier.
+################################################################
+
+namespace eval _tcl {
+proc get_script_folder {} {
+   set script_path [file normalize [info script]]
+   set script_folder [file dirname $script_path]
+   return $script_folder
+}
+}
+variable script_folder
+set script_folder [_tcl::get_script_folder]
+
+################################################################
+# Check if script is running in correct Vivado version.
+################################################################
+set scripts_vivado_version 2019.1
+set current_vivado_version [version -short]
+
+if { [string first $scripts_vivado_version $current_vivado_version] == -1 } {
+   puts ""
+   catch {common::send_msg_id "BD_TCL-109" "ERROR" "This script was generated using Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Please run the script in Vivado <$scripts_vivado_version> then open the design in Vivado <$current_vivado_version>. Upgrade the design by running \"Tools => Report => Report IP Status...\", then run write_bd_tcl to create an updated script."}
+
+   return 1
+}
+
+################################################################
+# START
+################################################################
+
+# To test this script, run the following commands from Vivado Tcl console:
+# source axi_inter_2x64_128_bd_script.tcl
+
+# If there is no project opened, this script will create a
+# project, but make sure you do not have an existing project
+# <./myproj/project_1.xpr> in the current working folder.
+
+set list_projs [get_projects -quiet]
+if { $list_projs eq "" } {
+   create_project project_1 myproj -part xc7z020clg484-3
+}
+
+
+# CHANGE DESIGN NAME HERE
+variable design_name
+set design_name axi_inter_2x64_128_bd
+
+# If you do not already have an existing IP Integrator design open,
+# you can create a design using the following command:
+#    create_bd_design $design_name
+
+# Creating design if needed
+set errMsg ""
+set nRet 0
+
+set cur_design [current_bd_design -quiet]
+set list_cells [get_bd_cells -quiet]
+
+if { ${design_name} eq "" } {
+   # USE CASES:
+   #    1) Design_name not set
+
+   set errMsg "Please set the variable <design_name> to a non-empty value."
+   set nRet 1
+
+} elseif { ${cur_design} ne "" && ${list_cells} eq "" } {
+   # USE CASES:
+   #    2): Current design opened AND is empty AND names same.
+   #    3): Current design opened AND is empty AND names diff; design_name NOT in project.
+   #    4): Current design opened AND is empty AND names diff; design_name exists in project.
+
+   if { $cur_design ne $design_name } {
+      common::send_msg_id "BD_TCL-001" "INFO" "Changing value of <design_name> from <$design_name> to <$cur_design> since current design is empty."
+      set design_name [get_property NAME $cur_design]
+   }
+   common::send_msg_id "BD_TCL-002" "INFO" "Constructing design in IPI design <$cur_design>..."
+
+} elseif { ${cur_design} ne "" && $list_cells ne "" && $cur_design eq $design_name } {
+   # USE CASES:
+   #    5) Current design opened AND has components AND same names.
+
+   set errMsg "Design <$design_name> already exists in your project, please set the variable <design_name> to another value."
+   set nRet 1
+} elseif { [get_files -quiet ${design_name}.bd] ne "" } {
+   # USE CASES: 
+   #    6) Current opened design, has components, but diff names, design_name exists in project.
+   #    7) No opened design, design_name exists in project.
+
+   set errMsg "Design <$design_name> already exists in your project, please set the variable <design_name> to another value."
+   set nRet 2
+
+} else {
+   # USE CASES:
+   #    8) No opened design, design_name not in project.
+   #    9) Current opened design, has components, but diff names, design_name not in project.
+
+   common::send_msg_id "BD_TCL-003" "INFO" "Currently there is no design <$design_name> in project, so creating one..."
+
+   create_bd_design $design_name
+
+   common::send_msg_id "BD_TCL-004" "INFO" "Making design <$design_name> as current_bd_design."
+   current_bd_design $design_name
+
+}
+
+common::send_msg_id "BD_TCL-005" "INFO" "Currently the variable <design_name> is equal to \"$design_name\"."
+
+if { $nRet != 0 } {
+   catch {common::send_msg_id "BD_TCL-114" "ERROR" $errMsg}
+   return $nRet
+}
+
+set bCheckIPsPassed 1
+##################################################################
+# CHECK IPs
+##################################################################
+set bCheckIPs 1
+if { $bCheckIPs == 1 } {
+   set list_check_ips "\ 
+xilinx.com:ip:axi_dwidth_converter:2.1\
+xilinx.com:ip:axi_crossbar:2.1\
+"
+
+   set list_ips_missing ""
+   common::send_msg_id "BD_TCL-006" "INFO" "Checking if the following IPs exist in the project's IP catalog: $list_check_ips ."
+
+   foreach ip_vlnv $list_check_ips {
+      set ip_obj [get_ipdefs -all $ip_vlnv]
+      if { $ip_obj eq "" } {
+         lappend list_ips_missing $ip_vlnv
+      }
+   }
+
+   if { $list_ips_missing ne "" } {
+      catch {common::send_msg_id "BD_TCL-115" "ERROR" "The following IPs are not found in the IP Catalog:\n  $list_ips_missing\n\nResolution: Please add the repository containing the IP(s) to the project." }
+      set bCheckIPsPassed 0
+   }
+
+}
+
+if { $bCheckIPsPassed != 1 } {
+  common::send_msg_id "BD_TCL-1003" "WARNING" "Will not continue with creation of design due to the error(s) above."
+  return 3
+}
+
+##################################################################
+# DESIGN PROCs
+##################################################################
+
+
+
+# Procedure to create entire design; Provide argument to make
+# procedure reusable. If parentCell is "", will use root.
+proc create_root_design { parentCell } {
+
+  variable script_folder
+  variable design_name
+
+  if { $parentCell eq "" } {
+     set parentCell [get_bd_cells /]
+  }
+
+  # Get object for parentCell
+  set parentObj [get_bd_cells $parentCell]
+  if { $parentObj == "" } {
+     catch {common::send_msg_id "BD_TCL-100" "ERROR" "Unable to find parent cell <$parentCell>!"}
+     return
+  }
+
+  # Make sure parentObj is hier blk
+  set parentType [get_property TYPE $parentObj]
+  if { $parentType ne "hier" } {
+     catch {common::send_msg_id "BD_TCL-101" "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>."}
+     return
+  }
+
+  # Save current instance; Restore later
+  set oldCurInst [current_bd_instance .]
+
+  # Set parent object as current
+  current_bd_instance $parentObj
+
+
+  # Create interface ports
+  set M00_AXI [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 M00_AXI ]
+  set_property -dict [ list \
+   CONFIG.ADDR_WIDTH {29} \
+   CONFIG.CLK_DOMAIN {axi_inter_2x64_128_bd_M00_ACLK} \
+   CONFIG.DATA_WIDTH {128} \
+   CONFIG.NUM_READ_OUTSTANDING {2} \
+   CONFIG.NUM_WRITE_OUTSTANDING {2} \
+   CONFIG.PROTOCOL {AXI4} \
+   ] $M00_AXI
+
+  set S00_AXI [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 S00_AXI ]
+  set_property -dict [ list \
+   CONFIG.ADDR_WIDTH {29} \
+   CONFIG.ARUSER_WIDTH {0} \
+   CONFIG.AWUSER_WIDTH {0} \
+   CONFIG.BUSER_WIDTH {0} \
+   CONFIG.CLK_DOMAIN {axi_inter_2x64_128_bd_S00_ACLK} \
+   CONFIG.DATA_WIDTH {64} \
+   CONFIG.FREQ_HZ {200000000} \
+   CONFIG.HAS_BRESP {1} \
+   CONFIG.HAS_BURST {1} \
+   CONFIG.HAS_CACHE {1} \
+   CONFIG.HAS_LOCK {1} \
+   CONFIG.HAS_PROT {1} \
+   CONFIG.HAS_QOS {1} \
+   CONFIG.HAS_REGION {1} \
+   CONFIG.HAS_RRESP {1} \
+   CONFIG.HAS_WSTRB {1} \
+   CONFIG.ID_WIDTH {1} \
+   CONFIG.MAX_BURST_LENGTH {256} \
+   CONFIG.NUM_READ_OUTSTANDING {2} \
+   CONFIG.NUM_READ_THREADS {1} \
+   CONFIG.NUM_WRITE_OUTSTANDING {2} \
+   CONFIG.NUM_WRITE_THREADS {1} \
+   CONFIG.PROTOCOL {AXI4} \
+   CONFIG.READ_WRITE_MODE {READ_WRITE} \
+   CONFIG.RUSER_BITS_PER_BYTE {0} \
+   CONFIG.RUSER_WIDTH {0} \
+   CONFIG.SUPPORTS_NARROW_BURST {1} \
+   CONFIG.WUSER_BITS_PER_BYTE {0} \
+   CONFIG.WUSER_WIDTH {0} \
+   ] $S00_AXI
+
+  set S01_AXI [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 S01_AXI ]
+  set_property -dict [ list \
+   CONFIG.ADDR_WIDTH {29} \
+   CONFIG.ARUSER_WIDTH {0} \
+   CONFIG.AWUSER_WIDTH {0} \
+   CONFIG.BUSER_WIDTH {0} \
+   CONFIG.CLK_DOMAIN {axi_inter_2x64_128_bd_S01_ACLK} \
+   CONFIG.DATA_WIDTH {64} \
+   CONFIG.FREQ_HZ {200000000} \
+   CONFIG.HAS_BRESP {1} \
+   CONFIG.HAS_BURST {1} \
+   CONFIG.HAS_CACHE {1} \
+   CONFIG.HAS_LOCK {1} \
+   CONFIG.HAS_PROT {1} \
+   CONFIG.HAS_QOS {1} \
+   CONFIG.HAS_REGION {1} \
+   CONFIG.HAS_RRESP {1} \
+   CONFIG.HAS_WSTRB {1} \
+   CONFIG.ID_WIDTH {1} \
+   CONFIG.MAX_BURST_LENGTH {256} \
+   CONFIG.NUM_READ_OUTSTANDING {2} \
+   CONFIG.NUM_READ_THREADS {1} \
+   CONFIG.NUM_WRITE_OUTSTANDING {2} \
+   CONFIG.NUM_WRITE_THREADS {1} \
+   CONFIG.PROTOCOL {AXI4} \
+   CONFIG.READ_WRITE_MODE {READ_WRITE} \
+   CONFIG.RUSER_BITS_PER_BYTE {0} \
+   CONFIG.RUSER_WIDTH {0} \
+   CONFIG.SUPPORTS_NARROW_BURST {1} \
+   CONFIG.WUSER_BITS_PER_BYTE {0} \
+   CONFIG.WUSER_WIDTH {0} \
+   ] $S01_AXI
+
+
+  # Create ports
+  set M00_AXI_ACLK [ create_bd_port -dir I -type clk M00_AXI_ACLK ]
+  set_property -dict [ list \
+   CONFIG.ASSOCIATED_BUSIF {M00_AXI} \
+   CONFIG.ASSOCIATED_RESET {M00_AXI_ARESETN} \
+   CONFIG.CLK_DOMAIN {axi_inter_2x64_128_bd_M00_ACLK} \
+ ] $M00_AXI_ACLK
+  set M00_AXI_ARESETN [ create_bd_port -dir I -type rst M00_AXI_ARESETN ]
+  set S00_AXI_ACLK [ create_bd_port -dir I -type clk S00_AXI_ACLK ]
+  set_property -dict [ list \
+   CONFIG.ASSOCIATED_BUSIF {S00_AXI} \
+   CONFIG.ASSOCIATED_RESET {S00_AXI_ARESETN} \
+   CONFIG.CLK_DOMAIN {axi_inter_2x64_128_bd_S00_ACLK} \
+   CONFIG.FREQ_HZ {200000000} \
+ ] $S00_AXI_ACLK
+  set S00_AXI_ARESETN [ create_bd_port -dir I -type rst S00_AXI_ARESETN ]
+  set S01_AXI_ACLK [ create_bd_port -dir I -type clk S01_AXI_ACLK ]
+  set_property -dict [ list \
+   CONFIG.ASSOCIATED_BUSIF {S01_AXI} \
+   CONFIG.ASSOCIATED_RESET {S01_AXI_ARESETN} \
+   CONFIG.CLK_DOMAIN {axi_inter_2x64_128_bd_S01_ACLK} \
+   CONFIG.FREQ_HZ {200000000} \
+ ] $S01_AXI_ACLK
+  set S01_AXI_ARESETN [ create_bd_port -dir I -type rst S01_AXI_ARESETN ]
+
+  # Create instance: s00_width_conv, and set properties
+  set s00_width_conv [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_dwidth_converter:2.1 s00_width_conv ]
+  set_property -dict [ list \
+   CONFIG.ACLK_ASYNC {1} \
+   CONFIG.FIFO_MODE {2} \
+   CONFIG.MI_DATA_WIDTH {128} \
+   CONFIG.SI_DATA_WIDTH {64} \
+   CONFIG.SYNCHRONIZATION_STAGES {2} \
+ ] $s00_width_conv
+
+  # Create instance: s01_width_conv, and set properties
+  set s01_width_conv [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_dwidth_converter:2.1 s01_width_conv ]
+  set_property -dict [ list \
+   CONFIG.ACLK_ASYNC {1} \
+   CONFIG.FIFO_MODE {2} \
+   CONFIG.MI_DATA_WIDTH {128} \
+   CONFIG.SI_DATA_WIDTH {64} \
+   CONFIG.SYNCHRONIZATION_STAGES {2} \
+ ] $s01_width_conv
+
+  # Create instance: xbar, and set properties
+  set xbar [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_crossbar:2.1 xbar ]
+  set_property -dict [ list \
+   CONFIG.DATA_WIDTH {128} \
+   CONFIG.ID_WIDTH {1} \
+   CONFIG.M00_A01_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M00_A02_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M00_A03_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M00_A04_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M00_A05_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M00_A06_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M00_A07_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M00_A08_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M00_A09_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M00_A10_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M00_A11_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M00_A12_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M00_A13_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M00_A14_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M00_A15_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M00_READ_ISSUING {8} \
+   CONFIG.M00_WRITE_ISSUING {8} \
+   CONFIG.M01_A00_ADDR_WIDTH {0} \
+   CONFIG.M01_A00_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M01_A01_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M01_A02_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M01_A03_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M01_A04_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M01_A05_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M01_A06_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M01_A07_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M01_A08_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M01_A09_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M01_A10_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M01_A11_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M01_A12_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M01_A13_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M01_A14_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M01_A15_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M01_READ_ISSUING {8} \
+   CONFIG.M01_WRITE_ISSUING {8} \
+   CONFIG.M02_A00_ADDR_WIDTH {0} \
+   CONFIG.M02_A00_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M02_A01_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M02_A02_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M02_A03_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M02_A04_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M02_A05_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M02_A06_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M02_A07_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M02_A08_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M02_A09_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M02_A10_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M02_A11_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M02_A12_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M02_A13_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M02_A14_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M02_A15_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M02_READ_ISSUING {8} \
+   CONFIG.M02_WRITE_ISSUING {8} \
+   CONFIG.M03_A00_ADDR_WIDTH {0} \
+   CONFIG.M03_A00_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M03_A01_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M03_A02_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M03_A03_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M03_A04_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M03_A05_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M03_A06_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M03_A07_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M03_A08_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M03_A09_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M03_A10_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M03_A11_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M03_A12_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M03_A13_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M03_A14_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M03_A15_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M03_READ_ISSUING {8} \
+   CONFIG.M03_WRITE_ISSUING {8} \
+   CONFIG.M04_A00_ADDR_WIDTH {0} \
+   CONFIG.M04_A00_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M04_A01_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M04_A02_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M04_A03_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M04_A04_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M04_A05_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M04_A06_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M04_A07_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M04_A08_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M04_A09_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M04_A10_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M04_A11_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M04_A12_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M04_A13_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M04_A14_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M04_A15_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M04_READ_ISSUING {8} \
+   CONFIG.M04_WRITE_ISSUING {8} \
+   CONFIG.M05_A00_ADDR_WIDTH {0} \
+   CONFIG.M05_A00_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M05_A01_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M05_A02_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M05_A03_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M05_A04_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M05_A05_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M05_A06_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M05_A07_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M05_A08_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M05_A09_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M05_A10_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M05_A11_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M05_A12_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M05_A13_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M05_A14_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M05_A15_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M05_READ_ISSUING {8} \
+   CONFIG.M05_WRITE_ISSUING {8} \
+   CONFIG.M06_A00_ADDR_WIDTH {0} \
+   CONFIG.M06_A00_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M06_A01_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M06_A02_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M06_A03_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M06_A04_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M06_A05_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M06_A06_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M06_A07_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M06_A08_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M06_A09_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M06_A10_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M06_A11_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M06_A12_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M06_A13_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M06_A14_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M06_A15_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M06_READ_ISSUING {8} \
+   CONFIG.M06_WRITE_ISSUING {8} \
+   CONFIG.M07_A00_ADDR_WIDTH {0} \
+   CONFIG.M07_A00_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M07_A01_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M07_A02_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M07_A03_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M07_A04_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M07_A05_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M07_A06_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M07_A07_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M07_A08_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M07_A09_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M07_A10_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M07_A11_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M07_A12_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M07_A13_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M07_A14_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M07_A15_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M07_READ_ISSUING {8} \
+   CONFIG.M07_WRITE_ISSUING {8} \
+   CONFIG.M08_A00_ADDR_WIDTH {0} \
+   CONFIG.M08_A00_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M08_A01_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M08_A02_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M08_A03_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M08_A04_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M08_A05_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M08_A06_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M08_A07_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M08_A08_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M08_A09_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M08_A10_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M08_A11_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M08_A12_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M08_A13_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M08_A14_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M08_A15_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M08_READ_ISSUING {8} \
+   CONFIG.M08_WRITE_ISSUING {8} \
+   CONFIG.M09_A00_ADDR_WIDTH {0} \
+   CONFIG.M09_A00_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M09_A01_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M09_A02_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M09_A03_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M09_A04_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M09_A05_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M09_A06_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M09_A07_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M09_A08_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M09_A09_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M09_A10_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M09_A11_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M09_A12_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M09_A13_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M09_A14_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M09_A15_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M09_READ_ISSUING {8} \
+   CONFIG.M09_WRITE_ISSUING {8} \
+   CONFIG.M10_A00_ADDR_WIDTH {0} \
+   CONFIG.M10_A00_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M10_A01_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M10_A02_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M10_A03_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M10_A04_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M10_A05_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M10_A06_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M10_A07_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M10_A08_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M10_A09_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M10_A10_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M10_A11_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M10_A12_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M10_A13_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M10_A14_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M10_A15_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M10_READ_ISSUING {8} \
+   CONFIG.M10_WRITE_ISSUING {8} \
+   CONFIG.M11_A00_ADDR_WIDTH {0} \
+   CONFIG.M11_A00_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M11_A01_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M11_A02_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M11_A03_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M11_A04_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M11_A05_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M11_A06_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M11_A07_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M11_A08_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M11_A09_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M11_A10_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M11_A11_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M11_A12_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M11_A13_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M11_A14_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M11_A15_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M11_READ_ISSUING {8} \
+   CONFIG.M11_WRITE_ISSUING {8} \
+   CONFIG.M12_A00_ADDR_WIDTH {0} \
+   CONFIG.M12_A00_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M12_A01_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M12_A02_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M12_A03_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M12_A04_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M12_A05_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M12_A06_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M12_A07_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M12_A08_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M12_A09_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M12_A10_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M12_A11_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M12_A12_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M12_A13_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M12_A14_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M12_A15_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M12_READ_ISSUING {8} \
+   CONFIG.M12_WRITE_ISSUING {8} \
+   CONFIG.M13_A00_ADDR_WIDTH {0} \
+   CONFIG.M13_A00_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M13_A01_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M13_A02_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M13_A03_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M13_A04_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M13_A05_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M13_A06_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M13_A07_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M13_A08_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M13_A09_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M13_A10_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M13_A11_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M13_A12_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M13_A13_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M13_A14_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M13_A15_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M13_READ_ISSUING {8} \
+   CONFIG.M13_WRITE_ISSUING {8} \
+   CONFIG.M14_A00_ADDR_WIDTH {0} \
+   CONFIG.M14_A00_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M14_A01_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M14_A02_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M14_A03_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M14_A04_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M14_A05_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M14_A06_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M14_A07_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M14_A08_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M14_A09_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M14_A10_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M14_A11_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M14_A12_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M14_A13_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M14_A14_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M14_A15_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M14_READ_ISSUING {8} \
+   CONFIG.M14_WRITE_ISSUING {8} \
+   CONFIG.M15_A00_ADDR_WIDTH {0} \
+   CONFIG.M15_A00_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M15_A01_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M15_A02_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M15_A03_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M15_A04_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M15_A05_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M15_A06_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M15_A07_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M15_A08_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M15_A09_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M15_A10_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M15_A11_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M15_A12_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M15_A13_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M15_A14_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M15_A15_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M15_READ_ISSUING {8} \
+   CONFIG.M15_WRITE_ISSUING {8} \
+   CONFIG.NUM_MI {1} \
+   CONFIG.NUM_SI {2} \
+   CONFIG.S00_READ_ACCEPTANCE {4} \
+   CONFIG.S00_WRITE_ACCEPTANCE {4} \
+   CONFIG.S01_BASE_ID {0x00000001} \
+   CONFIG.S01_READ_ACCEPTANCE {4} \
+   CONFIG.S01_WRITE_ACCEPTANCE {4} \
+   CONFIG.S02_BASE_ID {0x00000002} \
+   CONFIG.S02_READ_ACCEPTANCE {4} \
+   CONFIG.S02_WRITE_ACCEPTANCE {4} \
+   CONFIG.S03_BASE_ID {0x00000003} \
+   CONFIG.S03_READ_ACCEPTANCE {4} \
+   CONFIG.S03_WRITE_ACCEPTANCE {4} \
+   CONFIG.S04_BASE_ID {0x00000004} \
+   CONFIG.S04_READ_ACCEPTANCE {4} \
+   CONFIG.S04_WRITE_ACCEPTANCE {4} \
+   CONFIG.S05_BASE_ID {0x00000005} \
+   CONFIG.S05_READ_ACCEPTANCE {4} \
+   CONFIG.S05_WRITE_ACCEPTANCE {4} \
+   CONFIG.S06_BASE_ID {0x00000006} \
+   CONFIG.S06_READ_ACCEPTANCE {4} \
+   CONFIG.S06_WRITE_ACCEPTANCE {4} \
+   CONFIG.S07_BASE_ID {0x00000007} \
+   CONFIG.S07_READ_ACCEPTANCE {4} \
+   CONFIG.S07_WRITE_ACCEPTANCE {4} \
+   CONFIG.S08_BASE_ID {0x00000008} \
+   CONFIG.S08_READ_ACCEPTANCE {4} \
+   CONFIG.S08_WRITE_ACCEPTANCE {4} \
+   CONFIG.S09_BASE_ID {0x00000009} \
+   CONFIG.S09_READ_ACCEPTANCE {4} \
+   CONFIG.S09_WRITE_ACCEPTANCE {4} \
+   CONFIG.S10_BASE_ID {0x0000000a} \
+   CONFIG.S10_READ_ACCEPTANCE {4} \
+   CONFIG.S10_WRITE_ACCEPTANCE {4} \
+   CONFIG.S11_BASE_ID {0x0000000b} \
+   CONFIG.S11_READ_ACCEPTANCE {4} \
+   CONFIG.S11_WRITE_ACCEPTANCE {4} \
+   CONFIG.S12_BASE_ID {0x0000000c} \
+   CONFIG.S12_READ_ACCEPTANCE {4} \
+   CONFIG.S12_WRITE_ACCEPTANCE {4} \
+   CONFIG.S13_BASE_ID {0x0000000d} \
+   CONFIG.S13_READ_ACCEPTANCE {4} \
+   CONFIG.S13_WRITE_ACCEPTANCE {4} \
+   CONFIG.S14_BASE_ID {0x0000000e} \
+   CONFIG.S14_READ_ACCEPTANCE {4} \
+   CONFIG.S14_WRITE_ACCEPTANCE {4} \
+   CONFIG.S15_BASE_ID {0x0000000f} \
+   CONFIG.S15_READ_ACCEPTANCE {4} \
+   CONFIG.S15_WRITE_ACCEPTANCE {4} \
+   CONFIG.STRATEGY {2} \
+ ] $xbar
+
+  # Create interface connections
+  connect_bd_intf_net -intf_net S00_AXI_1 [get_bd_intf_ports S00_AXI] [get_bd_intf_pins s00_width_conv/S_AXI]
+  connect_bd_intf_net -intf_net S01_AXI_1 [get_bd_intf_ports S01_AXI] [get_bd_intf_pins s01_width_conv/S_AXI]
+  connect_bd_intf_net -intf_net s00_width_conv_M_AXI [get_bd_intf_pins s00_width_conv/M_AXI] [get_bd_intf_pins xbar/S00_AXI]
+  connect_bd_intf_net -intf_net s01_width_conv_M_AXI [get_bd_intf_pins s01_width_conv/M_AXI] [get_bd_intf_pins xbar/S01_AXI]
+  connect_bd_intf_net -intf_net xbar_M00_AXI [get_bd_intf_ports M00_AXI] [get_bd_intf_pins xbar/M00_AXI]
+
+  # Create port connections
+  connect_bd_net -net M00_AXI_ACLK_1 [get_bd_ports M00_AXI_ACLK] [get_bd_pins s00_width_conv/m_axi_aclk] [get_bd_pins s01_width_conv/m_axi_aclk] [get_bd_pins xbar/aclk]
+  connect_bd_net -net M00_AXI_ARESETN_1 [get_bd_ports M00_AXI_ARESETN] [get_bd_pins s00_width_conv/m_axi_aresetn] [get_bd_pins s01_width_conv/m_axi_aresetn] [get_bd_pins xbar/aresetn]
+  connect_bd_net -net S00_AXI_ACLK_1 [get_bd_ports S00_AXI_ACLK] [get_bd_pins s00_width_conv/s_axi_aclk]
+  connect_bd_net -net S00_AXI_ARESETN_1 [get_bd_ports S00_AXI_ARESETN] [get_bd_pins s00_width_conv/s_axi_aresetn]
+  connect_bd_net -net S01_AXI_ACLK_1 [get_bd_ports S01_AXI_ACLK] [get_bd_pins s01_width_conv/s_axi_aclk]
+  connect_bd_net -net S01_AXI_ARESETN_1 [get_bd_ports S01_AXI_ARESETN] [get_bd_pins s01_width_conv/s_axi_aresetn]
+
+  # Create address segments
+  create_bd_addr_seg -range 0x20000000 -offset 0x00000000 [get_bd_addr_spaces S00_AXI] [get_bd_addr_segs M00_AXI/Reg] SEG_M00_AXI_Reg
+  create_bd_addr_seg -range 0x20000000 -offset 0x00000000 [get_bd_addr_spaces S01_AXI] [get_bd_addr_segs M00_AXI/Reg] SEG_M00_AXI_Reg
+
+
+  # Restore current instance
+  current_bd_instance $oldCurInst
+
+  validate_bd_design
+  save_bd_design
+}
+# End of create_root_design()
+
+
+##################################################################
+# MAIN FLOW
+##################################################################
+
+create_root_design ""
+
+
diff --git a/fpga/usrp3/top/e31x/ip/ddr3_16bit/Makefile.inc b/fpga/usrp3/top/e31x/ip/ddr3_16bit/Makefile.inc
new file mode 100644
index 000000000..66187c699
--- /dev/null
+++ b/fpga/usrp3/top/e31x/ip/ddr3_16bit/Makefile.inc
@@ -0,0 +1,32 @@
+#
+# Copyright 2022 Ettus Research, a National Instruments Brand
+#
+
+include $(TOOLS_DIR)/make/viv_ip_builder.mak
+
+IP_DDR3_16BIT_SRCS = $(IP_BUILD_DIR)/ddr3_16bit/ddr3_16bit.xci
+
+IP_DDR3_16BIT_OUTS = $(addprefix $(IP_BUILD_DIR)/ddr3_16bit/, \
+ddr3_16bit.xci.out \
+ddr3_16bit/user_design/rtl/ddr3_16bit.v \
+ddr3_16bit/user_design/rtl/ddr3_16bit_mig.v \
+)
+
+IP_MIG_7SERIES_TG_SRCS = $(addprefix $(IP_BUILD_DIR)/ddr3_16bit/, \
+ddr3_16bit/example_design/rtl/example_top.v \
+ddr3_16bit/example_design/rtl/traffic_gen/mig_7series_v4_2_axi4_tg.v \
+ddr3_16bit/example_design/rtl/traffic_gen/mig_7series_v4_2_axi4_wrapper.v \
+ddr3_16bit/example_design/rtl/traffic_gen/mig_7series_v4_2_cmd_prbs_gen_axi.v  \
+ddr3_16bit/example_design/rtl/traffic_gen/mig_7series_v4_2_data_gen_chk.v \
+ddr3_16bit/example_design/rtl/traffic_gen/mig_7series_v4_2_tg.v \
+)
+
+IP_DDR3_16BIT_SIM_OUTS = $(addprefix $(IP_BUILD_DIR)/ddr3_16bit/, \
+ddr3_16bit/example_design/sim/ddr3_model.sv \
+ddr3_16bit/example_design/sim/ddr3_model_parameters.vh \
+)
+
+$(IP_DDR3_16BIT_SRCS) $(IP_DDR3_16BIT_OUTS) : $(IP_DIR)/ddr3_16bit/ddr3_16bit.xci $(IP_DIR)/ddr3_16bit/mig_*.prj
+	cp -f $(IP_DIR)/ddr3_16bit/mig_$(subst /,,$(PART_ID)).prj $(IP_DIR)/ddr3_16bit/mig_a.prj # Note: This won't allow parallel IP builds
+	$(call BUILD_VIVADO_IP,ddr3_16bit,$(ARCH),$(PART_ID),$(IP_DIR),$(IP_BUILD_DIR),0)
+	rm -f $(IP_DIR)/ddr3_16bit/mig_a.prj
diff --git a/fpga/usrp3/top/e31x/ip/mig_7series_0/mig_7series_0.xci b/fpga/usrp3/top/e31x/ip/ddr3_16bit/ddr3_16bit.xci
index 5b99fe23c..7d467a859 100644
--- a/fpga/usrp3/top/e31x/ip/mig_7series_0/mig_7series_0.xci
+++ b/fpga/usrp3/top/e31x/ip/ddr3_16bit/ddr3_16bit.xci
@@ -6,7 +6,7 @@
   <spirit:version>1.0</spirit:version>
   <spirit:componentInstances>
     <spirit:componentInstance>
-      <spirit:instanceName>mig_7series_0</spirit:instanceName>
+      <spirit:instanceName>ddr3_16bit</spirit:instanceName>
       <spirit:componentRef spirit:vendor="xilinx.com" spirit:library="ip" spirit:name="mig_7series" spirit:version="4.2"/>
       <spirit:configurableElementValues>
         <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.ARESETN.INSERT_VIP">0</spirit:configurableElementValue>
@@ -2300,7 +2300,7 @@
         <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.UI_EXTRA_CLOCKS">FALSE</spirit:configurableElementValue>
         <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.USE_AXI">1</spirit:configurableElementValue>
         <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.BOARD_MIG_PARAM">Custom</spirit:configurableElementValue>
-        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">mig_7series_0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">ddr3_16bit</spirit:configurableElementValue>
         <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MIG_DONT_TOUCH_PARAM">Custom</spirit:configurableElementValue>
         <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RESET_BOARD_INTERFACE">Custom</spirit:configurableElementValue>
         <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.XML_INPUT_FILE">mig_a.prj</spirit:configurableElementValue>
@@ -2646,3 +2646,4 @@
     </spirit:componentInstance>
   </spirit:componentInstances>
 </spirit:design>
+
diff --git a/fpga/usrp3/top/e31x/ip/mig_7series_0/mig_xc7z020clg484-1.prj b/fpga/usrp3/top/e31x/ip/ddr3_16bit/mig_xc7z020clg484-1.prj
index f8c67329b..74d75d1b7 100644
--- a/fpga/usrp3/top/e31x/ip/mig_7series_0/mig_xc7z020clg484-1.prj
+++ b/fpga/usrp3/top/e31x/ip/ddr3_16bit/mig_xc7z020clg484-1.prj
@@ -1,7 +1,7 @@
 <?xml version='1.0' encoding='UTF-8'?>
 <!-- IMPORTANT: This is an internal file that has been generated by the MIG software. Any direct editing or changes made to this file may result in unpredictable behavior or data corruption. It is strongly advised that users do not edit the contents of this file. Re-run the MIG GUI with the required settings if any of the options provided below need to be altered. -->
 <Project NoOfControllers="1" >
-    <ModuleName>mig_7series_0</ModuleName>
+    <ModuleName>ddr3_16bit</ModuleName>
     <dci_inouts_inputs>1</dci_inouts_inputs>
     <dci_inputs>1</dci_inputs>
     <Debug_En>OFF</Debug_En>
diff --git a/fpga/usrp3/top/e31x/ip/mig_7series_0/mig_xc7z020clg484-3.prj b/fpga/usrp3/top/e31x/ip/ddr3_16bit/mig_xc7z020clg484-3.prj
index 635ea1471..9494d07ae 100644
--- a/fpga/usrp3/top/e31x/ip/mig_7series_0/mig_xc7z020clg484-3.prj
+++ b/fpga/usrp3/top/e31x/ip/ddr3_16bit/mig_xc7z020clg484-3.prj
@@ -1,7 +1,7 @@
 <?xml version='1.0' encoding='UTF-8'?>
 <!-- IMPORTANT: This is an internal file that has been generated by the MIG software. Any direct editing or changes made to this file may result in unpredictable behavior or data corruption. It is strongly advised that users do not edit the contents of this file. Re-run the MIG GUI with the required settings if any of the options provided below need to be altered. -->
 <Project NoOfControllers="1" >
-    <ModuleName>mig_7series_0</ModuleName>
+    <ModuleName>ddr3_16bit</ModuleName>
     <dci_inouts_inputs>1</dci_inouts_inputs>
     <dci_inputs>1</dci_inputs>
     <Debug_En>OFF</Debug_En>
diff --git a/fpga/usrp3/top/e31x/ip/mig_7series_0/Makefile.inc b/fpga/usrp3/top/e31x/ip/mig_7series_0/Makefile.inc
deleted file mode 100644
index 87dd39573..000000000
--- a/fpga/usrp3/top/e31x/ip/mig_7series_0/Makefile.inc
+++ /dev/null
@@ -1,32 +0,0 @@
-#
-# Copyright 2015 Ettus Research
-#
-
-include $(TOOLS_DIR)/make/viv_ip_builder.mak
-
-IP_MIG_7SERIES_0_SRCS = $(IP_BUILD_DIR)/mig_7series_0/mig_7series_0.xci
-
-IP_MIG_7SERIES_0_OUTS = $(addprefix $(IP_BUILD_DIR)/mig_7series_0/, \
-mig_7series_0.xci.out \
-mig_7series_0/user_design/rtl/mig_7series_0.v \
-mig_7series_0/user_design/rtl/mig_7series_0_mig.v \
-)
-
-IP_MIG_7SERIES_TG_SRCS = $(addprefix $(IP_BUILD_DIR)/mig_7series_0/, \
-mig_7series_0/example_design/rtl/example_top.v \
-mig_7series_0/example_design/rtl/traffic_gen/mig_7series_v4_2_axi4_tg.v \
-mig_7series_0/example_design/rtl/traffic_gen/mig_7series_v4_2_axi4_wrapper.v \
-mig_7series_0/example_design/rtl/traffic_gen/mig_7series_v4_2_cmd_prbs_gen_axi.v  \
-mig_7series_0/example_design/rtl/traffic_gen/mig_7series_v4_2_data_gen_chk.v \
-mig_7series_0/example_design/rtl/traffic_gen/mig_7series_v4_2_tg.v \
-)
-
-IP_MIG_7SERIES_0_SIM_OUTS = $(addprefix $(IP_BUILD_DIR)/mig_7series_0/, \
-mig_7series_0/example_design/sim/ddr3_model.sv \
-mig_7series_0/example_design/sim/ddr3_model_parameters.vh \
-)
-
-$(IP_MIG_7SERIES_0_SRCS) $(IP_MIG_7SERIES_0_OUTS) : $(IP_DIR)/mig_7series_0/mig_7series_0.xci $(IP_DIR)/mig_7series_0/mig_*.prj
-	cp -f $(IP_DIR)/mig_7series_0/mig_$(subst /,,$(PART_ID)).prj $(IP_DIR)/mig_7series_0/mig_a.prj # Note: This won't allow parallel IP builds
-	$(call BUILD_VIVADO_IP,mig_7series_0,$(ARCH),$(PART_ID),$(IP_DIR),$(IP_BUILD_DIR),0)
-	rm -f $(IP_DIR)/mig_7series_0/mig_a.prj