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authorBen Hilburn <ben.hilburn@ettus.com>2014-07-22 15:49:02 -0700
committerBen Hilburn <ben.hilburn@ettus.com>2014-07-22 15:49:02 -0700
commitb63507efb3cf1a8fa20794c452d57028e18da182 (patch)
tree13f6ec6c3098dff29a3fb50ff3c70bc4d22e7e32 /fpga/usrp3/top/b200
parent7911d3e2e90672f44eafc635208053fe75ff19d9 (diff)
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fpga: Updating FPGA code for UHD-3.7.2-rc1
Diffstat (limited to 'fpga/usrp3/top/b200')
-rw-r--r--fpga/usrp3/top/b200/b200_core.v25
-rw-r--r--fpga/usrp3/top/b200/coregen/chipscope_icon.gise2
-rw-r--r--fpga/usrp3/top/b200/coregen/chipscope_icon.xise4
-rw-r--r--fpga/usrp3/top/b200/coregen/chipscope_ila_128.gise2
-rw-r--r--fpga/usrp3/top/b200/coregen/chipscope_ila_128.xise4
-rw-r--r--fpga/usrp3/top/b200/coregen/chipscope_ila_256.gise2
-rw-r--r--fpga/usrp3/top/b200/coregen/chipscope_ila_256.xise4
-rw-r--r--fpga/usrp3/top/b200/coregen/chipscope_ila_32.gise2
-rw-r--r--fpga/usrp3/top/b200/coregen/chipscope_ila_32.xise4
-rw-r--r--fpga/usrp3/top/b200/coregen/fifo_4k_2clk.gise2
-rw-r--r--fpga/usrp3/top/b200/coregen/fifo_4k_2clk.xise4
-rw-r--r--fpga/usrp3/top/b200/coregen/fifo_short_2clk.gise2
-rw-r--r--fpga/usrp3/top/b200/coregen/fifo_short_2clk.xise4
13 files changed, 37 insertions, 24 deletions
diff --git a/fpga/usrp3/top/b200/b200_core.v b/fpga/usrp3/top/b200/b200_core.v
index 016037688..dc8baba4f 100644
--- a/fpga/usrp3/top/b200/b200_core.v
+++ b/fpga/usrp3/top/b200/b200_core.v
@@ -1,5 +1,5 @@
//
-// Copyright 2013 Ettus Research LLC
+// Copyright 2013-14 Ettus Research LLC
//
@@ -78,11 +78,24 @@ module b200_core
/*******************************************************************
* PPS Timing stuff
******************************************************************/
- reg [1:0] int_pps_del, ext_pps_del;
+
+ // Generate an internal PPS signal
+ wire int_pps;
+ pps_generator #(.CLK_FREQ(100000000)) pps_gen
+ (.clk(bus_clk), .pps(int_pps));
+
+ // Flop PPS signals into radio clock domain
+ reg [1:0] gpsdo_pps_del, ext_pps_del, int_pps_del;
always @(posedge radio_clk) ext_pps_del[1:0] <= {ext_pps_del[0], pps_ext};
- always @(posedge radio_clk) int_pps_del[1:0] <= {int_pps_del[0], pps_int};
- wire pps_select;
- wire pps = pps_select? ext_pps_del[1] : int_pps_del[1];
+ always @(posedge radio_clk) gpsdo_pps_del[1:0] <= {gpsdo_pps_del[0], pps_int};
+ always @(posedge radio_clk) int_pps_del[1:0] <= {int_pps_del[0], int_pps};
+
+ // PPS mux
+ wire [1:0] pps_select;
+ wire pps = (pps_select == 2'b00)? gpsdo_pps_del[1] :
+ (pps_select == 2'b01)? ext_pps_del[1] :
+ (pps_select == 2'b10)? int_pps_del[1] :
+ 1'b0;
/*******************************************************************
* Response mux Routing logic
@@ -189,7 +202,7 @@ module b200_core
(.clk(bus_clk), .rst(1'b0/*keep*/), .strobe(set_stb), .addr(set_addr), .in(set_data),
.out(gpsdo_st), .changed());
- setting_reg #(.my_addr(SR_CORE_PPS_SEL), .awidth(8), .width(1)) sr_pps_sel
+ setting_reg #(.my_addr(SR_CORE_PPS_SEL), .awidth(8), .width(2)) sr_pps_sel
(.clk(bus_clk), .rst(bus_rst), .strobe(set_stb), .addr(set_addr), .in(set_data),
.out(pps_select), .changed());
diff --git a/fpga/usrp3/top/b200/coregen/chipscope_icon.gise b/fpga/usrp3/top/b200/coregen/chipscope_icon.gise
index a4f878755..29d14a154 100644
--- a/fpga/usrp3/top/b200/coregen/chipscope_icon.gise
+++ b/fpga/usrp3/top/b200/coregen/chipscope_icon.gise
@@ -15,7 +15,7 @@
<!-- -->
- <!-- Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. -->
+ <!-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. -->
<version xmlns="http://www.xilinx.com/XMLSchema">11.1</version>
diff --git a/fpga/usrp3/top/b200/coregen/chipscope_icon.xise b/fpga/usrp3/top/b200/coregen/chipscope_icon.xise
index 669cbf101..5cb07142c 100644
--- a/fpga/usrp3/top/b200/coregen/chipscope_icon.xise
+++ b/fpga/usrp3/top/b200/coregen/chipscope_icon.xise
@@ -9,10 +9,10 @@
<!-- along with the project source files, is sufficient to open and -->
<!-- implement in ISE Project Navigator. -->
<!-- -->
- <!-- Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. -->
+ <!-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. -->
</header>
- <version xil_pn:ise_version="14.4" xil_pn:schema_version="2"/>
+ <version xil_pn:ise_version="14.6" xil_pn:schema_version="2"/>
<files>
<file xil_pn:name="chipscope_icon.ngc" xil_pn:type="FILE_NGC">
diff --git a/fpga/usrp3/top/b200/coregen/chipscope_ila_128.gise b/fpga/usrp3/top/b200/coregen/chipscope_ila_128.gise
index 3af396d70..8f50adfb5 100644
--- a/fpga/usrp3/top/b200/coregen/chipscope_ila_128.gise
+++ b/fpga/usrp3/top/b200/coregen/chipscope_ila_128.gise
@@ -15,7 +15,7 @@
<!-- -->
- <!-- Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. -->
+ <!-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. -->
<version xmlns="http://www.xilinx.com/XMLSchema">11.1</version>
diff --git a/fpga/usrp3/top/b200/coregen/chipscope_ila_128.xise b/fpga/usrp3/top/b200/coregen/chipscope_ila_128.xise
index 3bc65beca..d89d10530 100644
--- a/fpga/usrp3/top/b200/coregen/chipscope_ila_128.xise
+++ b/fpga/usrp3/top/b200/coregen/chipscope_ila_128.xise
@@ -9,10 +9,10 @@
<!-- along with the project source files, is sufficient to open and -->
<!-- implement in ISE Project Navigator. -->
<!-- -->
- <!-- Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. -->
+ <!-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. -->
</header>
- <version xil_pn:ise_version="14.4" xil_pn:schema_version="2"/>
+ <version xil_pn:ise_version="14.6" xil_pn:schema_version="2"/>
<files>
<file xil_pn:name="chipscope_ila_128.ngc" xil_pn:type="FILE_NGC">
diff --git a/fpga/usrp3/top/b200/coregen/chipscope_ila_256.gise b/fpga/usrp3/top/b200/coregen/chipscope_ila_256.gise
index 6305e6288..85cc00a94 100644
--- a/fpga/usrp3/top/b200/coregen/chipscope_ila_256.gise
+++ b/fpga/usrp3/top/b200/coregen/chipscope_ila_256.gise
@@ -15,7 +15,7 @@
<!-- -->
- <!-- Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. -->
+ <!-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. -->
<version xmlns="http://www.xilinx.com/XMLSchema">11.1</version>
diff --git a/fpga/usrp3/top/b200/coregen/chipscope_ila_256.xise b/fpga/usrp3/top/b200/coregen/chipscope_ila_256.xise
index f8c51bac1..a9e75da04 100644
--- a/fpga/usrp3/top/b200/coregen/chipscope_ila_256.xise
+++ b/fpga/usrp3/top/b200/coregen/chipscope_ila_256.xise
@@ -9,10 +9,10 @@
<!-- along with the project source files, is sufficient to open and -->
<!-- implement in ISE Project Navigator. -->
<!-- -->
- <!-- Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. -->
+ <!-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. -->
</header>
- <version xil_pn:ise_version="14.4" xil_pn:schema_version="2"/>
+ <version xil_pn:ise_version="14.6" xil_pn:schema_version="2"/>
<files>
<file xil_pn:name="chipscope_ila_256.ngc" xil_pn:type="FILE_NGC">
diff --git a/fpga/usrp3/top/b200/coregen/chipscope_ila_32.gise b/fpga/usrp3/top/b200/coregen/chipscope_ila_32.gise
index 4bc01d034..e5487e74a 100644
--- a/fpga/usrp3/top/b200/coregen/chipscope_ila_32.gise
+++ b/fpga/usrp3/top/b200/coregen/chipscope_ila_32.gise
@@ -15,7 +15,7 @@
<!-- -->
- <!-- Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. -->
+ <!-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. -->
<version xmlns="http://www.xilinx.com/XMLSchema">11.1</version>
diff --git a/fpga/usrp3/top/b200/coregen/chipscope_ila_32.xise b/fpga/usrp3/top/b200/coregen/chipscope_ila_32.xise
index 9a9fb9459..8d210d750 100644
--- a/fpga/usrp3/top/b200/coregen/chipscope_ila_32.xise
+++ b/fpga/usrp3/top/b200/coregen/chipscope_ila_32.xise
@@ -9,10 +9,10 @@
<!-- along with the project source files, is sufficient to open and -->
<!-- implement in ISE Project Navigator. -->
<!-- -->
- <!-- Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. -->
+ <!-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. -->
</header>
- <version xil_pn:ise_version="14.4" xil_pn:schema_version="2"/>
+ <version xil_pn:ise_version="14.6" xil_pn:schema_version="2"/>
<files>
<file xil_pn:name="chipscope_ila_32.ngc" xil_pn:type="FILE_NGC">
diff --git a/fpga/usrp3/top/b200/coregen/fifo_4k_2clk.gise b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk.gise
index c631a4815..ae7343223 100644
--- a/fpga/usrp3/top/b200/coregen/fifo_4k_2clk.gise
+++ b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk.gise
@@ -15,7 +15,7 @@
<!-- -->
- <!-- Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. -->
+ <!-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. -->
<version xmlns="http://www.xilinx.com/XMLSchema">11.1</version>
diff --git a/fpga/usrp3/top/b200/coregen/fifo_4k_2clk.xise b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk.xise
index 2d8132c10..951b199cf 100644
--- a/fpga/usrp3/top/b200/coregen/fifo_4k_2clk.xise
+++ b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk.xise
@@ -9,10 +9,10 @@
<!-- along with the project source files, is sufficient to open and -->
<!-- implement in ISE Project Navigator. -->
<!-- -->
- <!-- Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. -->
+ <!-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. -->
</header>
- <version xil_pn:ise_version="14.4" xil_pn:schema_version="2"/>
+ <version xil_pn:ise_version="14.6" xil_pn:schema_version="2"/>
<files>
<file xil_pn:name="fifo_4k_2clk.ngc" xil_pn:type="FILE_NGC">
diff --git a/fpga/usrp3/top/b200/coregen/fifo_short_2clk.gise b/fpga/usrp3/top/b200/coregen/fifo_short_2clk.gise
index ea47d0f4b..ddb581fc1 100644
--- a/fpga/usrp3/top/b200/coregen/fifo_short_2clk.gise
+++ b/fpga/usrp3/top/b200/coregen/fifo_short_2clk.gise
@@ -15,7 +15,7 @@
<!-- -->
- <!-- Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. -->
+ <!-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. -->
<version xmlns="http://www.xilinx.com/XMLSchema">11.1</version>
diff --git a/fpga/usrp3/top/b200/coregen/fifo_short_2clk.xise b/fpga/usrp3/top/b200/coregen/fifo_short_2clk.xise
index 1ca7d35ee..1f72b185a 100644
--- a/fpga/usrp3/top/b200/coregen/fifo_short_2clk.xise
+++ b/fpga/usrp3/top/b200/coregen/fifo_short_2clk.xise
@@ -9,10 +9,10 @@
<!-- along with the project source files, is sufficient to open and -->
<!-- implement in ISE Project Navigator. -->
<!-- -->
- <!-- Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. -->
+ <!-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. -->
</header>
- <version xil_pn:ise_version="14.4" xil_pn:schema_version="2"/>
+ <version xil_pn:ise_version="14.6" xil_pn:schema_version="2"/>
<files>
<file xil_pn:name="fifo_short_2clk.ngc" xil_pn:type="FILE_NGC">
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