Pushing the bulk of UHD-3.7.0 code.

5 files changed, 89 insertions, 56 deletions

diff --git a/fpga/usrp3/top/b200/Makefile.b200.inc b/fpga/usrp3/top/b200/Makefile.b200.inc
index da7561cab..288a29fe3 100644
--- a/fpga/usrp3/top/b200/Makefile.b200.inc
+++ b/fpga/usrp3/top/b200/Makefile.b200.inc
@@ -22,6 +22,7 @@ include ../../lib/packet_proc/Makefile.srcs
 include ../../lib/timing/Makefile.srcs
 include ../../lib/vita/Makefile.srcs
 include ../../lib/wishbone/Makefile.srcs
+include ../../lib/axi/Makefile.srcs
 
 B200_COREGEN_SRCS = \
 coregen/b200_clk_gen.v \
@@ -76,7 +77,8 @@ $(GPIF2_SRCS) $(PACKET_PROC_SRCS) \
 $(WISHBONE_SRCS) \
 $(TIMING_SRCS) \
 $(DSP_SRCS) \
-$(VITA_SRCS)
+$(VITA_SRCS) \
+$(AXI_SRCS)
 
 ##################################################
 # Process Properties
diff --git a/fpga/usrp3/top/b200/b200.v b/fpga/usrp3/top/b200/b200.v
index 3a8ece238..b25c02bdf 100644
--- a/fpga/usrp3/top/b200/b200.v
+++ b/fpga/usrp3/top/b200/b200.v
@@ -1,19 +1,7 @@
 //
 // Copyright 2013 Ettus Research LLC
 //
-// This program is free software: you can redistribute it and/or modify
-// it under the terms of the GNU General Public License as published by
-// the Free Software Foundation, either version 3 of the License, or
-// (at your option) any later version.
-//
-// This program is distributed in the hope that it will be useful,
-// but WITHOUT ANY WARRANTY; without even the implied warranty of
-// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-// GNU General Public License for more details.
-//
-// You should have received a copy of the GNU General Public License
-// along with this program.  If not, see <http://www.gnu.org/licenses/>.
-//
+
 
 /***********************************************************
  * B200 Module Declaration
@@ -250,12 +238,14 @@ module b200 (
         .sclk(sclk), .sen(sen), .mosi(mosi), .miso(miso),
         .rb_misc({31'b0, pll_lock}), .misc_outs(misc_outs),
 
-        .debug_scl(GPIF_CTL8), .debug_sda(GPIF_CTL6),
-        .debug_txd(FPGA_TXD0), .debug_rxd(FPGA_RXD0),
+       .debug_scl(GPIF_CTL8), .debug_sda(GPIF_CTL6),
+       .debug_txd(FPGA_TXD0), .debug_rxd(FPGA_RXD0),
 
         .debug()
     );
 
+   
+
     ///////////////////////////////////////////////////////////////////////
     // GPIF2
     ///////////////////////////////////////////////////////////////////////
diff --git a/fpga/usrp3/top/b200/b200_core.v b/fpga/usrp3/top/b200/b200_core.v
index 45718b911..016037688 100644
--- a/fpga/usrp3/top/b200/b200_core.v
+++ b/fpga/usrp3/top/b200/b200_core.v
@@ -1,19 +1,7 @@
 //
 // Copyright 2013 Ettus Research LLC
 //
-// This program is free software: you can redistribute it and/or modify
-// it under the terms of the GNU General Public License as published by
-// the Free Software Foundation, either version 3 of the License, or
-// (at your option) any later version.
-//
-// This program is distributed in the hope that it will be useful,
-// but WITHOUT ANY WARRANTY; without even the implied warranty of
-// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-// GNU General Public License for more details.
-//
-// You should have received a copy of the GNU General Public License
-// along with this program.  If not, see <http://www.gnu.org/licenses/>.
-//
+
 
 /***********************************************************
  * B200 Core Guts
@@ -227,7 +215,7 @@ module b200_core
     wire [63:0] r1_rx_tdata; wire r1_rx_tlast, r1_rx_tvalid, r1_rx_tready;
     wire [63:0] rx_tdata_int; wire rx_tlast_int, rx_tvalid_int, rx_tready_int;
 
-    axi_mux4 #(.WIDTH(64), .BUFFER(1)) mux_for_rx
+   axi_mux4 #(.WIDTH(64), .BUFFER(1)) mux_for_rx
      (.clk(bus_clk), .reset(bus_rst), .clear(1'b0),
       .i0_tdata(r0_rx_tdata), .i0_tlast(r0_rx_tlast), .i0_tvalid(r0_rx_tvalid), .i0_tready(r0_rx_tready),
       .i1_tdata(r1_rx_tdata), .i1_tlast(r1_rx_tlast), .i1_tvalid(r1_rx_tvalid), .i1_tready(r1_rx_tready),
@@ -290,7 +278,8 @@ module b200_core
      ******************************************************************/
     `ifdef B200_CAN_HAZ_R1
     assign radio_st = 8'h2;
-
+   wire [63:0] radio1_debug;
+   
     radio_b200 #(.RADIO_FIFO_SIZE(RADIO_FIFO_SIZE),.SAMPLE_FIFO_SIZE(SAMPLE_FIFO_SIZE)) radio_1
     (
         .radio_clk(radio_clk), .radio_rst(radio_rst),
@@ -302,7 +291,7 @@ module b200_core
         .ctrl_tdata(r1_ctrl_tdata), .ctrl_tlast(r1_ctrl_tlast),  .ctrl_tvalid(r1_ctrl_tvalid), .ctrl_tready(r1_ctrl_tready),
         .resp_tdata(r1_resp_tdata), .resp_tlast(r1_resp_tlast),  .resp_tvalid(r1_resp_tvalid), .resp_tready(r1_resp_tready),
 
-        .debug()
+        .debug(radio1_debug)
     );
 
     `else
@@ -332,6 +321,8 @@ module b200_core
    wire    debug_stb;
    wire [31:0] debug_data;
    wire [7:0]  debug_addr;
+   wire [31:0] debug_serial;
+ 
    
    serial_to_settings serial_to_settings_i1
      (
@@ -341,18 +332,28 @@ module b200_core
       .sda(debug_sda),
       .set_stb(debug_stb),
       .set_addr(debug_addr),
-      .set_data(debug_data)
+      .set_data(debug_data),
+      .debug(debug_serial)
       );
 
+   // Nasty HAck to convert settings to wishbone crudely.
+   reg 	       wb_stb;
+   wire        wb_ack_o;
+   
+   
+   always @(posedge bus_clk)
+     wb_stb <= debug_stb ? 1 : ((wb_ack_o) ? 0 : wb_stb);
+   
+   
    
    simple_uart debug_uart
      (
       .clk_i(bus_clk), 
       .rst_i(bus_rst),
-      .we_i(debug_stb), 
-      .stb_i(debug_stb), 
-      .cyc_i(debug_stb), 
-      .ack_o(),
+      .we_i(wb_stb), 
+      .stb_i(wb_stb), 
+      .cyc_i(wb_stb), 
+      .ack_o(wb_ack_o),
       .adr_i(debug_addr[2:0]), 
       .dat_i(debug_data[31:0]), 
       .dat_o(),
@@ -362,8 +363,43 @@ module b200_core
       .rx_i(debug_rxd), 
       .baud_o()
       );
+
+   //
+   // Debug
+   //
+/* -----\/----- EXCLUDED -----\/-----
+
+   wire [35:0] CONTROL0;
    
+   chipscope_ila_128 chipscope_ila_i0
+     (
+      .CONTROL(CONTROL0), // INOUT BUS [35:0]
+      .CLK(bus_clk), // IN
+      .TRIG0(
+         {
+	  triggerA0,
+	  triggerB0,
+	  r0_rx_tlast,
+	  r0_rx_tvalid,
+	  r0_rx_tready,
+	  r1_rx_tlast,
+	  r1_rx_tvalid,
+	  r1_rx_tready,
+	  rx_tlast,
+	  rx_tvalid,
+	  rx_tready,
+	  r0_rx_tdata[15:0],
+	  r1_rx_tdata[15:0],
+	  rx_tdata[15:0]
+          }
+         ) // IN BUS [191:0]
+      );
 
+   chipscope_icon chipscope_icon_i0
+     (
+      .CONTROL0(CONTROL0) // INOUT BUS [35:0]
+      );
+ -----/\----- EXCLUDED -----/\----- */
    
 
 endmodule // b200_core
diff --git a/fpga/usrp3/top/b200/coregen/chipscope_ila_128.xise b/fpga/usrp3/top/b200/coregen/chipscope_ila_128.xise
index 8f58b6783..3bc65beca 100644
--- a/fpga/usrp3/top/b200/coregen/chipscope_ila_128.xise
+++ b/fpga/usrp3/top/b200/coregen/chipscope_ila_128.xise
@@ -17,11 +17,11 @@
   <files>
     <file xil_pn:name="chipscope_ila_128.ngc" xil_pn:type="FILE_NGC">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="2"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="1"/>
     </file>
     <file xil_pn:name="chipscope_ila_128.v" xil_pn:type="FILE_VERILOG">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="3"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
       <association xil_pn:name="PostMapSimulation" xil_pn:seqID="3"/>
       <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="3"/>
       <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="3"/>
diff --git a/fpga/usrp3/top/b200/radio_b200.v b/fpga/usrp3/top/b200/radio_b200.v
index a0ea808a5..7771851a3 100644
--- a/fpga/usrp3/top/b200/radio_b200.v
+++ b/fpga/usrp3/top/b200/radio_b200.v
@@ -1,19 +1,7 @@
 //
 // Copyright 2013 Ettus Research LLC
 //
-// This program is free software: you can redistribute it and/or modify
-// it under the terms of the GNU General Public License as published by
-// the Free Software Foundation, either version 3 of the License, or
-// (at your option) any later version.
-//
-// This program is distributed in the hope that it will be useful,
-// but WITHOUT ANY WARRANTY; without even the implied warranty of
-// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-// GNU General Public License for more details.
-//
-// You should have received a copy of the GNU General Public License
-// along with this program.  If not, see <http://www.gnu.org/licenses/>.
-//
+
 
 // radio top level module for b200
 //  Contains all clock-rate DSP components, all radio and hardware controls and settings
@@ -35,6 +23,7 @@ module radio_b200
 
    output [63:0] debug
    );
+   
 
    // ///////////////////////////////////////////////////////////////////////////////
    // FIFO Interfacing to the bus clk domain
@@ -73,7 +62,11 @@ module radio_b200
 
    wire [63:0] 	 rmux_tdata_r;
    wire 	 rmux_tlast_r, rmux_tvalid_r, rmux_tready_r;
-   
+
+   wire [63:0] 	 rx_tdata_int;
+   wire 	 rx_tready_int, rx_tvalid_int;
+   wire 	 rx_tlast_int;
+
    axi_fifo_2clk #(.WIDTH(65), .SIZE(0/*minimal*/)) ctrl_fifo
      (.reset(bus_rst),
       .i_aclk(bus_clk), .i_tvalid(ctrl_tvalid), .i_tready(ctrl_tready), .i_tdata({ctrl_tlast, ctrl_tdata}), 
@@ -89,10 +82,17 @@ module radio_b200
       .i_aclk(radio_clk), .i_tvalid(rmux_tvalid_r), .i_tready(rmux_tready_r), .i_tdata({rmux_tlast_r, rmux_tdata_r}), 
       .o_aclk(bus_clk), .o_tvalid(resp_tvalid), .o_tready(resp_tready), .o_tdata({resp_tlast, resp_tdata}));
    
-   axi_fifo_2clk #(.WIDTH(65), .SIZE(RADIO_FIFO_SIZE)) rx_fifo
+   axi_fifo_2clk #(.WIDTH(65), .SIZE(0)) rx_fifo
      (.reset(radio_rst),
       .i_aclk(radio_clk), .i_tvalid(rx_mux_tvalid_r), .i_tready(rx_mux_tready_r), .i_tdata({rx_mux_tlast_r, rx_mux_tdata_r}),
-      .o_aclk(bus_clk), .o_tvalid(rx_tvalid), .o_tready(rx_tready), .o_tdata({rx_tlast, rx_tdata}));
+      .o_aclk(bus_clk), .o_tvalid(rx_tvalid_int), .o_tready(rx_tready_int), .o_tdata({rx_tlast_int, rx_tdata_int}));
+   
+   axi_packet_gate #(.WIDTH(64), .SIZE(RADIO_FIFO_SIZE)) buffer_whole_pkt
+     (
+      .clk(bus_clk), .reset(bus_rst), .clear(1'b0),
+      .i_tdata(rx_tdata_int), .i_tlast(rx_tlast_int), .i_terror(1'b0), .i_tvalid(rx_tvalid_int), .i_tready(rx_tready_int),
+      .o_tdata(rx_tdata), .o_tlast(rx_tlast), .o_tvalid(rx_tvalid), .o_tready(rx_tready)
+      );
    
    // /////////////////////////////////////////////////////////////////////////////////////
    // Setting bus and controls
@@ -227,7 +227,7 @@ module radio_b200
    wire [31:0] 	  rx_sid;
    wire [11:0] 	  rx_seqnum;
    wire [63:0] rx_tdata_i; wire rx_tlast_i, rx_tvalid_i, rx_tready_i;
-
+   
    new_rx_framer #(.BASE(SR_RX_CTRL+4),.SAMPLE_FIFO_SIZE(SAMPLE_FIFO_SIZE)) new_rx_framer
      (.clk(radio_clk), .reset(radio_rst), .clear(1'b0),
       .set_stb(set_stb), .set_addr(set_addr), .set_data(set_data),
@@ -281,6 +281,11 @@ module radio_b200
       .i3_tdata(), .i3_tlast(), .i3_tvalid(1'b0), .i3_tready(),
       .o_tdata(rmux_tdata_r), .o_tlast(rmux_tlast_r), .o_tvalid(rmux_tvalid_r), .o_tready(rmux_tready_r));
 
+   // DEBUG LOGIC - NOT FOR PRODUCTION
 
    
+   assign debug = 0;
+
+   
+   
 endmodule // radio_b200