Merge FPGA repository back into UHD repository

The FPGA codebase was removed from the UHD repository in 2014 to reduce
the size of the repository. However, over the last half-decade, the
split between the repositories has proven more burdensome than it has
been helpful. By merging the FPGA code back, it will be possible to
create atomic commits that touch both FPGA and UHD codebases. Continuous
integration testing is also simplified by merging the repositories,
because it was previously difficult to automatically derive the correct
UHD branch when testing a feature branch on the FPGA repository.

This commit also updates the license files and paths therein.

We are therefore merging the repositories again. Future development for
FPGA code will happen in the same repository as the UHD host code and
MPM code.

== Original Codebase and Rebasing ==

The original FPGA repository will be hosted for the foreseeable future
at its original local location: https://github.com/EttusResearch/fpga/

It can be used for bisecting, reference, and a more detailed history.

The final commit from said repository to be merged here is
05003794e2da61cabf64dd278c45685a7abad7ec. This commit is tagged as
v4.0.0.0-pre-uhd-merge.

If you have changes in the FPGA repository that you want to rebase onto
the UHD repository, simply run the following commands:

- Create a directory to store patches (this should be an empty
  directory):

    mkdir ~/patches

- Now make sure that your FPGA codebase is based on the same state as
  the code that was merged:

    cd src/fpga # Or wherever your FPGA code is stored
    git rebase v4.0.0.0-pre-uhd-merge

  Note: The rebase command may look slightly different depending on what
  exactly you're trying to rebase.

- Create a patch set for your changes versus v4.0.0.0-pre-uhd-merge:

    git format-patch v4.0.0.0-pre-uhd-merge -o ~/patches

  Note: Make sure that only patches are stored in your output directory.
  It should otherwise be empty. Make sure that you picked the correct
  range of commits, and only commits you wanted to rebase were exported
  as patch files.

- Go to the UHD repository and apply the patches:

    cd src/uhd # Or wherever your UHD repository is stored
    git am --directory fpga ~/patches/*
    rm -rf ~/patches # This is for cleanup

== Contributors ==

The following people have contributed mainly to these files (this list
is not complete):

Co-authored-by: Alex Williams <alex.williams@ni.com>
Co-authored-by: Andrej Rode <andrej.rode@ettus.com>
Co-authored-by: Ashish Chaudhari <ashish@ettus.com>
Co-authored-by: Ben Hilburn <ben.hilburn@ettus.com>
Co-authored-by: Ciro Nishiguchi <ciro.nishiguchi@ni.com>
Co-authored-by: Daniel Jepson <daniel.jepson@ni.com>
Co-authored-by: Derek Kozel <derek.kozel@ettus.com>
Co-authored-by: EJ Kreinar <ej@he360.com>
Co-authored-by: Humberto Jimenez <humberto.jimenez@ni.com>
Co-authored-by: Ian Buckley <ian.buckley@gmail.com>
Co-authored-by: Jörg Hofrichter <joerg.hofrichter@ni.com>
Co-authored-by: Jon Kiser <jon.kiser@ni.com>
Co-authored-by: Josh Blum <josh@joshknows.com>
Co-authored-by: Jonathon Pendlum <jonathan.pendlum@ettus.com>
Co-authored-by: Martin Braun <martin.braun@ettus.com>
Co-authored-by: Matt Ettus <matt@ettus.com>
Co-authored-by: Michael West <michael.west@ettus.com>
Co-authored-by: Moritz Fischer <moritz.fischer@ettus.com>
Co-authored-by: Nick Foster <nick@ettus.com>
Co-authored-by: Nicolas Cuervo <nicolas.cuervo@ettus.com>
Co-authored-by: Paul Butler <paul.butler@ni.com>
Co-authored-by: Paul David <paul.david@ettus.com>
Co-authored-by: Ryan Marlow <ryan.marlow@ettus.com>
Co-authored-by: Sugandha Gupta <sugandha.gupta@ettus.com>
Co-authored-by: Sylvain Munaut <tnt@246tNt.com>
Co-authored-by: Trung Tran <trung.tran@ettus.com>
Co-authored-by: Vidush Vishwanath <vidush.vishwanath@ettus.com>
Co-authored-by: Wade Fife <wade.fife@ettus.com>

8 files changed, 615 insertions, 0 deletions

diff --git a/fpga/usrp3/top/b200/sim/b200_io_tb.v b/fpga/usrp3/top/b200/sim/b200_io_tb.v
new file mode 100644
index 000000000..647612a2d
--- /dev/null
+++ b/fpga/usrp3/top/b200/sim/b200_io_tb.v
@@ -0,0 +1,155 @@
+`timescale 1ns/1ps
+
+  module b200_io_tb();
+
+   //
+   // Xilinx Mandatory Simulation Primitive for global signals.
+   //
+   wire        GSR, GTS;
+   glbl glbl( );
+
+   //
+   // Test bench declarations
+   //
+   reg [7:0]   count;
+   wire [11:0] i0 = {4'hA,count};
+   wire [11:0] q0 = {4'hB,count};
+   wire [11:0] i1 = {4'hC,count};
+   wire [11:0] q1 = {4'hD,count};
+   reg 	       tb_clk = 0;
+
+   // RX sample bus.
+   reg 	       rx_clk = 0;  // Simulated clock from AD9361 for RX sample interface, radio_clk derived from this.
+   reg 	       rx_frame;
+   reg [11:0]  rx_data;
+   // TX sample bus.
+   wire        tx_clk;
+   wire        tx_frame;
+   wire [11:0] tx_data;
+   // Internal FPGA interface(s)
+   reg 	       reset  = 1;
+   wire        radio_clk;
+   reg 	       mimo;
+   wire [11:0] rx_i0, rx_q0, rx_i1, rx_q1;
+   reg [11:0] tx_i0, tx_q0, tx_i1, tx_q1;
+
+
+   // Set tb_clk to 100MHz.
+   // rx_clk is half the frequency of tb_clk, and tb_clk posedges are miday between edges on the rx_clk
+   always #10 tb_clk = ~tb_clk;
+   always @(negedge tb_clk) rx_clk <= ~rx_clk;
+
+
+   b200_io dut
+     (
+     .reset(reset),
+     .mimo(mimo),
+
+     // Baseband sample interface
+     .radio_clk(radio_clk),
+     .rx_i0(rx_i0),
+     .rx_q0(rx_q0),
+     .rx_i1(rx_i1),
+     .rx_q1(rx_q1),
+     .tx_i0(tx_i0),
+     .tx_q0(tx_q0),
+     .tx_i1(tx_i1),
+     .tx_q1(tx_q1),
+
+     // Catalina interface
+     .rx_clk(rx_clk),
+     .rx_frame(rx_frame),
+     .rx_data(rx_data),
+     .tx_clk(tx_clk),
+     .tx_frame(tx_frame),
+     .tx_data(tx_data)
+     );
+
+   // Internal Loopback Rx -> Tx.
+   always @(posedge radio_clk)
+     begin
+	tx_i0 <= rx_i0;
+	tx_q0 <= rx_q0;
+	tx_i1 <= rx_i1;
+	tx_q1 <= rx_q1;
+     end
+
+   //
+   // Task's for stimulus
+   //
+
+   task siso_burst;
+      input [7:0] len;
+      begin
+	 rx_frame <= 0;
+	 mimo <= 0;
+	 count <= 0;
+	 // Now give configuration a chance to perculate
+	 @(posedge rx_clk);
+	 @(posedge rx_clk);
+	 @(posedge rx_clk);
+	 @(posedge rx_clk);
+	 // Now entering main stimulus loop just after rising edge of rx_clk
+	 repeat(len)
+	   begin
+	      // Drive I data so that it surrounds a falling edge on rx_clk
+	      @(posedge tb_clk);
+	      rx_data <= i0;
+	      rx_frame <= 1;
+	      // Drive Q data so that it surrounds a rising edge on rx_clk
+	      @(posedge tb_clk);
+	      rx_data <= q0;
+	      rx_frame <= 0;
+	      // Increment test data pattern
+	      count <= count + 1;
+	   end // repeat (len)
+	 @(posedge rx_clk);
+	 @(posedge rx_clk);
+      end
+
+   endtask // BURST
+
+
+   task mimo_burst;
+      input [7:0] len;
+      begin
+	 rx_frame <= 0;
+	 mimo <= 1;
+	 count <= 0;
+	 // Now give configuration a chance to perculate
+	 @(posedge rx_clk);
+	 @(posedge rx_clk);
+	 @(posedge rx_clk);
+	 @(posedge rx_clk);
+	 // Now entering main stimulus loop just after rising edge of rx_clk
+	 repeat(len)
+	   // REMEMBER! B210 PCB markings for radio channels are swapped w.r.t AD9361's channels.
+	   // "Ch0" as indicated here is "Ch1" inside AD9361
+	   begin
+	      // Drive I data for Ch1 so that it surrounds a falling edge on rx_clk
+	      @(posedge tb_clk);
+	      rx_data <= i1;
+	      rx_frame <= 1;
+	      // Drive Q data for Ch1 so that it surrounds a rising edge on rx_clk
+	      @(posedge tb_clk);
+	      rx_data <= q1;
+	      // Drive I data for Ch0 so that it surrounds a falling edge on rx_clk
+	      @(posedge tb_clk);
+	      rx_data <= i0;
+	      rx_frame <= 0;
+	      // Drive Q data for Ch0 so that it surrounds a rising edge on rx_clk
+	      @(posedge tb_clk);
+	      rx_data <= q0;
+	      // Increment test data pattern
+	      count <= count + 1;
+	   end
+	 @(posedge rx_clk);
+	 @(posedge rx_clk);
+      end
+   endtask // MIMO_BURST
+
+   // Pull in local simulation script here.
+`include "simulation_script.v"
+
+
+endmodule // b200_io_tb
diff --git a/fpga/usrp3/top/b200/sim/b200_tb.v b/fpga/usrp3/top/b200/sim/b200_tb.v
new file mode 100644
index 000000000..62037ba94
--- /dev/null
+++ b/fpga/usrp3/top/b200/sim/b200_tb.v
@@ -0,0 +1,213 @@
+module b200_tb ();
+
+   wire cat_ce;
+   wire cat_miso;
+   wire cat_mosi;
+   wire cat_sclk;
+
+   wire fx3_ce;
+   wire fx3_miso;
+   wire fx3_mosi;
+   wire fx3_sclk;
+
+   wire pll_ce;
+   wire pll_mosi;
+   wire pll_sclk;
+
+   // UART
+   wire FPGA_RXD0;
+   wire FPGA_TXD0;
+
+   // Catalina Controls
+   wire codec_enable;
+   wire codec_en_agc;
+   wire codec_reset;
+   wire codec_sync;
+   wire codec_txrx;
+   wire [3:0] codec_ctrl_in;      // These should be outputs
+   wire [7:0] codec_ctrl_out;      // MUST BE INPUT
+
+   // Catalina Data
+   wire       codec_data_clk_p;          // Clock from CAT (RX)
+   wire       codec_fb_clk_p;           // Clock to CAT (TX)
+   wire [11:0] rx_codec_d;
+   wire [11:0] tx_codec_d;
+   wire        rx_frame_p;
+   wire        tx_frame_p;
+
+   wire        cat_clkout_fpga;
+
+   //always on 40MHz clock
+   wire        codec_main_clk_p;
+   wire        codec_main_clk_n;
+
+   // Debug Bus
+   wire [31:0] debug;
+   wire [1:0]  debug_clk;
+
+   // GPIF; FX3 Slave FIFO
+   wire        IFCLK;        // pclk
+   wire        FX3_EXTINT;
+   wire        GPIF_CTL0;    // n_slcs
+   wire        GPIF_CTL1;    // n_slwr
+   wire        GPIF_CTL2;    // n_sloe
+   wire        GPIF_CTL3;    // n_slrd
+   wire        GPIF_CTL7;    // n_pktend
+   wire        GPIF_CTL4;     // slfifo_flags[0]
+   wire        GPIF_CTL5;     // slfifo_flags[1]
+   wire        GPIF_CTL6;     // slfifo_flags[2]
+   wire        GPIF_CTL8;     // slfifo_flags[3]
+   wire        GPIF_CTL11;   // slfifo_addr[1]
+   wire        GPIF_CTL12;   // slfifo_addr[0]
+   wire [31:0] GPIF_D;
+   wire        GPIF_CTL9;     // global_reset
+
+   // GPS
+   wire        gps_lock;
+   wire        gps_rxd;
+   wire        gps_txd;
+   wire        gps_txd_nmea;
+
+   // LEDS
+   wire        LED_RX1;
+   wire        LED_RX2;
+   wire        LED_TXRX1_RX;
+   wire        LED_TXRX1_TX;
+   wire        LED_TXRX2_RX;
+   wire        LED_TXRX2_TX;
+
+   // Misc Hardware Control
+   wire        ref_sel;
+   wire        pll_lock;
+   wire        FPGA_CFG_CS;           // Driven by FX3 gpio.
+   wire        AUX_PWR_ON;            // Driven by FX3 gpio.
+
+   // PPS
+   wire        PPS_IN_EXT;
+   wire        PPS_IN_INT;
+
+   // RF Hardware Control
+   wire        SFDX1_RX;
+   wire        SFDX1_TX;
+   wire        SFDX2_RX;
+   wire        SFDX2_TX;
+   wire        SRX1_RX;
+   wire        SRX1_TX;
+   wire        SRX2_RX;
+   wire        SRX2_TX;
+   wire        tx_bandsel_a;
+   wire        tx_bandsel_b;
+   wire        tx_enable1;
+   wire        tx_enable2;
+   wire        rx_bandsel_a;
+   wire        rx_bandsel_b;
+   wire        rx_bandsel_c;
+
+
+   b200 b200_i1(
+		// SPI Interfaces
+		.cat_ce(),
+		.cat_miso(),
+		.cat_mosi(),
+		.cat_sclk(),
+
+		.fx3_ce(),
+		.fx3_miso(),
+		.fx3_mosi(),
+		.fx3_sclk(),
+
+		.pll_ce(),
+		.pll_mosi(),
+		.pll_sclk(),
+
+		// UART
+		.FPGA_RXD0(),
+		.FPGA_TXD0(),
+
+		// Catalina Controls
+		.codec_enable(),
+		.codec_en_agc(),
+		.codec_reset(),
+		.codec_sync(),
+		.codec_txrx(),
+		.codec_ctrl_in(),      // These should be outputs
+		.codec_ctrl_out(),      // MUST BE INPUT
+
+		// Catalina Data
+		.codec_data_clk_p(),          // Clock from CAT (RX)
+		.codec_fb_clk_p(),           // Clock to CAT (TX)
+		.rx_codec_d(),
+		.tx_codec_d(),
+		.rx_frame_p(),
+		.tx_frame_p(),
+
+		.cat_clkout_fpga(),
+
+		//always on 40MHz clock
+		.codec_main_clk_p(),
+		.codec_main_clk_n(),
+
+		// Debug Bus
+		.debug(),
+		.debug_clk(),
+
+		// GPIF, FX3 Slave FIFO
+		.IFCLK(),        // pclk
+		.FX3_EXTINT(),
+		.GPIF_CTL0(),    // n_slcs
+		.GPIF_CTL1(),    // n_slwr
+		.GPIF_CTL2(),    // n_sloe
+		.GPIF_CTL3(),    // n_slrd
+		.GPIF_CTL7(),    // n_pktend
+		.GPIF_CTL4(),     // slfifo_flags[0]
+		.GPIF_CTL5(),     // slfifo_flags[1]
+		.GPIF_CTL6(),     // slfifo_flags[2]
+		.GPIF_CTL8(),     // slfifo_flags[3]
+		.GPIF_CTL11(),   // slfifo_addr[1]
+		.GPIF_CTL12(),   // slfifo_addr[0]
+		.GPIF_D(),
+		.GPIF_CTL9(),     // global_reset
+
+		// GPS
+		.gps_lock(),
+		.gps_rxd(),
+		.gps_txd(),
+		.gps_txd_nmea(),
+
+		// LEDS
+		.LED_RX1(),
+		.LED_RX2(),
+		.LED_TXRX1_RX(),
+		.LED_TXRX1_TX(),
+		.LED_TXRX2_RX(),
+		.LED_TXRX2_TX(),
+
+		// Misc Hardware Control
+		.ref_sel(),
+		.pll_lock(),
+		.FPGA_CFG_CS(),           // Driven by FX3 gpio.
+		.AUX_PWR_ON(),            // Driven by FX3 gpio.
+
+		// PPS
+		.PPS_IN_EXT(),
+		.PPS_IN_INT(),
+
+		// RF Hardware Control
+		.SFDX1_RX(),
+		.SFDX1_TX(),
+		.SFDX2_RX(),
+		.SFDX2_TX(),
+		.SRX1_RX(),
+		.SRX1_TX(),
+		.SRX2_RX(),
+		.SRX2_TX(),
+		.tx_bandsel_a(),
+		.tx_bandsel_b(),
+		.tx_enable1(),
+		.tx_enable2(),
+		.rx_bandsel_a(),
+		.rx_bandsel_b(),
+		.rx_bandsel_c()
+		);
+
+endmodule // b200_tb
diff --git a/fpga/usrp3/top/b200/sim/b2x0/sim_b2x0_1/run_isim b/fpga/usrp3/top/b200/sim/b2x0/sim_b2x0_1/run_isim
new file mode 100755
index 000000000..dd9215934
--- /dev/null
+++ b/fpga/usrp3/top/b200/sim/b2x0/sim_b2x0_1/run_isim
@@ -0,0 +1,22 @@
+vlogcomp -work work ${XILINX}/verilog/src/glbl.v
+
+vlogcomp -work work --sourcelibext .v \
+        --sourcelibdir ../../../lib/axi \
+        --sourcelibdir ../../../lib/fifo \
+        --sourcelibdir ../../../lib/control \
+        --sourcelibdir ../../../top/b200/coregen \
+        --sourcelibdir ../../../top/b200 \
+        --sourcelibdir ../../../lib/timing \
+        --sourcelibdir ../../../lib/vita \
+        --sourcelibdir ../../../lib/packet_proc \
+        --sourcelibdir ../../../lib/dsp \
+        --sourcelibdir ../../../lib/wishbone \
+        --sourcelibdir ../../../lib/gpif2 \
+        ../../../top/b200/b200_tb.v
+
+
+
+fuse work.b200_tb work.glbl -L unisims_ver -L xilinxcorelib_ver -o b200_tb.exe
+
+# run the simulation scrip
+./b200_tb.exe  # -gui #-tclbatch simcmds.tcl
diff --git a/fpga/usrp3/top/b200/sim/sim_b200_io/mimo/mimo.wcfg b/fpga/usrp3/top/b200/sim/sim_b200_io/mimo/mimo.wcfg
new file mode 100644
index 000000000..4ecabdecf
--- /dev/null
+++ b/fpga/usrp3/top/b200/sim/sim_b200_io/mimo/mimo.wcfg
@@ -0,0 +1,112 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<wave_config>
+   <wave_state>
+   </wave_state>
+   <db_ref_list>
+      <db_ref path="./isim.wdb" id="1" type="auto">
+         <top_modules>
+            <top_module name="b200_io_tb" />
+            <top_module name="glbl" />
+         </top_modules>
+      </db_ref>
+   </db_ref_list>
+   <WVObjectSize size="4" />
+   <wvobject fp_name="group18" type="group">
+      <obj_property name="label">Test Bench</obj_property>
+      <obj_property name="DisplayName">label</obj_property>
+      <wvobject fp_name="/b200_io_tb/tb_clk" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">tb_clk</obj_property>
+         <obj_property name="ObjectShortName">tb_clk</obj_property>
+      </wvobject>
+      <wvobject fp_name="/b200_io_tb/reset" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">reset</obj_property>
+         <obj_property name="ObjectShortName">reset</obj_property>
+      </wvobject>
+      <wvobject fp_name="/b200_io_tb/mimo" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">mimo</obj_property>
+         <obj_property name="ObjectShortName">mimo</obj_property>
+      </wvobject>
+   </wvobject>
+   <wvobject fp_name="group33" type="group">
+      <obj_property name="label">RX</obj_property>
+      <obj_property name="DisplayName">label</obj_property>
+      <wvobject fp_name="/b200_io_tb/dut/rx_clk" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">rx_clk</obj_property>
+         <obj_property name="ObjectShortName">rx_clk</obj_property>
+      </wvobject>
+      <wvobject fp_name="/b200_io_tb/dut/rx_frame" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">rx_frame</obj_property>
+         <obj_property name="ObjectShortName">rx_frame</obj_property>
+      </wvobject>
+      <wvobject fp_name="/b200_io_tb/dut/rx_data" type="array" db_ref_id="1">
+         <obj_property name="ElementShortName">rx_data[11:0]</obj_property>
+         <obj_property name="ObjectShortName">rx_data[11:0]</obj_property>
+         <obj_property name="Radix">HEXRADIX</obj_property>
+      </wvobject>
+   </wvobject>
+   <wvobject fp_name="group32" type="group">
+      <obj_property name="label">TX</obj_property>
+      <obj_property name="DisplayName">label</obj_property>
+      <wvobject fp_name="/b200_io_tb/dut/tx_clk" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">tx_clk</obj_property>
+         <obj_property name="ObjectShortName">tx_clk</obj_property>
+      </wvobject>
+      <wvobject fp_name="/b200_io_tb/dut/tx_frame" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">tx_frame</obj_property>
+         <obj_property name="ObjectShortName">tx_frame</obj_property>
+      </wvobject>
+      <wvobject fp_name="/b200_io_tb/dut/tx_data" type="array" db_ref_id="1">
+         <obj_property name="ElementShortName">tx_data[11:0]</obj_property>
+         <obj_property name="ObjectShortName">tx_data[11:0]</obj_property>
+         <obj_property name="Radix">HEXRADIX</obj_property>
+      </wvobject>
+   </wvobject>
+   <wvobject fp_name="group13" type="group">
+      <obj_property name="label">Internal</obj_property>
+      <obj_property name="DisplayName">label</obj_property>
+      <wvobject fp_name="/b200_io_tb/dut/radio_clk" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">radio_clk</obj_property>
+         <obj_property name="ObjectShortName">radio_clk</obj_property>
+      </wvobject>
+      <wvobject fp_name="/b200_io_tb/dut/rx_i0" type="array" db_ref_id="1">
+         <obj_property name="ElementShortName">rx_i0[11:0]</obj_property>
+         <obj_property name="ObjectShortName">rx_i0[11:0]</obj_property>
+         <obj_property name="Radix">HEXRADIX</obj_property>
+      </wvobject>
+      <wvobject fp_name="/b200_io_tb/dut/rx_q0" type="array" db_ref_id="1">
+         <obj_property name="ElementShortName">rx_q0[11:0]</obj_property>
+         <obj_property name="ObjectShortName">rx_q0[11:0]</obj_property>
+         <obj_property name="Radix">HEXRADIX</obj_property>
+      </wvobject>
+      <wvobject fp_name="/b200_io_tb/dut/rx_i1" type="array" db_ref_id="1">
+         <obj_property name="ElementShortName">rx_i1[11:0]</obj_property>
+         <obj_property name="ObjectShortName">rx_i1[11:0]</obj_property>
+         <obj_property name="Radix">HEXRADIX</obj_property>
+      </wvobject>
+      <wvobject fp_name="/b200_io_tb/dut/rx_q1" type="array" db_ref_id="1">
+         <obj_property name="ElementShortName">rx_q1[11:0]</obj_property>
+         <obj_property name="ObjectShortName">rx_q1[11:0]</obj_property>
+         <obj_property name="Radix">HEXRADIX</obj_property>
+      </wvobject>
+      <wvobject fp_name="/b200_io_tb/dut/tx_i0" type="array" db_ref_id="1">
+         <obj_property name="ElementShortName">tx_i0[11:0]</obj_property>
+         <obj_property name="ObjectShortName">tx_i0[11:0]</obj_property>
+         <obj_property name="Radix">HEXRADIX</obj_property>
+      </wvobject>
+      <wvobject fp_name="/b200_io_tb/dut/tx_q0" type="array" db_ref_id="1">
+         <obj_property name="ElementShortName">tx_q0[11:0]</obj_property>
+         <obj_property name="ObjectShortName">tx_q0[11:0]</obj_property>
+         <obj_property name="Radix">HEXRADIX</obj_property>
+      </wvobject>
+      <wvobject fp_name="/b200_io_tb/dut/tx_i1" type="array" db_ref_id="1">
+         <obj_property name="ElementShortName">tx_i1[11:0]</obj_property>
+         <obj_property name="ObjectShortName">tx_i1[11:0]</obj_property>
+         <obj_property name="Radix">HEXRADIX</obj_property>
+      </wvobject>
+      <wvobject fp_name="/b200_io_tb/dut/tx_q1" type="array" db_ref_id="1">
+         <obj_property name="ElementShortName">tx_q1[11:0]</obj_property>
+         <obj_property name="ObjectShortName">tx_q1[11:0]</obj_property>
+         <obj_property name="Radix">HEXRADIX</obj_property>
+      </wvobject>
+   </wvobject>
+</wave_config>
diff --git a/fpga/usrp3/top/b200/sim/sim_b200_io/mimo/simulation_script.v b/fpga/usrp3/top/b200/sim/sim_b200_io/mimo/simulation_script.v
new file mode 100644
index 000000000..04e9079e1
--- /dev/null
+++ b/fpga/usrp3/top/b200/sim/sim_b200_io/mimo/simulation_script.v
@@ -0,0 +1,14 @@
+
+   initial
+     begin
+	reset <= 1;
+	mimo <= 0;
+	repeat(10) @(posedge rx_clk);
+	reset <= 0;
+	
+	repeat(10) @(posedge rx_clk);
+	
+	mimo_burst(20);
+	repeat(10) @(posedge rx_clk);
+	$finish;
+     end
diff --git a/fpga/usrp3/top/b200/sim/sim_b200_io/run_isim b/fpga/usrp3/top/b200/sim/sim_b200_io/run_isim
new file mode 100755
index 000000000..dc0ec02b7
--- /dev/null
+++ b/fpga/usrp3/top/b200/sim/sim_b200_io/run_isim
@@ -0,0 +1,22 @@
+vlogcomp -work work ${XILINX}/verilog/src/glbl.v
+
+# usrp3/top/b200/sim/sim_b200_io/siso 
+vlogcomp  -work work --sourcelibext .v \
+        --sourcelibdir ../../../../../lib/axi \
+        --sourcelibdir ../../../../../lib/fifo \
+        --sourcelibdir ../../../../../lib/control \
+        --sourcelibdir ../../../coregen \
+        --sourcelibdir ../../../ \
+        --sourcelibdir ../../../../../lib/timing \
+        --sourcelibdir ../../../../../lib/vita \
+        --sourcelibdir ../../../../../lib/packet_proc \
+        --sourcelibdir ../../../../../lib/dsp \
+        --sourcelibdir ../../../../../lib/wishbone \
+        --sourcelibdir ../../../../../lib/gpif2 \
+	--sourcelibdir ../../../../../lib/io \
+        ../../b200_io_tb.v
+
+fuse work.b200_io_tb work.glbl  -L unisims_ver -L xilinxcorelib_ver -o b200_io_tb.exe
+
+# run the simulation scrip
+./b200_io_tb.exe   -gui #-tclbatch simcmds.tcl
diff --git a/fpga/usrp3/top/b200/sim/sim_b200_io/siso/simulation_script.v b/fpga/usrp3/top/b200/sim/sim_b200_io/siso/simulation_script.v
new file mode 100644
index 000000000..ad2e7fc57
--- /dev/null
+++ b/fpga/usrp3/top/b200/sim/sim_b200_io/siso/simulation_script.v
@@ -0,0 +1,13 @@
+
+   initial
+     begin
+	reset <= 1;
+	mimo <= 0;
+	repeat(10) @(posedge rx_clk);
+	reset <= 0;
+	repeat(10) @(posedge rx_clk);
+	
+	siso_burst(20);
+	repeat(10) @(posedge rx_clk);
+	$finish;
+     end
diff --git a/fpga/usrp3/top/b200/sim/sim_b200_io/siso/siso.wcfg b/fpga/usrp3/top/b200/sim/sim_b200_io/siso/siso.wcfg
new file mode 100644
index 000000000..7ef57498f
--- /dev/null
+++ b/fpga/usrp3/top/b200/sim/sim_b200_io/siso/siso.wcfg
@@ -0,0 +1,64 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<wave_config>
+   <wave_state>
+   </wave_state>
+   <db_ref_list>
+      <db_ref path="./isim.wdb" id="1" type="auto">
+         <top_modules>
+            <top_module name="b200_io_tb" />
+            <top_module name="glbl" />
+         </top_modules>
+      </db_ref>
+   </db_ref_list>
+   <WVObjectSize size="3" />
+   <wvobject fp_name="group18" type="group">
+      <obj_property name="label">Test Bench</obj_property>
+      <obj_property name="DisplayName">label</obj_property>
+      <wvobject fp_name="/b200_io_tb/tb_clk" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">tb_clk</obj_property>
+         <obj_property name="ObjectShortName">tb_clk</obj_property>
+      </wvobject>
+      <wvobject fp_name="/b200_io_tb/reset" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">reset</obj_property>
+         <obj_property name="ObjectShortName">reset</obj_property>
+      </wvobject>
+      <wvobject fp_name="/b200_io_tb/mimo" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">mimo</obj_property>
+         <obj_property name="ObjectShortName">mimo</obj_property>
+      </wvobject>
+   </wvobject>
+   <wvobject fp_name="group33" type="group">
+      <obj_property name="label">RX</obj_property>
+      <obj_property name="DisplayName">label</obj_property>
+      <wvobject fp_name="/b200_io_tb/dut/rx_clk" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">rx_clk</obj_property>
+         <obj_property name="ObjectShortName">rx_clk</obj_property>
+      </wvobject>
+      <wvobject fp_name="/b200_io_tb/dut/rx_frame" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">rx_frame</obj_property>
+         <obj_property name="ObjectShortName">rx_frame</obj_property>
+      </wvobject>
+      <wvobject fp_name="/b200_io_tb/dut/rx_data" type="array" db_ref_id="1">
+         <obj_property name="ElementShortName">rx_data[11:0]</obj_property>
+         <obj_property name="ObjectShortName">rx_data[11:0]</obj_property>
+         <obj_property name="Radix">HEXRADIX</obj_property>
+      </wvobject>
+   </wvobject>
+   <wvobject fp_name="group32" type="group">
+      <obj_property name="label">TX</obj_property>
+      <obj_property name="DisplayName">label</obj_property>
+      <wvobject fp_name="/b200_io_tb/dut/tx_clk" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">tx_clk</obj_property>
+         <obj_property name="ObjectShortName">tx_clk</obj_property>
+      </wvobject>
+      <wvobject fp_name="/b200_io_tb/dut/tx_frame" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">tx_frame</obj_property>
+         <obj_property name="ObjectShortName">tx_frame</obj_property>
+      </wvobject>
+      <wvobject fp_name="/b200_io_tb/dut/tx_data" type="array" db_ref_id="1">
+         <obj_property name="ElementShortName">tx_data[11:0]</obj_property>
+         <obj_property name="ObjectShortName">tx_data[11:0]</obj_property>
+         <obj_property name="Radix">HEXRADIX</obj_property>
+      </wvobject>
+   </wvobject>
+</wave_config>