aboutsummaryrefslogtreecommitdiffstats
path: root/fpga/usrp3/top/b200/b200.v
diff options
context:
space:
mode:
authorBen Hilburn <ben.hilburn@ettus.com>2014-02-14 12:05:07 -0800
committerBen Hilburn <ben.hilburn@ettus.com>2014-02-14 12:05:07 -0800
commitff1546f8137f7f92bb250f685561b0c34cc0e053 (patch)
tree7fa6fd05c8828df256a1b20e2935bd3ba9899e2c /fpga/usrp3/top/b200/b200.v
parent4f691d88123784c2b405816925f1a1aef69d18c1 (diff)
downloaduhd-ff1546f8137f7f92bb250f685561b0c34cc0e053.tar.gz
uhd-ff1546f8137f7f92bb250f685561b0c34cc0e053.tar.bz2
uhd-ff1546f8137f7f92bb250f685561b0c34cc0e053.zip
Pushing the bulk of UHD-3.7.0 code.
Diffstat (limited to 'fpga/usrp3/top/b200/b200.v')
-rw-r--r--fpga/usrp3/top/b200/b200.v20
1 files changed, 5 insertions, 15 deletions
diff --git a/fpga/usrp3/top/b200/b200.v b/fpga/usrp3/top/b200/b200.v
index 3a8ece238..b25c02bdf 100644
--- a/fpga/usrp3/top/b200/b200.v
+++ b/fpga/usrp3/top/b200/b200.v
@@ -1,19 +1,7 @@
//
// Copyright 2013 Ettus Research LLC
//
-// This program is free software: you can redistribute it and/or modify
-// it under the terms of the GNU General Public License as published by
-// the Free Software Foundation, either version 3 of the License, or
-// (at your option) any later version.
-//
-// This program is distributed in the hope that it will be useful,
-// but WITHOUT ANY WARRANTY; without even the implied warranty of
-// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-// GNU General Public License for more details.
-//
-// You should have received a copy of the GNU General Public License
-// along with this program. If not, see <http://www.gnu.org/licenses/>.
-//
+
/***********************************************************
* B200 Module Declaration
@@ -250,12 +238,14 @@ module b200 (
.sclk(sclk), .sen(sen), .mosi(mosi), .miso(miso),
.rb_misc({31'b0, pll_lock}), .misc_outs(misc_outs),
- .debug_scl(GPIF_CTL8), .debug_sda(GPIF_CTL6),
- .debug_txd(FPGA_TXD0), .debug_rxd(FPGA_RXD0),
+ .debug_scl(GPIF_CTL8), .debug_sda(GPIF_CTL6),
+ .debug_txd(FPGA_TXD0), .debug_rxd(FPGA_RXD0),
.debug()
);
+
+
///////////////////////////////////////////////////////////////////////
// GPIF2
///////////////////////////////////////////////////////////////////////