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| author | michael-west <michael.west@ettus.com> | 2014-03-25 15:59:03 -0700 |
|---|---|---|
| committer | michael-west <michael.west@ettus.com> | 2014-03-25 15:59:03 -0700 |
| commit | 04292f9b109479b639add31f83fd240a6387f488 (patch) | |
| tree | 4b8723a4ae63626029704f901ee0083bb23bc1e9 /fpga/usrp3/top/b200/b200.v | |
| parent | 09915aa57bc88099cbcbbe925946ae65bc0ad8f0 (diff) | |
| parent | ff8a1252f3a51369abe0a165d963b781089ec66c (diff) | |
| download | uhd-04292f9b109479b639add31f83fd240a6387f488.tar.gz uhd-04292f9b109479b639add31f83fd240a6387f488.tar.bz2 uhd-04292f9b109479b639add31f83fd240a6387f488.zip | |
Merge branch 'master' into mwest/b200_docs
Diffstat (limited to 'fpga/usrp3/top/b200/b200.v')
| -rw-r--r-- | fpga/usrp3/top/b200/b200.v | 20 |
1 files changed, 5 insertions, 15 deletions
diff --git a/fpga/usrp3/top/b200/b200.v b/fpga/usrp3/top/b200/b200.v index 3a8ece238..b25c02bdf 100644 --- a/fpga/usrp3/top/b200/b200.v +++ b/fpga/usrp3/top/b200/b200.v @@ -1,19 +1,7 @@ // // Copyright 2013 Ettus Research LLC // -// This program is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see <http://www.gnu.org/licenses/>. -// + /*********************************************************** * B200 Module Declaration @@ -250,12 +238,14 @@ module b200 ( .sclk(sclk), .sen(sen), .mosi(mosi), .miso(miso), .rb_misc({31'b0, pll_lock}), .misc_outs(misc_outs), - .debug_scl(GPIF_CTL8), .debug_sda(GPIF_CTL6), - .debug_txd(FPGA_TXD0), .debug_rxd(FPGA_RXD0), + .debug_scl(GPIF_CTL8), .debug_sda(GPIF_CTL6), + .debug_txd(FPGA_TXD0), .debug_rxd(FPGA_RXD0), .debug() ); + + /////////////////////////////////////////////////////////////////////// // GPIF2 /////////////////////////////////////////////////////////////////////// |