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| author | Martin Braun <martin.braun@ettus.com> | 2022-02-09 12:36:54 +0100 |
|---|---|---|
| committer | Wade Fife <wade.fife@ettus.com> | 2022-02-10 11:35:47 -0700 |
| commit | 3a9f3204842d9851fef0e87b6b7d27261624a7fc (patch) | |
| tree | d4afdc77b5e83bf74a39cf5390a3b753f27aaeb8 /fpga/usrp3/top/b200/Makefile | |
| parent | 6bb7dffa4f0e16d5c51c69fb56af152dabf71236 (diff) | |
| download | uhd-3a9f3204842d9851fef0e87b6b7d27261624a7fc.tar.gz uhd-3a9f3204842d9851fef0e87b6b7d27261624a7fc.tar.bz2 uhd-3a9f3204842d9851fef0e87b6b7d27261624a7fc.zip | |
fpga: b2xx: Generate utilization report files
Currently, the build process copies the .twr and .syr files into the
build/ process after running ISE. For a succinct utilization report,
those files are not suitable, though, because they contain too much
information.
However, the build process already produces a custom, short utilization
report using grep and a summary of those reports. This patch modifies
the build such that the same output is copied into
a usrp_$product_fpga.rpt file, similar to our gen-3 devices.
Diffstat (limited to 'fpga/usrp3/top/b200/Makefile')
| -rw-r--r-- | fpga/usrp3/top/b200/Makefile | 21 |
1 files changed, 12 insertions, 9 deletions
diff --git a/fpga/usrp3/top/b200/Makefile b/fpga/usrp3/top/b200/Makefile index 8a3569e00..19d595a53 100644 --- a/fpga/usrp3/top/b200/Makefile +++ b/fpga/usrp3/top/b200/Makefile @@ -12,21 +12,22 @@ ##Output: ## build/usrp_<product>_fpga.bit: Configuration bitstream with header ## build/usrp_<product>_fpga.bin: Configuration bitstream without header -## build/usrp_<product>_fpga.syr: Xilinx system report +## build/usrp_<product>_fpga.syr: Xilinx synthesis report ## build/usrp_<product>_fpga.twr: Xilinx timing report +## build/usrp_<product>_fpga.rpt: Utilization and timing summary report # Build USRP B2x0 design with a debug UART on J400 ifeq ($(DEBUG_UART),1) OPTIONS += DEBUG_UART=1 endif -print_report = \ - echo "========================================================================"; \ - cat $(1)/b200.syr | grep "Device utilization summary:" -A 30; \ - echo "========================================================================"; \ - echo "Timing Summary:\n"; \ - cat $(1)/b200.twr | grep constraint | grep met | grep -v "*"; \ - echo "========================================================================"; +export_report = \ + echo "========================================================================" > $(2); \ + cat $(1)/b200.syr | grep "Device utilization summary:" -A 31 >> $(2); \ + echo "========================================================================" >> $(2); \ + echo "Timing Summary:\n" >> $(2); \ + cat $(1)/b200.twr | grep constraint | grep met | grep -v "*" >> $(2); \ + echo "========================================================================" >> $(2); # pre_build($1=Device) ifeq ($(EXPORT_ONLY),1) @@ -51,7 +52,8 @@ ifeq ($(PROJECT_ONLY),1) echo "\nProject Generation DONE ... $(1)\n"; else post_build = \ - @$(call print_report,build-$(1)) \ + @$(call export_report,build-$(1),build-$(1)/b200.rpt) \ + cat build-$(1)/b200.rpt; \ mkdir -p build; \ echo "Exporting bitstream files..."; \ cp build-$(1)/b200.bin build/usrp_`echo $(1) | tr A-Z a-z`_fpga.bin; \ @@ -59,6 +61,7 @@ else echo "Exporting logs..."; \ cp build-$(1)/b200.syr build/usrp_`echo $(1) | tr A-Z a-z`_fpga.syr; \ cp build-$(1)/b200.twr build/usrp_`echo $(1) | tr A-Z a-z`_fpga.twr; \ + cp build-$(1)/b200.rpt build/usrp_`echo $(1) | tr A-Z a-z`_fpga.rpt; \ echo "\nBuild DONE ... $(1)\n"; endif |