fpga: tools: Add support for RFSoC

This commit includes the following changes to the tools:
- Change part definition in XCI and BD editors for the RFSoC family
- Resolve part name in Vivado IP management utilities with
  viv_gen_part_id.py

2 files changed, 9 insertions, 9 deletions

diff --git a/fpga/usrp3/tools/scripts/setupenv_base.sh b/fpga/usrp3/tools/scripts/setupenv_base.sh
index 8a82d83ea..6ca9ff60e 100644
--- a/fpga/usrp3/tools/scripts/setupenv_base.sh
+++ b/fpga/usrp3/tools/scripts/setupenv_base.sh
@@ -325,8 +325,7 @@ function viv_create_ip {
     ip_name=$1
     ip_dir=$(readlink -f $2)
     ip_vlnv=$3
-    IFS='/' read -r -a prod_tokens <<< "${PRODUCT_ID_MAP[$4]}"
-    part_name=${prod_tokens[1]}${prod_tokens[2]}${prod_tokens[3]}
+    part_name=$(python $REPO_BASE_PATH/tools/scripts/viv_gen_part_id.py "${PRODUCT_ID_MAP[$2]}")
     if [[ -z $part_name ]]; then
         echo "ERROR: Invalid product name $4. Supported: ${!PRODUCT_ID_MAP[@]}"
         return 1
@@ -376,8 +375,7 @@ function viv_modify_bd {
     fi
 
     bd_path=$(readlink -f $1)
-    IFS='/' read -r -a prod_tokens <<< "${PRODUCT_ID_MAP[$2]}"
-    part_name=${prod_tokens[1]}${prod_tokens[2]}${prod_tokens[3]}
+    part_name=$(python $REPO_BASE_PATH/tools/scripts/viv_gen_part_id.py "${PRODUCT_ID_MAP[$2]}")
     if [[ -f $bd_path ]]; then
         $VIVADO_EXEC -mode gui -source $(resolve_viv_path $VIV_IP_UTILS) -nolog -nojournal -tclargs modify $part_name $(resolve_viv_path $bd_path)
     else
@@ -397,8 +395,7 @@ function viv_modify_tcl_bd {
     fi
 
     src_path=$(readlink -f $1)
-    IFS='/' read -r -a prod_tokens <<< "${PRODUCT_ID_MAP[$2]}"
-    part_name=${prod_tokens[1]}${prod_tokens[2]}${prod_tokens[3]}
+    part_name=$(python $REPO_BASE_PATH/tools/scripts/viv_gen_part_id.py "${PRODUCT_ID_MAP[$2]}")
     bd_ip_repo="${src_path%/top*}/lib/vivado_ipi"
     if [[ -f $src_path ]]; then
         $VIVADO_EXEC -mode gui -source $(resolve_viv_path $VIV_IP_UTILS) -nolog -nojournal -tclargs modify_bdtcl $part_name $(resolve_viv_path $src_path) $(resolve_viv_path $bd_ip_repo)
@@ -419,8 +416,7 @@ function viv_ls_ip {
         return 1
     fi
 
-    IFS='/' read -r -a prod_tokens <<< "${PRODUCT_ID_MAP[$1]}"
-    part_name=${prod_tokens[1]}${prod_tokens[2]}${prod_tokens[3]}
+    part_name=$(python $REPO_BASE_PATH/tools/scripts/viv_gen_part_id.py "${PRODUCT_ID_MAP[$2]}")
     if [[ -z $part_name ]]; then
         echo "ERROR: Invalid product name $1. Supported: ${!PRODUCT_ID_MAP[@]}"
         return 1
diff --git a/fpga/usrp3/tools/scripts/viv_ip_xci_editor.py b/fpga/usrp3/tools/scripts/viv_ip_xci_editor.py
index b749b76da..8648c8b5e 100644
--- a/fpga/usrp3/tools/scripts/viv_ip_xci_editor.py
+++ b/fpga/usrp3/tools/scripts/viv_ip_xci_editor.py
@@ -57,7 +57,11 @@ def main():
         if args.action == 'read_partid':
             print(xci_info['DEVICE'] + '/' + xci_info['PACKAGE'] + '/' + xci_info['SPEEDGRADE'] + '/' + xci_info['TEMPERATURE_GRADE'] + '/' + xci_info['SILICON_REVISION'])
         if args.action == 'read_part':
-            print(xci_info['DEVICE'] + xci_info['PACKAGE'] + xci_info['SPEEDGRADE'])
+            # The UltraScale+ RFSoC family ids are expected diferently in Vivado, a '-' must separate each property.
+            if xci_info['ARCHITECTURE'] == "zynquplusRFSOC":
+                print(xci_info['DEVICE'] + "-" + xci_info['PACKAGE'] + xci_info['SPEEDGRADE'] + "-" + xci_info['TEMPERATURE_GRADE'])
+            else:
+                print(xci_info['DEVICE'] + xci_info['PACKAGE'] + xci_info['SPEEDGRADE'])
     elif args.action == 'retarget':
         # Write a new XCI file with modified target info
         if not os.path.isdir(args.output_dir):