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author | Andrew Moch <Andrew.Moch@ni.com> | 2020-06-22 17:13:36 +0100 |
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committer | Wade Fife <wade.fife@ettus.com> | 2020-06-25 14:44:04 -0500 |
commit | c3bca6c87700054c96320de119a58f6a688dbd5a (patch) | |
tree | 5caa6aca23b6ea84335ea22398698aa1ea3569ea /fpga/usrp3/tools | |
parent | 8661f46df66329511ccb3cf083830e19d65ea402 (diff) | |
download | uhd-c3bca6c87700054c96320de119a58f6a688dbd5a.tar.gz uhd-c3bca6c87700054c96320de119a58f6a688dbd5a.tar.bz2 uhd-c3bca6c87700054c96320de119a58f6a688dbd5a.zip |
fpga: lib: Add synthesizable AXI4-Stream SV components
Components are connected together with AxiStreamIfc. Some features
include:
(1) Add bytes to the start of a packet
(2) Remove bytes from a packet
(3) Wrappers for some older components
a. fifo - buffer but imediately pass a packet
b. packet_gate - buffer and hold till end of packet
c. width_conv - cross clock domains and change width of axi bus
The AxiStreamIf was moved from PkgAxiStreamBfm to its own file. It can
be used to connect to ports with continuous assignment.
AxiStreamPacketIf must be used procedurally but allows the following
new methods:
- reached_packet_byte - notify when tdata contains a paritcular byte
- get_packet_byte/get_packet_field - extract a byte or field from axi
- put_packet_byte/put_packet_field - overwrite a byte or field onto axi
Diffstat (limited to 'fpga/usrp3/tools')
-rw-r--r-- | fpga/usrp3/tools/utils/testbenches.excludes | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/fpga/usrp3/tools/utils/testbenches.excludes b/fpga/usrp3/tools/utils/testbenches.excludes index 7ac5b134f..79c3bb557 100644 --- a/fpga/usrp3/tools/utils/testbenches.excludes +++ b/fpga/usrp3/tools/utils/testbenches.excludes @@ -13,3 +13,7 @@ top/n3xx/sim/ten_gig_eth_loopback top/x300/sim/x300_pcie_int top/n3xx/dboards/eiscat/radio/noc_block_ddc_eiscat_tb top/n3xx/dboards/eiscat/radio/noc_block_radio_core_eiscat_tb + +# These testbenches only work in ModelSim +lib/axi4s_sv/axi4s_remove_bytes_tb +lib/axi4s_sv/axi4s_add_bytes_tb |