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authorMartin Braun <martin.braun@ettus.com>2020-12-01 18:50:12 +0100
committerWade Fife <wade.fife@ettus.com>2021-01-04 13:28:36 -0600
commitca68195b5d12c5410cfac8d459a0b0902c4c72c7 (patch)
treed50d2bd7541000fa0a0470c4f1f4610c93d3b410 /fpga/usrp3/tools/utils/rfnoc-system-sim
parent3b9ced8f07c068faf1f494ce170cb44edaa47075 (diff)
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fpga: Remove Python2 support from build system
- 2to3 was used to convert the Python scripts, except where the tool choked and manual intervention was required - All references to "python" where replaced with "python3" - buffer() was replaced by memoryview()
Diffstat (limited to 'fpga/usrp3/tools/utils/rfnoc-system-sim')
-rw-r--r--fpga/usrp3/tools/utils/rfnoc-system-sim/README8
-rwxr-xr-xfpga/usrp3/tools/utils/rfnoc-system-sim/colosseum_models.py4
-rwxr-xr-xfpga/usrp3/tools/utils/rfnoc-system-sim/ni_hw_models.py4
-rw-r--r--fpga/usrp3/tools/utils/rfnoc-system-sim/rfnocsim.py4
-rwxr-xr-xfpga/usrp3/tools/utils/rfnoc-system-sim/sim_colosseum.py22
5 files changed, 21 insertions, 21 deletions
diff --git a/fpga/usrp3/tools/utils/rfnoc-system-sim/README b/fpga/usrp3/tools/utils/rfnoc-system-sim/README
index 514e9e43b..bba85c10a 100644
--- a/fpga/usrp3/tools/utils/rfnoc-system-sim/README
+++ b/fpga/usrp3/tools/utils/rfnoc-system-sim/README
@@ -1,6 +1,6 @@
Dependencies:
-- python2
- graphviz
-- python-graphviz
-- python-numpy
-- python-matplotlib
+- python3
+- python3-graphviz
+- python3-numpy
+- python3-matplotlib
diff --git a/fpga/usrp3/tools/utils/rfnoc-system-sim/colosseum_models.py b/fpga/usrp3/tools/utils/rfnoc-system-sim/colosseum_models.py
index f13b1b194..8697ee199 100755
--- a/fpga/usrp3/tools/utils/rfnoc-system-sim/colosseum_models.py
+++ b/fpga/usrp3/tools/utils/rfnoc-system-sim/colosseum_models.py
@@ -1,4 +1,4 @@
-#!/usr/bin/env python
+#!/usr/bin/env python3
#
# Copyright 2016 Ettus Research
#
@@ -16,8 +16,8 @@
# along with this program. If not, see <http://www.gnu.org/licenses/>.
#
-import rfnocsim
import math
+import rfnocsim
import ni_hw_models as hw
class ColGlobals():
diff --git a/fpga/usrp3/tools/utils/rfnoc-system-sim/ni_hw_models.py b/fpga/usrp3/tools/utils/rfnoc-system-sim/ni_hw_models.py
index 815003c5f..b8fd8dfc8 100755
--- a/fpga/usrp3/tools/utils/rfnoc-system-sim/ni_hw_models.py
+++ b/fpga/usrp3/tools/utils/rfnoc-system-sim/ni_hw_models.py
@@ -1,4 +1,4 @@
-#!/usr/bin/env python
+#!/usr/bin/env python3
#
# Copyright 2016 Ettus Research
#
@@ -16,8 +16,8 @@
# along with this program. If not, see <http://www.gnu.org/licenses/>.
#
-import rfnocsim
import math
+import rfnocsim
class UsrpX310(rfnocsim.SimComp):
# Hardware specific constants
diff --git a/fpga/usrp3/tools/utils/rfnoc-system-sim/rfnocsim.py b/fpga/usrp3/tools/utils/rfnoc-system-sim/rfnocsim.py
index d841cc06b..a55a84cd2 100644
--- a/fpga/usrp3/tools/utils/rfnoc-system-sim/rfnocsim.py
+++ b/fpga/usrp3/tools/utils/rfnoc-system-sim/rfnocsim.py
@@ -623,7 +623,7 @@ class Visualizer():
for c in sorted(comps):
comp = self.__sim_core.lookup(c)
for s in sorted(comp.get_items()):
- print(' - %s: (%s) Latency = %gs'%(s,c,comp.get_latency(s)))
+ print((' - %s: (%s) Latency = %gs' % (s, c, comp.get_latency(s))))
print('=================================================================')
def dump_debug_audit_log(self, ctype, name_filt='.*'):
@@ -645,7 +645,7 @@ class Visualizer():
status = 'WARNING (Used but Undriven)'
else:
status = 'Unused'
- print(' - %s: Status = %s'%(c,status))
+ print((' - %s: Status = %s'%(c,status)))
print('=================================================================')
def new_figure(self, grid_dims=[1,1], fignum=1, figsize=(16, 9), dpi=72):
diff --git a/fpga/usrp3/tools/utils/rfnoc-system-sim/sim_colosseum.py b/fpga/usrp3/tools/utils/rfnoc-system-sim/sim_colosseum.py
index 81ef6cbf9..8e906ba1c 100755
--- a/fpga/usrp3/tools/utils/rfnoc-system-sim/sim_colosseum.py
+++ b/fpga/usrp3/tools/utils/rfnoc-system-sim/sim_colosseum.py
@@ -1,4 +1,4 @@
-#!/usr/bin/env python
+#!/usr/bin/env python3
#
# Copyright 2016 Ettus Research
#
@@ -16,11 +16,11 @@
# along with this program. If not, see <http://www.gnu.org/licenses/>.
#
+import argparse
+import re
import rfnocsim
import ni_hw_models as hw
import colosseum_models
-import argparse
-import re
def main():
# Arguments
@@ -101,39 +101,39 @@ def main():
for u in sim_core.list_components('', '.*/' + ln):
c = sim_core.lookup(u)
m = re.match('(.+)/(SER_.*)', u)
- if (c.get_utilization('bandwidth') != master_stats[ln]):
+ if c.get_utilization('bandwidth') != master_stats[ln]:
print('[WARN] Data flowing over ' + ln + ' is probably different between ' + master_fpga + ' and ' + m.group(1))
# Visualize various metrics
vis = rfnocsim.Visualizer(sim_core)
vis.show_network()
- vis.new_figure([1,2])
+ vis.new_figure([1, 2])
vis.plot_utilization(rfnocsim.comptype.hardware, 'BEE7.*', 1)
vis.plot_utilization(rfnocsim.comptype.producer, 'USRP.*', 2)
vis.show_figure()
- vis.new_figure([1,2])
+ vis.new_figure([1, 2])
vis.plot_utilization(rfnocsim.comptype.channel, 'BEE7_000.*FPGA_NW.*EXT.*', 1)
vis.plot_utilization(rfnocsim.comptype.channel, 'BEE7_006.*FPGA_SE.*EXT.*', 2)
vis.show_figure()
- vis.new_figure([1,3])
+ vis.new_figure([1, 3])
vis.plot_utilization(rfnocsim.comptype.channel, 'BEE7_010.*FPGA_NW.*SER_EW_.*', 1)
vis.plot_utilization(rfnocsim.comptype.channel, 'BEE7_010.*FPGA_NW.*SER_NS_.*', 2)
vis.plot_utilization(rfnocsim.comptype.channel, 'BEE7_010.*FPGA_NW.*SER_XX_.*', 3)
vis.show_figure()
- vis.new_figure([1,4])
+ vis.new_figure([1, 4])
vis.plot_utilization(rfnocsim.comptype.channel, 'BEE7_000.*FPGA_NW.*EXT.*', 1)
vis.plot_utilization(rfnocsim.comptype.channel, 'BEE7_001.*FPGA_NW.*EXT.*', 2)
vis.plot_utilization(rfnocsim.comptype.channel, 'BEE7_002.*FPGA_NW.*EXT.*', 3)
vis.plot_utilization(rfnocsim.comptype.channel, 'BEE7_003.*FPGA_NW.*EXT.*', 4)
vis.show_figure()
- vis.new_figure([1,4])
+ vis.new_figure([1, 4])
vis.plot_utilization(rfnocsim.comptype.channel, 'BEE7_010.*FPGA_NW.*EXT.*', 1)
vis.plot_utilization(rfnocsim.comptype.channel, 'BEE7_010.*FPGA_NE.*EXT.*', 2)
vis.plot_utilization(rfnocsim.comptype.channel, 'BEE7_010.*FPGA_SW.*EXT.*', 3)
vis.plot_utilization(rfnocsim.comptype.channel, 'BEE7_010.*FPGA_SE.*EXT.*', 4)
vis.show_figure()
- vis.new_figure([1,2])
- vis.plot_consumption_latency('.*','.*USRP_.*', 1)
+ vis.new_figure([1, 2])
+ vis.plot_consumption_latency('.*', '.*USRP_.*', 1)
vis.plot_path_latency('tx[(0)]', '.*', 2)
vis.show_figure()
vis.plot_utilization(rfnocsim.comptype.producer, '.*MGMT_HOST.*')