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author | Wade Fife <wade.fife@ettus.com> | 2020-08-26 13:51:51 -0500 |
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committer | Wade Fife <wade.fife@ettus.com> | 2020-08-28 15:07:38 -0500 |
commit | c6bb9924e56664ccb337694f8ef485ba8245edfd (patch) | |
tree | 673fc767d9b70e11a3ddae1983d0a75356a48e21 /fpga/usrp3/sim/rfnoc | |
parent | d352f5a9c3bd3791f0320be1e615146fe7459453 (diff) | |
download | uhd-c6bb9924e56664ccb337694f8ef485ba8245edfd.tar.gz uhd-c6bb9924e56664ccb337694f8ef485ba8245edfd.tar.bz2 uhd-c6bb9924e56664ccb337694f8ef485ba8245edfd.zip |
fpga: n3xx: Update AXI interconnect address range
This change allows the entire 2 GiB address space to be accessed on
each memory port.
Diffstat (limited to 'fpga/usrp3/sim/rfnoc')
0 files changed, 0 insertions, 0 deletions