fpga: lib: Add clock domain comments to interfaces

7 files changed, 28 insertions, 13 deletions

diff --git a/fpga/usrp3/lib/axi4_sv/axi.vh b/fpga/usrp3/lib/axi4_sv/axi.vh
index c2b0c5fd0..bacddff5b 100644
--- a/fpga/usrp3/lib/axi4_sv/axi.vh
+++ b/fpga/usrp3/lib/axi4_sv/axi.vh
@@ -3,8 +3,9 @@
 //
 // SPDX-License-Identifier: LGPL-3.0-or-later
 //
-// Header File: AxiIf.vh
-// Description: Macros for use with AXI4(FULL)
+// Header File: axi.vh
+//
+// Description: Macros for use with AxiIf (AXI4 full)
 //
 
 //-----------------------------------------------------------------------------
diff --git a/fpga/usrp3/lib/axi4s_sv/axi4s_fifo.sv b/fpga/usrp3/lib/axi4s_sv/axi4s_fifo.sv
index d312b6f32..647e1dc1c 100644
--- a/fpga/usrp3/lib/axi4s_sv/axi4s_fifo.sv
+++ b/fpga/usrp3/lib/axi4s_sv/axi4s_fifo.sv
@@ -14,6 +14,7 @@
 module axi4s_fifo #(
   int SIZE  = 1 // default size set to one to act as a pipe phase
  ) (
+  // Clock domain: i.clk (o.clk is unused)
   input logic clear=1'b0,
   interface   i,  // AxiStreamIf or AxiStreamPacketIf
   interface   o,  // AxiStreamIf or AxiStreamPacketIf
diff --git a/fpga/usrp3/lib/rfnoc/xport_sv/chdr_xport_adapter.sv b/fpga/usrp3/lib/rfnoc/xport_sv/chdr_xport_adapter.sv
index f757ddf5e..178215195 100644
--- a/fpga/usrp3/lib/rfnoc/xport_sv/chdr_xport_adapter.sv
+++ b/fpga/usrp3/lib/rfnoc/xport_sv/chdr_xport_adapter.sv
@@ -45,18 +45,18 @@ module chdr_xport_adapter #(
   int          NODE_INST    = 0,
   bit          ALLOW_DISC   = 1
 )(
-  // Device info
+  // Device info (domain: eth_rx.clk)
   input  logic [15:0] device_id,
-  // Device addresses
+  // Device addresses (domain: eth_rx.clk)
   input  logic [47:0] my_mac,
   input  logic [31:0] my_ip,
   input  logic [15:0] my_udp_chdr_port,
 
-  // Ethernet
+  // Ethernet (domain: eth_rx.clk)
   AxiStreamIf.slave  eth_rx, // tUser={*not used*}
   AxiStreamIf.master eth_tx, // tUser={1'b0,trailing bytes}
 
-  // CHDR
+  // CHDR (domain: eth_rx.clk)
   AxiStreamIf.slave  v2e,  // tUser={*not used*}
   AxiStreamIf.master e2v   // tUser={*not used*}
 );
diff --git a/fpga/usrp3/lib/rfnoc/xport_sv/eth_ipv4_add_udp.sv b/fpga/usrp3/lib/rfnoc/xport_sv/eth_ipv4_add_udp.sv
index 07d5f9932..34e0dba1f 100644
--- a/fpga/usrp3/lib/rfnoc/xport_sv/eth_ipv4_add_udp.sv
+++ b/fpga/usrp3/lib/rfnoc/xport_sv/eth_ipv4_add_udp.sv
@@ -24,6 +24,8 @@ module eth_ipv4_add_udp #(
   logic [15:0] FLAG_FRAG = { 3'b010 /* don't fragment */, 13'h0 },
   logic [15:0] TTL_PROT = { 8'h10 /* TTL */, 8'h11 /* UDP */ }
 )(
+  // Clock domain: i.clk (o_.clk is unused)
+
   // Device addresses
   input  logic [47:0] mac_src,
   input  logic [31:0] ip_src,
diff --git a/fpga/usrp3/lib/rfnoc/xport_sv/eth_ipv4_chdr_adapter.sv b/fpga/usrp3/lib/rfnoc/xport_sv/eth_ipv4_chdr_adapter.sv
index 355cafb8b..c452b1631 100644
--- a/fpga/usrp3/lib/rfnoc/xport_sv/eth_ipv4_chdr_adapter.sv
+++ b/fpga/usrp3/lib/rfnoc/xport_sv/eth_ipv4_chdr_adapter.sv
@@ -25,7 +25,8 @@
 //   - PREAMBLE_BYTES: Number of bytes of Preamble expected
 //   - ADD_SOF: Add a SOF indication into the tuser field of the e2c path.
 //              If false use TKEEP instead of USER.
-//   - SYNC: Set if MAC is not the same as bus_clk
+//   - SYNC: Set if the CPU clock domain (c2e, e2c) is not the same as the
+//           Ethernet clock domain (eth_rx, eth_tx).
 //   - ENET_W: Width of the link to the Ethernet MAC
 //   - CPU_W: Width of the CPU interface
 //   - CHDR_W: Width of the CHDR interface
@@ -71,15 +72,19 @@ module eth_ipv4_chdr_adapter #(
   output logic        chdr_dropped,
   output logic        cpu_dropped,
 
-  // Ethernet MAC
+  // Ethernet MAC (domain: eth_rx.clk)
   output logic       eth_pause_req,
   AxiStreamIf.master eth_tx, // tUser = {1'b0,trailing bytes};
   AxiStreamIf.slave  eth_rx, // tUser = {error,trailing bytes};
-  // CHDR router interface
+
+  // CHDR router interface (eth_rx.clk)
   AxiStreamIf.master e2v, // tUser = {*not used*};
   AxiStreamIf.slave  v2e, // tUser = {*not used*};
+  
   // CPU DMA
+  // (domain: e2c.clk if SYNC=0, else eth_rx.clk)
   AxiStreamIf.master e2c, // tUser = {sof,trailing bytes};
+  // (domain: c2e.clk if SYNC=0, else eth_rx.clk)
   AxiStreamIf.slave  c2e  // tUser = {1'b0,trailing bytes};
 
 );
diff --git a/fpga/usrp3/lib/rfnoc/xport_sv/eth_ipv4_chdr_dispatch.sv b/fpga/usrp3/lib/rfnoc/xport_sv/eth_ipv4_chdr_dispatch.sv
index 17aaadc73..f0b4224bc 100644
--- a/fpga/usrp3/lib/rfnoc/xport_sv/eth_ipv4_chdr_dispatch.sv
+++ b/fpga/usrp3/lib/rfnoc/xport_sv/eth_ipv4_chdr_dispatch.sv
@@ -47,7 +47,8 @@ module eth_ipv4_chdr_dispatch #(
   bit DROP_MIN_PACKET  = 0,
   int ENET_W           = 64
 )(
-
+  // Clock domain: eth_rx.clk (other interface clocks are unused)
+  
   // AXI-Stream interfaces
   output logic        eth_pause_req,
   AxiStreamIf.slave   eth_rx, // tUser={error,trailing bytes};
diff --git a/fpga/usrp3/lib/rfnoc/xport_sv/eth_ipv4_interface.sv b/fpga/usrp3/lib/rfnoc/xport_sv/eth_ipv4_interface.sv
index fe6fff8c8..73ee3d94b 100644
--- a/fpga/usrp3/lib/rfnoc/xport_sv/eth_ipv4_interface.sv
+++ b/fpga/usrp3/lib/rfnoc/xport_sv/eth_ipv4_interface.sv
@@ -19,7 +19,8 @@
 //   - DROP_MIN_PACKET: Drop packets smaller than 64 bytes?
 //   - PREAMBLE_BYTES: Number of bytes of Preamble expected
 //   - ADD_SOF: Add a SOF indication into the tuser field of e2c
-//   - SYNC: Set if MAC is not the same as bus_clk
+//   - SYNC: Set if the CPU clock domain (c2e, e2c) is not the same as the
+//           Ethernet clock domain (eth_rx, eth_tx).
 //   - ENET_W: Width of the link to the Ethernet MAC
 //   - CPU_W: Width of the CPU interface
 //   - CHDR_W: Width of the CHDR interface
@@ -63,15 +64,19 @@ module eth_ipv4_interface #(
   output logic [31:0] my_ip,
   output logic [15:0] my_udp_chdr_port,
 
-  // Ethernet MAC
+  // Ethernet MAC (domain: eth_rx.clk)
   output logic       eth_pause_req,
   AxiStreamIf.master eth_tx, // tUser = {1'b0,trailing bytes};
   AxiStreamIf.slave  eth_rx, // tUser = {error,trailing bytes};
-  // CHDR router interface
+
+  // CHDR router interface (domain: eth_rx.clk)
   AxiStreamIf.master e2v, // tUser = {*not used*};
   AxiStreamIf.slave  v2e, // tUser = {*not used*};
+
   // CPU DMA
+  // (domain: e2c.clk if SYNC=0, else eth_rx.clk)
   AxiStreamIf.master e2c, // tUser = {sof,trailing bytes};
+  // (domain: c2e.clk if SYNC=0, else eth_rx.clk)
   AxiStreamIf.slave  c2e  // tUser = {1'b0,trailing bytes};
 
  );